DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Amendment to Specification
The amendment to Specification, paragraph [0030] filed on 07/06/2026 has been considered by the Examiner.
Response to Amendment
The amendment with respect to claim(s) 1-5, 8, 11-15, and 18, filed on 9/30/2026 have been fully considered for examination based on their merits. The previously presented claim(s) 6-7, 9-10, 16-17, and 19 have been considered.
Claim Objections
Claim 15 is objected to because of the following informalities: It appears an amendment is made to claim 15, however, claim 15 is marked as “Original” in the claim amendment filed on 07/06/2026. Appropriate correction is required.
Response to Arguments
Applicant’s arguments, see Remarks, pages 11-20, filed 07/06/2026, with respect to the rejection(s) of claim(s) 1-19 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of AMRANI in view of TSAO and WENG.
Regarding Claim 1. Applicant argues (see Remarks, page 14-17) that the previous Office action filed on 04/08/2026 fails to disclose or suggest the amended limitations to claim 1. More specifically, the prior art does not disclose or suggest that the under bump metallization or the UBM interconnect laterally surround the portion of the inner solder interconnect. The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior-art of TSAO teaches a semiconductor device having first metal layer and the pillar portion, wherein the first metal layer is surrounded laterally by an under bump metallization. In a similar way, the prior art of WENG teaches the inner interconnect is laterally surrounded by the UBM.
The Applicant presented a drawing, Fig. 2 on page 15 and compared it with the magnified drawing, Fig. 5 on page 16 relevant with the instant application. However, the Examiner observed some inconsistencies in labelling first inner interconnect portion, i.e. 208a of Fig. 2, with respect to the first inner solder interconnect portion, as drawn an imaginary broken line in Fig. 5. The prior art of WENG, Fig. 8 (upside down) is shown below for comparison with the Fig. 5 (magnified drawing) of the instant application.
PNG
media_image1.png
550
973
media_image1.png
Greyscale
PNG
media_image2.png
540
879
media_image2.png
Greyscale
Regarding Claims 2-19. The independent Claim(s) 11, and dependent claims 2-10, and 12-19 follow similar arguments as Claim 1, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abderrahim El Amrani et al, (hereinafter AMRANI), WO 2022174324 A1, in view of Pei-Haw Tsao et al, (hereinafter TSAO), US 20190164920 A1, and Li-Sheng Weng et al, (hereinafter WENG), US 20210125951 A1.
Regarding Claim 1, AMRANI teaches an integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]) comprising:
a die substrate (Fig. 1, 104);
a plurality of pads (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]);
a plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]) coupled and touching (annotated Figure 1) to the plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]), wherein the plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]) comprise a first pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]).
PNG
media_image3.png
940
979
media_image3.png
Greyscale
AMRANI does not explicitly disclose an integrated device, comprising: a plurality of under bump metallization interconnects coupled to and touching the plurality of pads, wherein the plurality of under bump metallization interconnects comprise a first under bump metallization interconnect.
TSAO teaches an integrated device (Fig. 2, semiconductor device, [0006]) comprising:
a plurality of under bump metallization interconnects (Figs. 1/5, 40) coupled to and touching (annotated Figure 1) the plurality of pads (Figs. 1/5, 20, bonding pads), wherein the plurality of under bump metallization interconnects (Figs. 1/5, 40) comprise a first under bump metallization interconnect (Figs. 1/5, 40).
PNG
media_image4.png
734
1017
media_image4.png
Greyscale
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified AMRANI to incorporate the teachings of TSAO such that an integrated device comprising: a plurality of under bump metallization interconnects coupled to and touching the plurality of pads, wherein the plurality of under bump metallization interconnects comprise a first under bump metallization interconnect. The above arrangement form a plurality of under bump metallizations, 40 over the bonding pads, 20 which are electrically connected to the circuitry of the substrate, 15 (TSAO, [0027], [0035]).
AMRANI as modified by TSAO does not explicitly disclose an integrated device comprising: a plurality of inner solder interconnects coupled to and touching the plurality of under bump metallization interconnects, wherein the plurality of inner solder interconnects comprise a first inner solder interconnect; and wherein the first inner solder interconnect comprises: a first inner solder interconnect portion; and a second inner solder interconnect portion; wherein the first inner solder interconnect portion of the first inner solder interconnect is coupled to and touches the first under bump metallization interconnect, wherein a portion of the first under bump metallization interconnect at least partially laterally surrounds the first inner solder interconnect portion of the first inner solder interconnect, and wherein a portion of the first pillar shell interconnect at least partially laterally surrounds the second inner solder interconnect portion of the first inner solder interconnect.
WENG teaches an integrated device (Fig. 6, 600) comprising
a plurality of inner solder interconnects (Fig. 8, 210, inner interconnect) coupled to and touching (annotated inset of Figure 8) the plurality of under bump metallization interconnects (Fig. 8, 844), wherein the plurality of inner solder interconnects (Fig. 8, 210, inner interconnect) comprise a first inner solder interconnect (Fig. 8, 210, inner interconnect); and
wherein the first inner solder interconnect (Fig. 8, 210, inner interconnect) comprises:
a first inner solder interconnect portion (annotated inset of Figure 8); and
a second inner solder interconnect portion (annotated inset of Figure 8);
wherein the first inner solder interconnect portion (annotated inset of Figure 8) of the first inner solder interconnect (Fig. 8, 210, inner interconnect) is coupled to and touches (annotated inset of Figure 8) the first under bump metallization interconnect (Fig. 8, 844),
wherein a portion of the first under bump metallization interconnect (Fig. 8, 844) at least partially laterally surrounds (annotated inset of Figure 8) the first inner solder interconnect portion (annotated inset of Figure 8) of the first inner solder interconnect (Fig. 8, 210, inner interconnect), and
wherein a portion of the first pillar shell interconnect (Fig. 8, 230, conductive layer) at least partially laterally surrounds (annotated inset of Figure 8) the second inner solder interconnect portion (annotated inset of Figure 8) of the first inner solder interconnect (Fig. 8, 210, inner interconnect).
PNG
media_image5.png
664
1140
media_image5.png
Greyscale
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified AMRANI as modified by TSAO to incorporate the teachings of WENG such that an integrated device comprising: a plurality of inner solder interconnects coupled to and touching the plurality of under bump metallization interconnects, wherein the plurality of inner solder interconnects comprise a first inner solder interconnect; and wherein the first inner solder interconnect comprises: a first inner solder interconnect portion; and a second inner solder interconnect portion; wherein the first inner solder interconnect portion of the first inner solder interconnect is coupled to and touches the first under bump metallization interconnect, wherein a portion of the first under bump metallization interconnect at least partially laterally surrounds the first inner solder interconnect portion of the first inner solder interconnect, and wherein a portion of the first pillar shell interconnect at least partially laterally surrounds the second inner solder interconnect portion of the first inner solder interconnect. The above arrangement to couple the inner interconnect, 210 to the UBM, 844, which in turn connected to pad, 644 for interconnects (i) between integrated device and a substrate, (ii) an integrated device and a PCB, and/or (iii) a substrate and PCB (WENG, [0032]).
Though AMRANI teaches an integrated device comprising plurality of bump structures comprises a pad, solder portions, and a barrier layer as a single unit, AMRANI as modified by TSAO does not explicitly disclose an integrated device comprising “plurality” of the components of the plurality of bump structure, such as a plurality of pads, a plurality of solder interconnects, a plurality of inner solder interconnects, and a plurality of pillar shell interconnects.
WENG teaches a package (Figs. 6-11, WLP, wafer level package, [0045]) comprising “plurality” of the components of the integrated device, such as a plurality of pads (Fig. 6, 644), a plurality of solder interconnects (Fig. 6, 200a, 200b, 200c, interconnect structures), a plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), and a plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have AMRANI as modified by TSAO to incorporate the teachings of WENG such that an integrated device comprising “plurality” of the components of the plurality of bump structure, such as a plurality of pads, a plurality of solder interconnects, a plurality of inner solder interconnects, and a plurality of pillar shell interconnects, so that the plurality of interconnect structures is configured to provide an electrical path for a signal such that the signal is shielded as the signal travels through the interconnect structure, (WENG, [0006]).
Regarding Claim 2, AMRANI as modified by TSAO and WENG teaches the integrated device of claim 1.
AMRANI further teaches the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]), further comprising:
a plurality of solder interconnects (Fig. 1, 114, second solder portion, [0042]) coupled to the plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]),
wherein the plurality of solder interconnects (Fig. 1, 114, second solder portion, [0042]) are separate from the plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]).
wherein the plurality of solder interconnects (Fig. 1, 114, second solder portion, [0042]) comprise a first solder interconnect (Fig. 1, 114, second solder portion, [0042]) coupled to and touching (annotated Figure 1) the first pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]).
PNG
media_image6.png
952
979
media_image6.png
Greyscale
WENG further teaches the integrated device (Fig. 6, 600), further comprising the pluralities of the components of the integrated device such as, a plurality of under bump metallization interconnects (Fig. 8, 844), the plurality of pads (Fig. 6, 644), the plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), a plurality of solder interconnects (Fig. 6, 200a, 200b, 200c, interconnect structures), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 3, AMRANI as modified by TSAO and WENG teaches the integrated device of claim 1.
AMRANI further teaches the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]),
wherein the plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]) are located at least partially inside of the plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]),
wherein the first pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]) from the plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]) includes a first material (nickel (Ni)/nickel-copper (Ni-Cu) alloy, [0014], [0046]), and
wherein the first inner solder interconnect (Fig. 1, 112, first solder portion, [0042]) from the plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]) includes a second material (tin (Sn, [0012]) that is different from the first material nickel (Ni)/nickel-copper (Ni-Cu) alloy, [0014], [0046]).
WENG further teaches the integrated device (Fig. 6, 600), further comprising the pluralities of the components of the integrated device such as, the plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 4, AMRANI as modified by TSAO and WENG teaches the integrated device (of claim 1.
AMRANI further teaches the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]),
wherein the plurality of pads (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]) comprise a first pad (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]) and a second pad (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]),
wherein the plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]) further comprise a second inner solder interconnect (Fig. 1, 112, first solder portion, [0042]), and
wherein the plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]) further comprise a second pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]).
WENG further teaches the integrated device (Fig. 6, 600), further comprising the pluralities of the components of the integrated device such as, the plurality of pads (Fig. 6, 644), the plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
WENG further teaches the integrated device (Fig. 6, 600),
wherein the first inner solder interconnect portion (annotated inset of Figure 8) of the first inner solder interconnect (Fig. 8, 210, inner interconnect) has a first width (annotated inset of Figure 8),
wherein the second inner solder interconnect portion (annotated inset of Figure 8) of the first inner solder interconnect (Fig. 8, 210, inner interconnect) has a second width that is greater than the first width (annotated inset of Figure 8).
PNG
media_image7.png
562
973
media_image7.png
Greyscale
Regarding Claim 5, AMRANI as modified by TSAO and WENG teaches the integrated device of claim 4.
TSAO further teaches the integrated device (Fig. 2, semiconductor device, [0006],
wherein the first under bump metallization interconnect (Figs. 1/5, 40) is coupled to the first pad (Figs. 1/5, 20, bonding pads), and
wherein the plurality of under bump metallization interconnects (Figs. 1/5, 40) further comprise a second under bump metallization interconnect (Figs. 1/5, 40) coupled to the second pad (Figs. 1/5, 20, bonding pads), and
AMRANI further teaches the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]), further comprising:
wherein the second inner solder interconnect (Fig. 1, 112, first solder portion, [0042]) is coupled to and touching the second under bump metallization interconnect (Fig. 1, 108, under bump metallurgy (UBM) layer, [0039]) and the second pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]).
WENG further teaches the integrated device (Fig. 6, 600), further comprising the pluralities of the components of the integrated device such as, a plurality of under bump metallization interconnects (Fig. 8, 844), the plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 6, AMRANI as modified by TSAO and WENG teaches the integrated device of claim 4.
AMRANI further teaches the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]),
wherein the first inner solder interconnect (Fig. 1, 112, first solder portion, [0042]) is located between the first pad (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]) and the first pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]), and
wherein the second inner solder interconnect (Fig. 1, 112, first solder portion, [0042]) is located between the second pad (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]) and the second pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]).
WENG further teaches the integrated device (Fig. 6, 600), further comprising the pluralities of the components of the integrated device such as, the plurality of pads (Fig. 6, 644), the plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 7, AMRANI as modified by TSAO and WENG teaches the integrated device of claim 4.
AMRANI further teaches the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]).,
wherein the first pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]) and the second pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]) are touching a passivation layer (Fig. 1, the UBM layer, 108 may comprise one or more layers of material disposed over a passivation layer (not shown) applied to the substrate, 104, [0040]) of the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]).
WENG further teaches the integrated device (Fig. 6, 600), further comprising the pluralities of the components of the integrated device such as the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 8, AMRANI as modified by TSAO and WENG teaches the integrated device of claim 4.
AMRANI further teaches the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]), comprising a plurality of solder interconnects (Fig. 1, 114, second solder portion, [0042]) that comprise first solder interconnect (Figs. 1/2A, 114, second solder portion, [0042]),
wherein the first pillar shell interconnect (Figs. 1/2A, 116, barrier layer, [0042]) includes a first lateral portion (annotated Figure 2A) and a first top portion (annotated Figure 2A),
wherein the first top portion (annotated Figure 2A) comprises a first outer top surface (annotated Figure 2A) and a first inner top surface (annotated Figure 2A),
wherein the first inner solder interconnect (Figs. 1/2A, 112, first solder portion, [0042]) touches the first inner top surface (annotated Figure 2A), and
wherein the first solder interconnect (Figs. 1/2A, 114, second solder portion, [0042]) touches the first outer top surface (annotated Figure 2A).
PNG
media_image8.png
862
1201
media_image8.png
Greyscale
WENG further teaches the integrated device (Fig. 6, 600), further comprising the pluralities of the components of the integrated device such as, the plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), a plurality of solder interconnects (Fig. 6, 200a, 200b, 200c, interconnect structures), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 9, AMRANI as modified by TSAO and WENG teaches the integrated device of claim 1.
AMRANI further teaches the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]), further comprising a die interconnection portion (Fig. 1, BEOL (not shown), [0049]) coupled to the die substrate (Fig. 1, 104), wherein the plurality of pads (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]) are coupled to the die interconnection portion (Fig. 1, BEOL (not shown), [0049]).
WENG further teaches the integrated device (Fig. 6, 600), further comprising the pluralities of the components of the integrated device such as, the plurality of pads (Fig. 6, 644).
Regarding Claim 10, AMRANI as modified by TSAO and WENG teaches the integrated device of claim 1.
AMRANI further teaches the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]), wherein the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]) is part of a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle (IC device (e.g. memory device, a system-on-chip device, a logic device, an input/output device, and the like, [0038]).
Regarding Claim 11, AMRANI teaches a package (Fig. 1, 100, plurality of bump structure/solder bump structure that is used to join an IC chip or semiconductor chip or a pad, 102 to a substrate (not shown) to form a flip chip packaging assembly (also referred to as a “flip chip packaging”), [0036]) comprising:
a substrate (Fig. 2B, 202); and
an integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]) coupled to the substrate (Fig. 2B, 202) through at least a plurality of solder interconnects (Fig. 1, 114, second solder portion, [0042]), wherein the integrated device comprises device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]):
a die substrate (Fig. 1, 104);
a plurality of pads (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]);
a plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]) coupled and touching (annotated Figure 1) to the plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]),
PNG
media_image3.png
940
979
media_image3.png
Greyscale
wherein the plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]) comprise a first shell interconnect (Fig. 1, 116, barrier layer, [0042]) coupled to the first inner solder interconnect (Fig. 1, 112, first solder portion, [0042]),
Wherein the plurality of solder interconnects (Fig. 1, 114, second solder portion, [0042]) are coupled to and touching (annotated Figure 1) the plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]).
PNG
media_image9.png
940
979
media_image9.png
Greyscale
AMRANI does not explicitly disclose a package, comprising: a plurality of under bump metallization interconnects coupled to and touching the plurality of pads, wherein the plurality of under bump metallization interconnects comprise a first under bump metallization interconnect.
TSAO teaches a package (Fig. 2, semiconductor device, [0006]) comprising:
a plurality of under bump metallization interconnects (Figs. 1/5, 40) coupled to and touching (annotated Figure 1) the plurality of pads (Figs. 1/5, 20, bonding pads), wherein the plurality of under bump metallization interconnects (Figs. 1/5, 40) comprise a first under bump metallization interconnect (Figs. 1/5, 40).
PNG
media_image4.png
734
1017
media_image4.png
Greyscale
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified AMRANI to incorporate the teachings of TSAO such that a package comprising: a plurality of under bump metallization interconnects coupled to and touching the plurality of pads, wherein the plurality of under bump metallization interconnects comprise a first under bump metallization interconnect. The above arrangement form a plurality of under bump metallizations, 40 over the bonding pads, 20 which are electrically connected to the circuitry of the substrate, 15 (TSAO, [0027], [0035]).
AMRANI as modified by TSAO does not explicitly disclose a package comprising: a plurality of inner solder interconnects coupled to and touching the plurality of under bump metallization interconnects, wherein the plurality of inner solder interconnects comprise a first inner solder interconnect; and wherein the first inner solder interconnect comprises: a first inner solder interconnect portion; and a second inner solder interconnect portion; wherein the first inner solder interconnect portion of the first inner solder interconnect is coupled to and touches the first under bump metallization interconnect, wherein a portion of the first under bump metallization interconnect at least partially laterally surrounds the first inner solder interconnect portion of the first inner solder interconnect, and wherein a portion of the first pillar shell interconnect at least partially laterally surrounds the second inner solder interconnect portion of the first inner solder interconnect.
WENG teaches a package (Figs. 6-11, WLP, wafer level package, [0045]) comprising
a plurality of inner solder interconnects (Fig. 8, 210, inner interconnect) coupled (annotated inset of Figure 8) to the plurality of under bump metallization interconnects (Fig. 8, 844),
wherein the plurality of inner solder interconnects (Fig. 8, 210, inner interconnect) comprise a first inner solder interconnect (Fig. 8, 210, inner interconnect); and
wherein the first inner solder interconnect (Fig. 8, 210, inner interconnect) comprises:
a first inner solder interconnect portion (annotated inset of Figure 8) comprising a first width (annotated inset of Figure 8), wherein the first inner solder interconnect portion (annotated inset of Figure 8) is coupled to and touches (annotated inset of Figure 8) the first under bump metallization interconnect (Fig. 8, 844); and
a second inner solder interconnect portion (annotated inset of Figure 8) comprising a second width (annotated inset of Figure 8) that is greater than the first width (annotated inset of Figure 8).
PNG
media_image10.png
664
1140
media_image10.png
Greyscale
PNG
media_image11.png
562
973
media_image11.png
Greyscale
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified AMRANI as modified by TSAO to incorporate the teachings of WENG such that a package comprising: a plurality of inner solder interconnects coupled to and touching the plurality of under bump metallization interconnects, wherein the plurality of inner solder interconnects comprise a first inner solder interconnect; and wherein the first inner solder interconnect comprises: a first inner solder interconnect portion; and a second inner solder interconnect portion; wherein the first inner solder interconnect portion of the first inner solder interconnect is coupled to and touches the first under bump metallization interconnect, wherein a portion of the first under bump metallization interconnect at least partially laterally surrounds the first inner solder interconnect portion of the first inner solder interconnect, and wherein a portion of the first pillar shell interconnect at least partially laterally surrounds the second inner solder interconnect portion of the first inner solder interconnect. The above arrangement to couple the inner interconnect, 210 to the UBM, 844, which in turn connected to pad, 644 for interconnects (i) between integrated device and a substrate, (ii) an integrated device and a PCB, and/or (iii) a substrate and PCB (WENG, [0032]).
Though AMRANI teaches an integrated device comprising plurality of bump structures comprises a pad, solder portions, and a barrier layer as a single unit, AMRANI as modified by TSAO does not explicitly disclose a package comprising “plurality” of the components of the plurality of bump structure, such as a plurality of pads, a plurality of solder interconnects, a plurality of inner solder interconnects, and a plurality of pillar shell interconnects.
WENG teaches a package (Figs. 6-11, WLP, wafer level package, [0045]) comprising “plurality” of the components of the integrated device, such as a plurality of pads (Fig. 6, 644), a plurality of solder interconnects (Fig. 6, 200a, 200b, 200c, interconnect structures), a plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), and a plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 12, AMRANI as modified by TSAO and WENG teaches the package of claim 11.
WENG further teaches the package (Figs. 6-11, WLP, wafer level package, [0045]), wherein a portion of the first under bump metallization interconnect (Fig. 8, 844) at least partially laterally surrounds (annotated inset of Figure 8) the first inner solder interconnect portion (annotated inset of Figure 8) of the first inner solder interconnect (Fig. 8, 210, inner interconnect).
PNG
media_image12.png
664
1140
media_image12.png
Greyscale
AMRANI further teaches the package (Fig. 1, 100, plurality of bump structure/solder bump structure that is used to join an IC chip or semiconductor chip or a pad, 102 to a substrate (not shown) to form a flip chip packaging assembly (also referred to as a “flip chip packaging”), [0036]), wherein the plurality of solder interconnects (Fig. 1, 114, second solder portion, [0042]) are separate from the plurality of inner solder interconnects (Fig. 1, 116, barrier layer, [0042]).
WENG further teaches the package (Figs. 6-11, WLP, wafer level package, [0045]) comprising “plurality” of the components of the integrated device, such as a plurality of under bump metallization interconnects (Fig. 8, 844), the plurality of pads (Fig. 6, 644), a plurality of solder interconnects (Fig. 6, 200a, 200b, 200c, interconnect structures), a plurality of inner solder interconnects (Fig. 6, 210, inner interconnect).
Regarding Claim 13, AMRANI as modified by TSAO and WENG teaches the package of claim 11.
AMRANI further teaches the package (Fig. 1, 100, plurality of bump structure/solder bump structure that is used to join an IC chip or semiconductor chip or a pad, 102 to a substrate (not shown) to form a flip chip packaging assembly (also referred to as a “flip chip packaging”), [0036]),
wherein the plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]) are located at least partially inside of the plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]),
wherein the first pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]) from the plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]) includes a first material (nickel (Ni)/nickel-copper (Ni-Cu) alloy, [0014], [0046]), and
wherein the first inner solder interconnect (Fig. 1, 112, first solder portion, [0042]) from the plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]) includes a second material (tin (Sn, [0012]) that is different from the first material nickel (Ni)/nickel-copper (Ni-Cu) alloy, [0014], [0046]).
WENG further teaches the package (Figs. 6-11, WLP, wafer level package, [0045]) comprising “plurality” of the components of the integrated device, such as the plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 14, AMRANI as modified by TSAO and WENG teaches the package of claim 11.
AMRANI further teaches the package (Fig. 1, 100, plurality of bump structure/solder bump structure that is used to join an IC chip or semiconductor chip or a pad, 102 to a substrate (not shown) to form a flip chip packaging assembly (also referred to as a “flip chip packaging”), [0036]),
wherein the plurality of pads (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]) comprise a first pad (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]) and a second pad (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]),
wherein the plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]) further comprise a second inner solder interconnect (Fig. 1, 112, first solder portion, [0042]), and
wherein the plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]) further comprise a second pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]).
WENG further teaches the package (Figs. 6-11, WLP, wafer level package, [0045]), further comprising the pluralities of the components of the integrated device such as, the plurality of pads (Fig. 6, 644), the plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 15, AMRANI as modified by TSAO and WENG teaches the package of claim 14.
TSAO further teaches the package (Fig. 2, semiconductor device, [0006],
wherein the first under bump metallization interconnect (Figs. 1/5, 40) is coupled to the first pad (Figs. 1/5, 20, bonding pads), and
wherein the plurality of under bump metallization interconnects (Figs. 1/5, 40) further comprise a second under bump metallization interconnect (Figs. 1/5, 40) coupled to the second pad (Figs. 1/5, 20, bonding pads), and
AMRANI further teaches the package (Fig. 1, 100, plurality of bump structure/solder bump structure that is used to join an IC chip or semiconductor chip or a pad, 102 to a substrate (not shown) to form a flip chip packaging assembly (also referred to as a “flip chip packaging”), [0036]), further comprising:
wherein the second inner solder interconnect (Fig. 1, 112, first solder portion, [0042]) is coupled to and touching the second under bump metallization interconnect (Fig. 1, 108, under bump metallurgy (UBM) layer, [0039]) and the second pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]).
WENG further teaches the package (Figs. 6-11, WLP, wafer level package, [0045]), further comprising the pluralities of the components of the integrated device such as, a plurality of under bump metallization interconnects (Fig. 8, 844), the plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 16, AMRANI as modified by TSAO and WENG teaches the package of claim 14.
AMRANI further teaches the package (Fig. 1, 100, plurality of bump structure/solder bump structure that is used to join an IC chip or semiconductor chip or a pad, 102 to a substrate (not shown) to form a flip chip packaging assembly (also referred to as a “flip chip packaging”), [0036]),
wherein the first inner solder interconnect (Fig. 1, 112, first solder portion, [0042]) is located between the first pad (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]) and the first pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]), and
wherein the second inner solder interconnect (Fig. 1, 112, first solder portion, [0042]) is located between the second pad (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]) and the second pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]).
WENG further teaches the package (Figs. 6-11, WLP, wafer level package, [0045]), further comprising the pluralities of the components of the integrated device such as, the plurality of pads (Fig. 6, 644), the plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 17, AMRANI as modified by TSAO and WENG teaches the package claim 14.
AMRANI further teaches the package (Fig. 1, 100, plurality of bump structure/solder bump structure that is used to join an IC chip or semiconductor chip or a pad, 102 to a substrate (not shown) to form a flip chip packaging assembly (also referred to as a “flip chip packaging”), [0036]),
wherein the first pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]) and the second pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]) are touching a passivation layer (Fig. 1, the UBM layer, 108 may comprise one or more layers of material disposed over a passivation layer (not shown) applied to the substrate, 104, [0040]) of the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]).
WENG teaches the package (Figs. 6-11, WLP, wafer level package, [0045]) comprising “plurality” of the components of the integrated device, such as the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 18, AMRANI as modified by TSAO and WENG teaches the integrated device of claim 14.
AMRANI further teaches the package (Fig. 1, 100, plurality of bump structure/solder bump structure that is used to join an IC chip or semiconductor chip or a pad, 102 to a substrate (not shown) to form a flip chip packaging assembly (also referred to as a “flip chip packaging”), [0036]), wherein the plurality of solder interconnects (Fig. 1, 114, second solder portion, [0042]) comprise a first solder interconnect (Figs. 1/2A, 114, second solder portion, [0042]),
wherein the first pillar shell interconnect (Figs. 1/2A, 116, barrier layer, [0042]) includes a first lateral portion (annotated Figure 2A) and a first top portion (annotated Figure 2A),
wherein the first top portion (annotated Figure 2A) comprises a first outer top surface (annotated Figure 2A) and a first inner top surface (annotated Figure 2A),
wherein the first inner solder interconnect (Figs. 1/2A, 112, first solder portion, [0042]) touches the first inner top surface (annotated Figure 2A), and
wherein the first solder interconnect (Figs. 1/2A, 114, second solder portion, [0042]) touches the first outer top surface (annotated Figure 2A).
PNG
media_image8.png
862
1201
media_image8.png
Greyscale
WENG further teaches the package (Figs. 6-11, WLP, wafer level package, [0045]), further comprising the pluralities of the components of the integrated device such as, the plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), a plurality of solder interconnects (Fig. 6, 200a, 200b, 200c, interconnect structures), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 19, AMRANI as modified by TSAO and WENG teaches the package of claim 11.
AMRANI further teaches the package (Fig. 1, 100, plurality of bump structure/solder bump structure that is used to join an IC chip or semiconductor chip or a pad, 102 to a substrate (not shown) to form a flip chip packaging assembly (also referred to as a “flip chip packaging”), [0036]), wherein the package is part of a device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]) selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle (IC device (e.g. memory device, a system-on-chip device, a logic device, an input/output device, and the like, [0038]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20230154878 A1 – Figure 2
STATEMENT OF RELEVANCE – The under bump metallization layer, 212 at least partially laterally surrounds the base portion, 122 as equated to first inner solder interconnect.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
