DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Claim(s) 1-19 directed to a semiconductor device, in the reply filed on 03/20/2026 is acknowledged.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 09/12/2023 and 01/30/2025 are in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure are being considered by the Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abderrahim El Amrani et al, (hereinafter AMRANI), WO 2022174324 A1, in view of Li-Sheng Weng et al, (hereinafter WENG), US 20210125951 A1.
Regarding Claim 1, AMRANI teaches an integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]) comprising:
a die substrate (Fig. 1, 104);
a plurality of pads (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]);
a plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]) coupled to the plurality of pads (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]); and
a plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]) coupled to the plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]),
wherein the plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]) are located between the plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]) and the plurality of pads (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]).
Though AMRANI teaches an integrated device comprising plurality of bump structures comprises a pad, solder portion, and a barrier layer as a single unit, AMRANI does not explicitly disclose an integrated device comprising “plurality” of the components of the plurality of bump structure, such as a plurality of pads, a plurality of inner solder interconnects, and a plurality of pillar shell interconnects.
WENG teaches an integrated device (Fig. 6, 600) comprising “plurality” of the components of the integrated device, such as a plurality of pads (Fig. 6, 644), a plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), and a plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified AMRANI to incorporate the teachings of WENG such that an integrated device comprising “plurality” of the components of the plurality of bump structure, such as a plurality of pads, a plurality of inner solder interconnects, and a plurality of pillar shell interconnects, so that the plurality of interconnect structures is configured to provide an electrical path for a signal such that the signal is shielded as the signal travels through the interconnect structure, (WENG, [0006]).
Regarding Claim 2, AMRANI as modified by WENG teaches the integrated device of claim 1.
AMRANI further teaches the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]), further comprising:
a plurality of underbump metallization interconnects (Fig. 1, 108, under bump metallurgy (UBM) layer, [0039]) coupled to the plurality of pads (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]), wherein the plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]) are coupled to the plurality of pads (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]) through the plurality of underbump metallization interconnects (Fig. 1, 108, under bump metallurgy (UBM) layer, [0039]); and
a plurality of solder interconnects (Fig. 1, 114, second solder portion, [0042]) coupled to the plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]), wherein the plurality of solder interconnects (Fig. 1, 114, second solder portion, [0042]) are separate from the plurality of inner solder interconnects (Fig. 1, 116, barrier layer, [0042]).
WENG further teaches the integrated device (Fig. 6, 600), further comprising the pluralities of the components of the integrated device such as, a plurality of underbump metallization interconnects (Fig. 8, 844), the plurality of pads (Fig. 6, 644), the plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), a plurality of solder interconnects (Fig. 6, 200a, 200b, 200c, interconnect structures), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 3, AMRANI as modified by WENG teaches the integrated device of claim 1.
AMRANI further teaches the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]),
wherein the plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]) are located at least partially inside of the plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]),
wherein a pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]) from the plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]) includes a first material (nickel (Ni)/nickel-copper (Ni-Cu) alloy, [0014], [0046]), and
wherein an inner solder interconnect (Fig. 1, 112, first solder portion, [0042]) from the plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]) includes a second material (tin (Sn, [0012]) that is different from the first material nickel (Ni)/nickel-copper (Ni-Cu) alloy, [0014], [0046]).
WENG further teaches the integrated device (Fig. 6, 600), further comprising the pluralities of the components of the integrated device such as, the plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 4, AMRANI as modified by WENG teaches the integrated device (of claim 1.
AMRANI further teaches the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]),
wherein the plurality of pads (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]) comprise a first pad (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]) and a second pad (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]),
wherein the plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]) comprise a first inner solder interconnect (Fig. 1, 112, first solder portion, [0042]) and a second inner solder interconnect (Fig. 1, 112, first solder portion, [0042]), and
wherein the plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]) comprise a first pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]) and a second pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]).
WENG further teaches the integrated device (Fig. 6, 600), further comprising the pluralities of the components of the integrated device such as, the plurality of pads (Fig. 6, 644), the plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 5, AMRANI as modified by WENG teaches the integrated device of claim 4.
AMRANI further teaches the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]), further comprising:
a first underbump metallization interconnect (Fig. 1, 108, under bump metallurgy (UBM) layer, [0039]) coupled to the first pad (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]); and
a second underbump metallization interconnect (Fig. 1, 108, under bump metallurgy (UBM) layer, [0039]) coupled to the second pad (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]),
wherein the first inner solder interconnect (Fig. 1, 112, first solder portion, [0042]) is coupled to and touching the first underbump metallization interconnect (Fig. 1, 108, under bump metallurgy (UBM) layer, [0039]) and the first pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]), and
wherein the second inner solder interconnect (Fig. 1, 112, first solder portion, [0042]) is coupled to and touching the second underbump metallization interconnect (Fig. 1, 108, under bump metallurgy (UBM) layer, [0039]) and the second pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]).
WENG further teaches the integrated device (Fig. 6, 600), further comprising the pluralities of the components of the integrated device such as, a plurality of underbump metallization interconnects (Fig. 8, 844), the plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 6, AMRANI as modified by WENG teaches the integrated device (of claim 4.
AMRANI further teaches the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]),
wherein the first inner solder interconnect (Fig. 1, 112, first solder portion, [0042]) is located between the first pad (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]) and the first pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]), and
wherein the second inner solder interconnect (Fig. 1, 112, first solder portion, [0042]) is located between the second pad (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]) and the second pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]).
WENG further teaches the integrated device (Fig. 6, 600), further comprising the pluralities of the components of the integrated device such as, the plurality of pads (Fig. 6, 644), the plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 7, AMRANI as modified by WENG teaches the integrated device of claim 4.
AMRANI further teaches the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]) of claim 4.
wherein the first pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]) and the second pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]) are touching a passivation layer (Fig. 1, the UBM layer, 108 may comprise one or more layers of material disposed over a passivation layer (not shown) applied to the substrate, 104, [0040]) of the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]).
WENG further teaches the integrated device (Fig. 6, 600), further comprising the pluralities of the components of the integrated device such as the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 8, AMRANI as modified by WENG teaches the integrated device of claim 4.
AMRANI further teaches the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]), comprising a first solder interconnect (Figs. 1/2A, 114, second solder portion, [0042]),
wherein the first pillar shell interconnect (Figs. 1/2A, 116, barrier layer, [0042]) includes a first lateral portion (annotated Figure 2A) and a first top portion (annotated Figure 2A),
wherein the first top portion (annotated Figure 2A) comprises a first outer top surface (annotated Figure 2A) and a first inner top surface (annotated Figure 2A),
wherein the first inner solder interconnect (Figs. 1/2A, 112, first solder portion, [0042]) touches the first inner top surface (annotated Figure 2A), and
wherein the first solder interconnect (Figs. 1/2A, 114, second solder portion, [0042]) touches the first outer top surface (annotated Figure 2A).
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WENG further teaches the integrated device (Fig. 6, 600), further comprising the pluralities of the components of the integrated device such as, the plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), a plurality of solder interconnects (Fig. 6, 200a, 200b, 200c, interconnect structures), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 9, AMRANI as modified by WENG teaches the integrated device of claim 1.
AMRANI further teaches the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]), further comprising a die interconnection portion (Fig. 1, BEOL (not shown), [0049]) coupled to the die substrate (Fig. 1, 104), wherein the plurality of pads (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]) are coupled to the die interconnection portion (Fig. 1, BEOL (not shown), [0049]).
WENG further teaches the integrated device (Fig. 6, 600), further comprising the pluralities of the components of the integrated device such as, the plurality of pads (Fig. 6, 644).
Regarding Claim 10, AMRANI as modified by WENG teaches the integrated device of claim 1.
AMRANI further teaches the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]), wherein the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]) is part of a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle (IC device (e.g. memory device, a system-on-chip device, a logic device, an input/output device, and the like, [0038]).
Regarding Claim 11, AMRANI teaches a package (Fig. 1, 100, plurality of bump structure/solder bump structure that is used to join an IC chip or semiconductor chip or a pad, 102 to a substrate (not shown) to form a flip chip packaging assembly (also referred to as a “flip chip packaging”), [0036]) comprising:
a substrate (Fig. 2B, 202); and
an integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]) coupled to the substrate (Fig. 2B, 202) through at least a plurality of solder interconnects (Fig. 1, 114, second solder portion, [0042]), wherein the integrated device comprises device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]):
a die substrate (Fig. 1, 104);
a plurality of pads (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]);
a plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]) coupled to the plurality of pads (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]); and
a plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]) coupled to the plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]),
wherein the plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]) are located between the plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]) and the plurality of pads (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]), and
wherein the plurality of solder interconnects (Fig. 1, 114, second solder portion, [0042]) are coupled to the plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]).
Though AMRANI teaches an integrated device comprising plurality of bump structures comprises a pad, solder portions, and a barrier layer as a single unit, AMRANI does not explicitly disclose an integrated device comprising “plurality” of the components of the plurality of bump structure, such as a plurality of pads, a plurality of solder interconnects, a plurality of inner solder interconnects, and a plurality of pillar shell interconnects.
WENG teaches a package (Figs. 6-11, WLP, wafer level package, [0045]) comprising “plurality” of the components of the integrated device, such as a plurality of pads (Fig. 6, 644), a plurality of solder interconnects (Fig. 6, 200a, 200b, 200c, interconnect structures), a plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), and a plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified AMRANI to incorporate the teachings of WENG such that an integrated device comprising “plurality” of the components of the plurality of bump structure, such as a plurality of pads, a plurality of solder interconnects, a plurality of inner solder interconnects, and a plurality of pillar shell interconnects, so that the plurality of interconnect structures is configured to provide an electrical path for a signal such that the signal is shielded as the signal travels through the interconnect structure, (WENG, [0006]).
Regarding Claim 12, AMRANI as modified by WENG teaches the package of claim 11.
AMRANI further teaches the package (Fig. 1, 100, plurality of bump structure/solder bump structure that is used to join an IC chip or semiconductor chip or a pad, 102 to a substrate (not shown) to form a flip chip packaging assembly (also referred to as a “flip chip packaging”), [0036]),
wherein the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]) further comprises a plurality of underbump metallization interconnects (Fig. 1, 108, under bump metallurgy (UBM) layer, [0039]) coupled to the plurality of pads (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]),
wherein the plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]) are coupled to the plurality of pads (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]) through the plurality of underbump metallization interconnects (Fig. 1, 108, under bump metallurgy (UBM) layer, [0039]), and
wherein the plurality of solder interconnects (Fig. 1, 114, second solder portion, [0042]) are separate from the plurality of inner solder interconnects (Fig. 1, 116, barrier layer, [0042]).
WENG teaches a package (Figs. 6-11, WLP, wafer level package, [0045]) comprising “plurality” of the components of the integrated device, such as a plurality of underbump metallization interconnects (Fig. 8, 844), the plurality of pads (Fig. 6, 644), a plurality of solder interconnects (Fig. 6, 200a, 200b, 200c, interconnect structures), a plurality of inner solder interconnects (Fig. 6, 210, inner interconnect).
Regarding Claim 13, AMRANI as modified by WENG teaches the package of claim 11.
AMRANI further teaches the package (Fig. 1, 100, plurality of bump structure/solder bump structure that is used to join an IC chip or semiconductor chip or a pad, 102 to a substrate (not shown) to form a flip chip packaging assembly (also referred to as a “flip chip packaging”), [0036]),
wherein the plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]) are located at least partially inside of the plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]),
wherein a pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]) from the plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]) includes a first material (nickel (Ni)/nickel-copper (Ni-Cu) alloy, [0014], [0046]), and
wherein an inner solder interconnect (Fig. 1, 112, first solder portion, [0042]) from the plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]) includes a second material (tin (Sn, [0012]) that is different from the first material nickel (Ni)/nickel-copper (Ni-Cu) alloy, [0014], [0046]).
WENG teaches a package (Figs. 6-11, WLP, wafer level package, [0045]) comprising “plurality” of the components of the integrated device, such as the plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 14, AMRANI as modified by WENG teaches the package of claim 11.
AMRANI further teaches a package (Fig. 1, 100, plurality of bump structure/solder bump structure that is used to join an IC chip or semiconductor chip or a pad, 102 to a substrate (not shown) to form a flip chip packaging assembly (also referred to as a “flip chip packaging”), [0036]),
wherein the plurality of pads (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]) comprise a first pad (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]) and a second pad (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]),
wherein the plurality of inner solder interconnects (Fig. 1, 112, first solder portion, [0042]) comprise a first inner solder interconnect (Fig. 1, 112, first solder portion, [0042]) and a second inner solder interconnect (Fig. 1, 112, first solder portion, [0042]), and
wherein the plurality of pillar shell interconnects (Fig. 1, 116, barrier layer, [0042]) comprise a first pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]) and a second pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]).
WENG teaches a package (Figs. 6-11, WLP, wafer level package, [0045]) comprising “plurality” of the components of the integrated device, such as the plurality of pads (Fig. 6, 644), the plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 15, AMRANI as modified by WENG teaches the package of claim 14.
AMRANI further teaches a package (Fig. 1, 100, plurality of bump structure/solder bump structure that is used to join an IC chip or semiconductor chip or a pad, 102 to a substrate (not shown) to form a flip chip packaging assembly (also referred to as a “flip chip packaging”), [0036]), further comprising:
a first underbump metallization interconnect (Fig. 1, 108, under bump metallurgy (UBM) layer, [0039]) coupled to the first pad (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]); and
a second underbump metallization interconnect (Fig. 1, 108, under bump metallurgy (UBM) layer, [0039]) coupled to the second pad (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]),
wherein the first inner solder interconnect (Fig. 1, 112, first solder portion, [0042]) is coupled to and touching the first underbump metallization interconnect (Fig. 1, 108, under bump metallurgy (UBM) layer, [0039]) and the first pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]), and
wherein the second inner solder interconnect (Fig. 1, 112, first solder portion, [0042]) is coupled to and touching the second underbump metallization interconnect (Fig. 1, 108, under bump metallurgy (UBM) layer, [0039]) and the second pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]).
WENG teaches a package (Figs. 6-11, WLP, wafer level package, [0045]) comprising “plurality” of the components of the integrated device, such as a plurality of underbump metallization interconnects (Fig. 8, 844), the plurality of pads (Fig. 6, 644), the plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 16, AMRANI as modified by WENG teaches the of claim 14.
AMRANI further teaches the package (Fig. 1, 100, plurality of bump structure/solder bump structure that is used to join an IC chip or semiconductor chip or a pad, 102 to a substrate (not shown) to form a flip chip packaging assembly (also referred to as a “flip chip packaging”), [0036]),
wherein the first inner solder interconnect (Fig. 1, 112, first solder portion, [0042]) is located between the first pad (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]) and the first pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]), and
wherein the second inner solder interconnect (Fig. 1, 112, first solder portion, [0042]) is located between the second pad (Fig. 1, 102, IC chip/semiconductor chip/pad, [0036]) and the second pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]).
WENG teaches a package (Figs. 6-11, WLP, wafer level package, [0045]) comprising “plurality” of the components of the integrated device, such as the plurality of pads (Fig. 6, 644), the plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 17, AMRANI as modified by WENG teaches the package claim 14.
AMRANI further teaches a package (Fig. 1, 100, plurality of bump structure/solder bump structure that is used to join an IC chip or semiconductor chip or a pad, 102 to a substrate (not shown) to form a flip chip packaging assembly (also referred to as a “flip chip packaging”), [0036]),
wherein the first pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]) and the second pillar shell interconnect (Fig. 1, 116, barrier layer, [0042]) are touching a passivation layer (Fig. 1, the UBM layer, 108 may comprise one or more layers of material disposed over a passivation layer (not shown) applied to the substrate, 104, [0040]) of the integrated device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]).
WENG teaches a package (Figs. 6-11, WLP, wafer level package, [0045]) comprising “plurality” of the components of the integrated device, such as the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
Regarding Claim 18, AMRANI as modified by WENG teaches the package of claim 14,
AMRANI further teaches the package (Fig. 1, 100, plurality of bump structure/solder bump structure that is used to join an IC chip or semiconductor chip or a pad, 102 to a substrate (not shown) to form a flip chip packaging assembly (also referred to as a “flip chip packaging”), [0036]), further comprising a first solder interconnect(Figs. 1/2A, 114, second solder portion, [0042]),
wherein the first pillar shell interconnect (Figs. 1/2A, 116, barrier layer, [0042]) includes a first lateral portion (annotated Figure 2A) and a first top portion (annotated Figure 2A),
wherein the first top portion (annotated Figure 2A) comprises a first outer top surface (annotated Figure 2A) and a first inner top surface (annotated Figure 2A),
wherein the first inner solder interconnect (Figs. 1/2A, 112, first solder portion, [0042]) touches the first inner top surface (annotated Figure 2A), and
wherein the first solder interconnect (Figs. 1/2A, 114, second solder portion, [0042]) touches the first outer top surface (annotated Figure 2A).
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WENG teaches a package (Figs. 6-11, WLP, wafer level package, [0045]) comprising “plurality” of the components of the integrated device, such as the plurality of solder interconnects (Fig. 6, 200a, 200b, 200c, interconnect structures), a plurality of inner solder interconnects (Fig. 6, 210, inner interconnect), the plurality of pillar shell interconnects (Fig. 6, 230, conductive layer).
.
Regarding Claim 19, AMRANI as modified by WENG teaches the package of claim 11.
AMRANI further teaches a package (Fig. 1, 100, plurality of bump structure/solder bump structure that is used to join an IC chip or semiconductor chip or a pad, 102 to a substrate (not shown) to form a flip chip packaging assembly (also referred to as a “flip chip packaging”), [0036]), wherein the package is part of a device (Fig. 1, 100, plurality of bump structures may be formed on an integrated circuit (IC) device, [0036]) selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle (IC device (e.g. memory device, a system-on-chip device, a logic device, an input/output device, and the like, [0038]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 5130779 A – Figure 17
STATEMENT OF RELEVANCE – A side view of two elongated interconnections showing the solder mass, after joining to a substrate showing that there is enough space between them to locate a signal carrier.
US 20190096836 A1 – Figure 16
STATEMENT OF RELEVANCE – Cross-sectional views that illustrate a method of forming a bump structure.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2812 /CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812
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