DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim(s) 8-13 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/22/2026.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. JP2022-146920, filed on 09/29/2023.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 6/28/2026 is/are in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7, and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harry-Hak-Lay Chuang et al, (hereinafter CHUANG), US 20220036932 A1, in view of Masaru Toko et al, (hereinafter TOKO), US 20210082999 A1.
(NOTE: For the CHUANG prior art, the identical labels are used and mapped for first (left side) and second (right side) of the elements in Figure 13. For example, MS is used as the memory stack equated for both the first and the second memory cells of the instant application; For TOKO prior art, since identical memory cells are stacked, as in Figure 1, the plurality of elements are identically labeled for the first and second elements. For example, VR is labeled for both first and second magnetoresistive effect element.)
Regarding Claim 1, CHUANG teaches a magnetic memory device (Fig. 13, MRAM devices, [0009]) comprising:
a lower insulating layer (Fig. 13, 114, ILD layer);
a first lower conductive portion (Fig. 13, 112, metallization pattern) provided in the lower insulating layer (Fig. 13, 114, ILD layer);
a second lower conductive portion (Fig. 13, 112, metallization pattern) provided in the lower insulating layer (Fig. 13, 114, ILD layer), and arranged to be apart from the first lower conductive portion (Fig. 13, 112, metallization pattern) and adjacent to the first lower conductive portion (Fig. 13, 112, metallization pattern) in a first direction (annotated Figure 13);
a first memory cell (Fig. 13, MS, memory stack) provided on the lower insulating layer (Fig. 13, 114, ILD layer) and on the first lower conductive portion (Fig. 13, 112, metallization pattern), and including a first magnetoresistance effect element, a first switching element (Figs. 2/13, 160/162, resistance switching layer, may be a magnetic tunnel junction (MTJ) structure, [0017) and a first bottom electrode (Figs. 2/13, 150/152) connected to the first lower conductive portion (Fig. 13, 112, metallization pattern) which are stacked in a second direction (annotated Figure 13) intersecting the first direction (annotated Figure 13);
a second memory cell (Fig. 13, MS, memory stack) provided on the lower insulating layer (Fig. 13, 114, ILD layer) and on the second lower conductive portion (Fig. 13, 112, metallization pattern), arranged adjacent to the first memory cell (annotated Figure 13, MS, memory stack) in the first direction (annotated Figure 13), and including a second magnetoresistance effect element, a second switching element (Figs. 2/13, 160/162, resistance switching layer, may be a magnetic tunnel junction (MTJ) structure, [0017]) and a second bottom electrode (Figs. 2/13, 150/152) connected to the second lower conductive portion (Fig. 13, 112, metallization pattern) which are stacked in the second direction (annotated Figure 13),
wherein
as viewed from a third direction (annotated Figure 13) intersecting the first (annotated Figure 13) and second directions (annotated Figure 13), a width (annotated Figure 13) of the first lower conductive portion (Fig. 13, 112, metallization pattern) in the first direction (annotated Figure 13) is less than a width (annotated Figure 13) of the first bottom electrode (Figs. 2/13, 150/152) in the first direction (Figs. 2/13, 150/152), and a width (Figs. 2/13, 150/152) of the second lower conductive portion (Fig. 13, 112, metallization pattern) in the first direction (annotated Figure 13) is less than a width (annotated Figure 13) of the second bottom electrode (Figs. 2/13, 150/152) in the first direction (annotated Figure 13), and
the lower insulating layer (Fig. 13, 114, ILD layer) has a void (Fig. 13, 200V) under a region between the first memory cell (Fig. 13, MS, memory stack) and the second memory cell (Fig. 13, MS, memory stack).
Though CHUANG teaches a magnetic memory device comprising a memory stack, with the single layer, 160/162, as a resistance switching layer, may be a magnetic tunnel junction (MTJ) structure, [0017] as mentioned above, that have been equated to two separate layers, a first/second magnetoresistance effect element (31) and a first/second switching element (32) of the instant application, due to their identical features and characteristics, CHUANG does not explicitly disclose a magnetic memory device comprising, a first/second memory cell, including a first/second magnetoresistance effect element, and a first/second switching element.
TOKO teaches a magnetic memory device (Fig. 1, 1, magnetoresistive memory device, [0068]) comprising, a first/second memory cell (Fig. 4, MC), including a first/second magnetoresistance effect element (Fig. 4, VR), and a first/second switching element (Fig. 4, SE/32, selector/variable resistance material).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHUANG to incorporate the teachings of TOKO, such that a magnetic memory device comprising, a first/second memory cell, including a first/second magnetoresistance effect element, and a first/second switching element, so that the variable resistance material, 32 (selector, SE) act as a switching element, based on the threshold value of the voltage applied, the device switching from the high-resistance state to low-resistance state or vice-versa for the electrically conductive or insulative, and further the magnetoresistive effect element, VR of a memory cell (MC) record the data reading through the MC based on the aforementioned resistance switching states (TOKO, [0046-0047], [0053]),
Regarding Claim 2, CHUANG as modified by TOKO teaches the magnetic memory device of claim 1.
CHUANG further teaches the magnetic memory device (Fig. 1, 1, magnetoresistive memory device, [0068]), wherein
the first lower conductive portion (Fig. 13, 112, metallization pattern) is a first lower wiring line (Fig. 13, 140, bottom electrode vias (BEVA), [0014]) extending along the third direction (annotated Figure 13 above; X direction);
the second lower conductive portion (Fig. 13, 112, metallization pattern) is a second lower wiring line (Fig. 13, 140, bottom electrode vias (BEVA), [0014]) extending along the third direction (annotated Figure 13 above; X direction). and the void (Fig. 13, 200V) is located between the first lower wiring line (Fig. 13, 140, bottom electrode vias (BEVA), [0014]) and the second lower wiring line (Fig. 13, 140, bottom electrode vias (BEVA), [0014]) and extends along the third direction (annotated Figure 13 above; X direction).
Regarding Claim 3, CHUANG as modified by TOKO teaches the magnetic memory device of claim 2.
CHUANG further teaches the magnetic memory device (Fig. 1, 1, magnetoresistive memory device, [0068]), wherein
the first bottom electrode (Fig. 13, 152) is provided on the lower insulating layer (Fig. 13, 114, ILD layer) and on the first lower wiring line (Fig. 13, 140, bottom electrode vias (BEVA), [0014]), and
the second bottom electrode (Fig. 13, 152) is provided on the lower insulating layer (Fig. 13, 114, ILD layer) and on the second lower wiring line (Fig. 13, 140, bottom electrode vias (BEVA), [0014]).
Regarding Claim 4, CHUANG as modified by TOKO teaches the magnetic memory device of claim 2.
CHUANG further teaches the magnetic memory device (Fig. 1, 1, magnetoresistive memory device, [0068]), wherein
the lower insulating layer (Fig. 13, 114, ILD layer) includes:
a first insulating layer (Fig. 13, 130, the dielectric layer) formed of a first insulating material (example, SiN, [0012]) and including a pair of portions sandwiching a pair of side surfaces of the first lower wiring line (Fig. 13, 140, bottom electrode vias (BEVA), [0014]), and a pair of portions sandwiching a pair of side surfaces of the second lower wiring line (Fig. 13, 140, bottom electrode vias (BEVA), [0014]); and
a second insulating layer (Fig. 13, 206, dielectric portions) formed of a second insulating material (example, SiOx, [0027]) different from the first insulating material (example, SiN, [0012]) and including a pair of portions extending along the third direction (annotated Figure 13 above; X direction) along a pair of inner side surfaces of the void (Fig. 13, 200V).
Regarding Claim 5, CHUANG as modified by TOKO teaches the magnetic memory device of claim 4.
CHUANG further teaches the magnetic memory device (Fig. 1, 1, magnetoresistive memory device, [0068]), wherein
a level of an upper surface (annotated Figure 13) of the second insulating layer (Fig. 13, 206, dielectric portions) in a height direction (annotated Figure 13, Z direction) is lower than (annotated Figure 13) a level of an upper surface (annotated Figure 13) of the first insulating layer (Fig. 13, 130, the dielectric layer) in the height direction (annotated Figure 13, Z direction).
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Regarding Claim 6, CHUANG as modified by TOKO teaches the magnetic memory device of claim 4.
CHUANG further teaches the magnetic memory device (Fig. 1, 1, magnetoresistive memory device, [0068]), wherein
a bottom portion (annotated Figure 13 above) of the void (Fig. 13, 200V) is closed by the second insulating layer (Fig. 13, 206, dielectric portions).
Regarding Claim 7, CHUANG as modified by TOKO teaches the magnetic memory device of claim 4.
CHUANG further teaches the magnetic memory device (Fig. 1, 1, magnetoresistive memory device, [0068]), wherein
the lower insulating layer (Fig. 13, 114, ILD layer) further includes a third insulating layer (Fig. 13, 202, dielectric portions) formed of the second insulating material (example, SiOx, [0027]) and including a pair of portions extending along the third direction (annotated Figure 13 above; X direction) along the pair of side surfaces of the first lower wiring line (Fig. 13, 140, bottom electrode vias (BEVA), [0014]) and a pair of portions extending along the third direction (annotated Figure 13 above; X direction) along along the pair of side surfaces of the second lower wiring line (Fig. 13, 140, bottom electrode vias (BEVA), [0014]).
Regarding Claim 14, CHUANG as modified by TOKO teaches the magnetic memory device of claim 1.
TOKO further teaches a magnetic memory device (Fig. 1, 1, magnetoresistive memory device, [0068]) wherein
the first switching element (Fig. 4, SE/32, selector/variable resistance material) is provided on a lower layer side of the first magnetoresistance effect element (Fig. 4, VR) and connected to the first bottom electrode (Fig. 4, 31, lower electrode), and
the second switching element (Fig. 4, SE/32, selector/variable resistance material) is provided on a lower layer side of the second magnetoresistance effect element (Fig. 4, VR) and connected to the second bottom electrode (Fig. 4, 31, lower electrode).
Regarding Claim 15, CHUANG as modified by TOKO teaches the magnetic memory device of claim 1.
TOKO further teaches a magnetic memory device (Fig. 1, 1, magnetoresistive memory device, [0068]), wherein
each of the first and second magnetoresistance effect elements (Fig. 5, VR) includes:
a first magnetic layer (Fig. 5, 43, ferromagnet/storage layer, [0051]) having a variable magnetization direction ([0051]);
a second magnetic layer (Fig. 5, 41, ferromagnet/reference layer, [0049]) having a fixed magnetization direction ([0049]); and
a non-magnetic layer (Fig. 5, 42, insulator, [0058]) located between ([0058]) the first magnetic layer (Fig. 5, 43, ferromagnet/storage layer, [0051]) and the second magnetic layer.
Regarding Claim 16, CHUANG as modified by TOKO teaches the magnetic memory device of claim 1.
CHUANG further teaches the magnetic memory device (Fig. 1, 1, magnetoresistive memory device, [0068]), wherein
each of the first and second switching elements (Figs. 2/13, 160/162, resistance switching layer, may be a magnetic tunnel junction (MTJ) structure, [0017) changes from an off state to an on state ([0017]) when a voltage applied ([0020]) between two terminals (Fig. 13, 152/172, bottom/top electrodes) thereof becomes equal to or higher than a predetermined voltage ([0020]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20110254112 A1 – Figure 3
STATEMENT OF RELEVANCE – A cross-sectional view of the memory cell, MC with switching transistors, Tr1 and Tr2 arranged and including void (60) in between them.
US 20140284734 A1 – Figure 42
STATEMENT OF RELEVANCE – A sectional view showing structure of the magnetic random access memory having MTJ element disposed on an ILD (inter layer dielectric) and BEC (bottom electrode contact).
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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