Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Response to Amendment
The amendment filed March 24th, 2026 has for Claim 1 has been entered. Claims 1-12 remain pending.
Response to Arguments
Applicants arguments filed March 24th, 2026 have been fully considered but are not fully persuasive.
Applicant’s arguments, see Remarks pages 4-6, filed March 24th, 2026, with respect to the rejection of Claim 1 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of, the statutory basis of Claim 1 has changed and therefore its dependent within the original 102(a)(1) rejections Claims 1, 2, and 8-12 will therefore be revaluated and relayed within this document.
Applicants arguments, see Remarks pages 7-9, regarding Claims 3-7 are considered non persuasive. The arguments of the applicant merely cites how the claims included in the portion of the Non-Final rejection filed on January 26th, 2026 do not fully disclose the features of the amended Claim 1. Within a 35 U.S.C. 103 rejection, the prior references are used in combination within the art of the 35 U.S.C. 102 rejection and therefore not required to disclose all the features, but only those not expressed (see MPEP 2158). By citing the references of the 103 rejections do not disclose those of the accepted amended Claim 1, the argument is not persuasive, as those references never disclosed the independent claim in full.
In reference to the citing of nonobvious combination in Claim 7, the person of ordinary skill is also a person of ordinary creativity, and in many cases is able to fit disclosures in way that are not typically considered. Furthermore, obviousness is not whether the features of a secondary reference may be wholly incorporated into the structure of the primary reference as described, but is rather the test of the combined teachings of those references would have suggested to those of ordinary skill in the art (see MPEP 2145). For these reasons, a rejection under 35 U.S.C. 103 based on the new amended claim is not withdrawn from consideration.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ong et al. (US 2020/0006247 A1), hereinafter as O1, in view of Kim et al. (US 2022/0013475 A1), hereinafter as K1.
Regarding Claim 1, O1 discloses an electronic package (see FIG. 1, element 100, and [0014] ln. 2 “chip package 100”), comprising:
a carrier structure (FIG. 1, element 102, and [0015] ln. 1 “package substrate 102”) being defined with an encapsulation area (see FIG.1 where the encapsulation area is being defined as the area of the substrate 102 with the element 136, [0026] ln. 1 “chip 136”, see attached image below) and a functional area (see FIG. 1 where the functional area is being defined as the area to the right of the chip 136, with the elements contained in element 116 [0016] ln. 1 “stiffener 116”, see attached image below) adjacent to the encapsulation area on one side of the carrier structure (see FIG. 1 and the attached image for the described functional area being disposed adjacent to the described encapsulation area);
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an electronic element (see FIG. 1 , element 136, and [0026] ln. 1 “chip 136”) disposed on the encapsulation area of the carrier structure (see FIG. 1 where the chip 136 is disposed in the described encapsulation area) and electrically connected to the carrier structure (see FIG. 1 and [0026] ln. 2 “a chip 136, such as a logic processor or a central processing unit, that is electrically coupled to the package substrate 102”);
a heat dissipation member comprising at least one metal frame (see FIG. 1, element 116, [0016] ln. 1 “stiffener 116” and [0027] ln. 1 “stiffener 116 can be formed from an electrically conductive material…the electrically conductive material can be a conductive metal, such as copper, aluminum, stainless steel, or another suitable metal” which are heat dissipating metals), wherein the at least one metal frame is disposed on the functional area of the carrier structure (see FIG. 1 where element 16 is disposed in the described functional area) and thermally connected to the electronic element (see FIG. 1, element 110, [0015] ln. 3 “internal circuitry 110” which can be seen extending from the electronic element 136 and connecting to the metal frame element 116 through the element 126 [0020] ln. 1 “plurality of electrical connections 126 that extend through the stiffener 116”, and see [0015] ln. 13 “112 can also include dies, which can connect to the top surface 114 of the package substrate 102 through the stiffener” where the electronic component 136 and stiffer 116 are thermally connected through the substrate 102); and
O1 does not explicitly disclose an encapsulation layer formed on the encapsulation area of the carrier structure and covering the electronic element,
K1 discloses an encapsulation layer (see FIG. 12 and 13, element 33, [0055] ln. 1 “encapsulant 33” where FIG. 12 shows label for element 33 that is not described in FIG. 13 but is included in the drawing) formed on the encapsulation area of the carrier structure (see FIG. 12 and 13, where the encapsulation area of K1 is described by the left most element 33 and the right most element 33, see attached figure) and covering the electronic element (see FIG. 13, elements 120a and 120b, and [0050] “first semiconductor chip structure 120 a and a second semiconductor ship structure 120b” are enclosed by encapsulant elements 33),
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The specifically encapsulated electronic element as disclosed by K1 is incorporated as the electronic element of O1.
wherein the encapsulation layer (element 33 of K1) is free from being formed on the functional area (see FIG. 1 of O1 where the described functional area and described encapsulation area have space between them, and are not formed in contact), and the at least one metal frame on the functional area is free from being covered by any encapsulant or packaging material (see FIG. 1 of O1 where the metal frame described by element 116 is free from contact of the encapsulant present in the encapsulation area due to the gaps between elements).
It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the disclosure of K1 with O1 as there is motivation to include encapsulant surround an electronic element to yield predictable results – there is motivation to surround an electronic element with an encapsulant or packaging material for the structural integrity of the element as well as for thermal dissipation and regulation (see K1 [0055]) and this inclusion yields predictable results.
Regrading Claim 2, O1 and K1 disclose the electronic package of claim 1, where O1 further discloses wherein the carrier structure has a heat dissipation layer (see FIG. 1, elements 126 and 128, [0021] ln. 1 “least one electrical connection 126 , such as electrical connection 128…can be in direct contact with the stiffener 116” working as a heat dissipating layer within the stiffener 116) thermally connected to the electronic element (see FIG. 1 where element 126 is connected to the electronic component 136 through 110) and the heat dissipation member (as mentioned prior, elements 126 and 128 can be in direct contact with the stiffener 116).
Regarding Claim 3, O1 and K1 disclose the electronic package of claim 1, where K1 further discloses wherein a height of the electronic element (elements 120a and 120b) relative to the carrier structure is equal to a height of the encapsulation layer (element 33) relative to the carrier structure (see FIG. 13 where the elements 33, 120a and 120b are the same height relative to the carrier structure represented by 110).
Regarding Claim 4, O1 and K1 disclose the electronic package of claim 1, where O1 further discloses wherein a height of the heat dissipation member (element 116) relative to the carrier structure is equal to a height of the electronic element (element 136) relative to the carrier structure (see FIG. 1 where the elements 116 and 136 are the same height relative to the carrier structure element 102).
Regarding Claim 5, O1 and K1 disclose the electronic package of claim 1, where O1 further discloses wherein a height of the heat dissipation member (element 116) relative to the carrier structure is less than or equal to a height of the encapsulation layer (element 136) relative to the carrier structure (see FIG. 1 where the height of element 116 and 136 are equal to each other).
Regarding Claim 8, O1 and K1 disclose the electronic package of claim 1, where K1 further discloses wherein the electronic element (element 136) has a sensible heat area (Note: The examiner is interpreting heat sensible area to mean an area that conducts heat. See FIG. 1 and [0015] ln. 1 “package substrate 102 can have…solder balls” which are conductive and therefore sense heat), the carrier structure (element 102) has a functional pad corresponding to a position of the sensible heat area (see FIG. 1 and the pad underneath element 126 that is connected to the solder balls through element 110), and the electronic element is thermally connected to the heat dissipation member (element 116) via the functional pad (as mentioned prior the elements 126 and 128 can be directly connected the element 116, and therefore the electronic element 136 is connected through 110 to the pad underneath element 126 which is connected to the stiffener 116).
Regarding Claim 9, O1 and K1 disclose the electronic package of claim 1, where O1 further discloses further comprising at least one electronic module (see FIG. 1, element 112, [0015] ln. 7 “components 112 can include semiconductor memory, such as dynamic random-access memory (DRAM), integrated circuits, such as radio frequency integrated circuits, WIFI integrated circuits, or other active components” which includes electronic components) disposed on the functional area (see FIG. 1 where element 112 is disposed in the described functional area) and electrically connected to the carrier structure (see FIG. 1 and [0015] ln. 13 “components 112 can also include dies, which can connect to the top surface 114 of the package substrate 102 through the stiffener”).
Regarding Claim 10, O1 and K1 disclose the electronic package of claim 9, where O1 further discloses wherein the electronic module (element 112) is surrounded by the heat dissipation member (see FIG. 1 where the stiffener 116 surrounds element 112).
Regarding Claim 11, O1 and K1 disclose the electronic package of claim 1, K1 further discloses further comprising a heat dissipation structure (see FIG. 13, element 140, [0047] ln. 2 “heat sink 140”) disposed on the heat dissipation member (see FIG. 13, elements, 103 and 131, [0031] ln. 4 “The stiffener 130 may include a conductive frame 131” where the heat sink 140 is disposed on the heat dissipating stiffener 130).
Regarding Claim 12, O1 and K1 disclose the electronic package of claim 1, where O1 further discloses wherein a plurality of the heat dissipation members (element 116) are disposed on the carrier structure (see FIG. 1 where there is more than one stiffener heat dissipator element 116 on the substrate 102). Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ong et al. (US 2020/0006247 A1), hereinafter as O1, and Kim et al. (US 2022/0013475 A1), hereinafter as K1, in view of Kim, in view of Kim et al. (US 2023/0090461 A1), hereinafter as K2.
Regarding Claim 6, O1 and K1 disclose the electronic package of claim 1, but do not further disclose wherein the heat dissipation member is flush with a side surface of the carrier structure.
K2 discloses wherein the heat dissipation member (see FIG. 2, element 190, [0024] ln. 8 “heat sink 190”) is flush with a side surface of the carrier structure (see FIG. 2, element 100, and [0024] ln. 3 “substrate 100” where the heat sink 190 is flush with the side of the substrate 100).
The alignment of the heat dissipation member as disclosed by K2 is incorporated into the disclosure of O1 and K1. It would have been obvious to one of ordinary skill in the art at time of filing to incorporate the disclosure of K2 into O1 and K1 as there is motivation to create an optimized electronic package to yield predictable results – by having the heat dissipating structure aligned with the substrate, no excess space is left within the package and is therefore fully optimizing the space while not having excess space lacking purpose (see K2 [0056-0058]). Optimizing the package structure yields predictable results.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ong et al. (US 2020/0006247 A1), hereinafter as O1, and Kim et al. (US 2022/0013475 A1), hereinafter as K1, in view of Vincent et al. (US 2022/0181230 A1), hereinafter as V1.
Regarding Claim 7, O1 and K1 disclose the electronic package of claim 1, but dot not disclose wherein the heat dissipation member protrudes from a side surface of the carrier structure.
V1 discloses wherein the heat dissipation member (see FIG. 10A, elements 1002, 1004, [0037] ln. 11 “thermal conductive layer 1002”, [0037] ln. 15 “heatsink structure 1004” where the two elements are a part of the same heat dissipating structure) protrudes from a side surface of the carrier structure (see FIG. 10A, elements 104 and 1010, [0012] ln. 5 “package substrate 104” where the heat dissipating members 1002 and 1004 are connected to another element 1010 of this heating dissipating structure and it extends over the edge of the package substrate 104).
The heat dissipating member extending outside the substrate as disclosed by V1 is incorporated into the disclosure of O1 and K1. It would have been obvious to one of ordinary skill in the art at time of filing to incorporate the disclosure of V1 into O1 and K1 as there is motivation to have a heat dissipating member that isn’t confined entirely to the structure as this could help deal with overheating in the package and yield predictable results – by having the heat dissipating member extended outside the device packaged, excess heat can be led away from the device itself and help with internal overheating of the device package (see V1 [0011] and [0037]). The drawing out of heat within an electronic package yields predictable results.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yee et al. (US 2024/0096722 A1), Shao et al. (US 2024/00145342 A1), Im et al. (US 2019/00229100 A1) with their relevance as described in the action filed on January 26th, 2026.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRENNEN STUART CUDA whose telephone number is (571)272-6563. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.S.C./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights