Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the
first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, the reference to a specific claim number is presented in bold. Cited claim
limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitation, subsequent reference to the already disclosed claim limitation are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 and/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C.
102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 8-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated
by Yee et al. (US 20240096722 A1), hereinafter Y1.
Regarding Claim 1, Y1 discloses an electronic package (see Figs. 14-16, element 200, [0048]), comprising:
a carrier structure (element 202) being defined with an encapsulation area (area of element 212, 212A, 212B, see [0051] “an encapsulant 212 may be formed or applied over the redistribution structure 204”) and a functional area (area excluding element 212 above element 204) adjacent to the encapsulation area on one side (top side) of the carrier structure (see Figs. 14-16 and [0052] “the first portion 212A of the encapsulant 212 and the second portion 212B of the encapsulant 212 are separated from each other” in which they are adjacent on the carrier structure),
an electronic element (element 50E, [0050]) disposed on the encapsulation area of the carrier structure and electrically connected (element 208 and 210) to the carrier structure (see Fig. 15 and [0050] “50E can be bonded to top metallization pattern 208 via conductive connector 210” which is electronically connected),
a heat dissipation member (see Fig. 13, elements 140, 150, 160, [0035] “through insulating vias (TIVs) 140…may comprise copper”, making the TIVs conductive as copper is a heat conducting material), disposed on the functional area of the carrier structure and thermally connected to the electronic element (see [0050] Thermal and electrical connection), and
an encapsulation (element 212, 212A, 212B, see [0051]) layer formed on the encapsulation area of the carrier structure and covering the electronic element, wherein the encapsulation layer is free from being formed on the functional area (see Fig. 16, [0052] “encapsulant 212 may be disposed above the redistribution structure 204 and surround the semiconductor device 100 and the device die 50E” and it be noted “the first portion 212A of the encapsulant 212 and the second portion 212B of the encapsulant 212 are separated from each other”).
Regarding Claim 2, Y1 discloses the electronic package of Claim 1, wherein
the carrier structure has a heat dissipation layer (see Fig. 14 element 204, 208, [0049] “redistribution layer…metallization pattern” metallization patterns have an inherent material property which can dissipate heat) thermally (through elements 170 and 210, see [0043] “conductive connectors 170” and [0060] “conductive connectors 210”) connected to the electronic element and the heat dissipation member (see Fig. 15, elements 100, 170, 208, 240, [0050], “the semiconductor device 100 and one or more device dies, e.g., a device die 50E are attached to the first side 204A of the redistribution structure 204” and “the semiconductor device 100 may be bonded (e.g., flip-chip bonded) to the top metallization pattern 208 of the redistribution structure 204 through the conductive connectors 170”).
Regarding Claim 8, Y1 discloses the electronic package of Claim 1, wherein
the electronic element has a sensible heat area (a sensible area is not further defined, it is understood to be any material able to conduct heat {copper, tin, etc.}, see Fig. 15, element 210, [0050] “device die 50 E may be bonded (e.g., flip-chip bonded) to the top metallization pattern 208 through conductive connectors 210…conductive connectors 210 may be substantially similar to the conductive connectors 170 both in formation process and composition” and see [0043] “conductive connectors 170 may include a conductive material” making the conductive connectors of 50E a heat sensible area), the carrier structure has a functional pad (element 208, see [0049] “top metallization pattern”) corresponding to a position of the sensible heat area (vertically corresponding to a position of the sensible heat area because it is vertically connected through element 210), and the electronic element is thermally connected to the heat dissipation member via the functional pad (see area of element 210, [0050] “device die 50 E may be bonded (e.g., flip-chip bonded) to the top metallization pattern 208 through conductive connectors 210”).
Regarding Claim 9, Y1 discloses the electronic package of claim 1, further comprising:
at least one electronic module (element 50A) disposed on the functional area and electrically connected to the carrier structure (see Fig. 15 and [0035] “the TIVs 140 over and electrically connected to the metallization pattern of 128 of the redistribution structure 112” showing the electronic module is connected to the substrate).
Regarding Claim 10, Y1 discloses the electronic package of claim 9, wherein
the electronic module is surrounded by the heat dissipation member (see Fig. 22, element 350, and [0062] “The heat sink 350 is disposed above the redistribution structure 204 and surrounds the semiconductor device 402 and the semiconductor device 100”).
Regarding Claim 11, Y1 discloses the electronic package of claim 1, further comprising
a heat dissipation structure disposed on the heat dissipation member (see Fig. 19, elements 354, 352 and [0057] “the lid 354 and the annular structure 352 are separate structures attached to each other through an adhesive layer” as a two-piece heat dissipation structure disposed on a heat dissipation member).
Regarding Claim 12, Y1 discloses the electronic package of claim 1, wherein
a plurality of the heat dissipation members are disposed on the carrier structure (see Fig. 6, element 140, 150, 160, [0035] “a plurality of through insulating vias (TIVs) 140” as the TIVs are understood to disperse heat).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C.
102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Yee et al. (US 20240096722 A1), hereinafter Y1, in view of Shao et al. (US 20240145342 A1), hereinafter as S1.
Regarding Claim 3, Y1 discloses the electronic package of Claim 1. Y1 does not explicitly disclose wherein a height of the electronic element relative to the carrier structure is equal to a height of the encapsulation layer relative to the carrier structure.
S1 discloses wherein a height of the electronic element (element 80/80B) relative to the carrier structure is equal to a height of the encapsulation layer (element 90) relative to the carrier structure (see Figs. 9, the tops of elements 80/80B, 90 and [0017] “the top surface of one or more second integrated circuit devices 80B can also be coplanar with the top surface of the heat sink 60 and the encapsulant 90”).
The height of the electronic element compared to the encapsulation layer relative to the carrier structure as taught by S1 is incorporated as the height of the heat dissipation member compared to the encapsulation layer relative to the carrier structure of Y1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Y1 and S1 since the combination is a simple substitution of a known element for another to obtain predictable results - simple substitution for package performance is a known improvement of package management, and substituting the heights of electronic elements and encapsulation layer for aligned heights obtains predictable results (see [0002] of Y1 and [0002] of S1).
Regarding Claim 4¸Y1 discloses the electronic package of Claim 1. Y1 does not explicitly disclose wherein a height of the heat dissipation member relative to the carrier structure is equal to a height of the electronic element relative to the carrier structure.
S1 discloses wherein a height of the heat dissipation (element 60) member relative to the carrier structure is equal to a height of the electronic element (element 80/80B) relative to the carrier structure (see Fig. 9, the tops of element 80/80B and element 60, as well as [0017] “the top surface of one or more second integrated circuit devices 80B can also be coplanar with the top surface of the heat sink 60”).
The height of the heat dissipation member compared to the electronic element relative to the carrier structure as taught by S1 is incorporated as the height of the heat dissipation member compared to the electronic element relative to the carrier structure of Y1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Y1 and S1 since the combination is a simple substitution of a known element for another to obtain predictable results - simple substitution for package performance is a known improvement of package management, and substituting the heights of the heat dissipation member and the electronic elements for aligned heights obtains predictable results (see [0002] of Y1 and [0002] of S1).
Regarding Claim 5, Y1 discloses the electronic package of Claim 1. Y1 does not explicitly disclose wherein a height of the heat dissipation member relative to the carrier structure is equal to a height of the electronic element relative to the carrier structure.
S1 discloses wherein a height of the heat dissipation member (element 60) relative to the carrier structure is less than or equal to a height of the encapsulation layer (element 90) relative to the carrier structure (see Fig. 9, the tops of elements 60 and 90, as well as [0017] “the top surface of one or more second integrated circuit devices 80B can also be coplanar with the top surface of the heat sink 60 and the encapsulant 90” meaning the heat dissipation member and encapsulant are equal or less than in height since they are both the same height as the circuit device).
The height of the heat dissipation member compared to the encapsulation layer relative to the carrier structure as taught by S1 is incorporated as the height of the heat dissipation member compared to the encapsulation layer relative to the carrier structure of Y1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Y1 and S1 since the combination is a simple substitution of a known element for another to obtain predictable results - simple substitution for package performance is a known improvement of package management, and substituting the heights of the heat dissipation member and encapsulation layer for aligned heights obtains predictable results (see [0002] of Y1 and [0002] of S1).
Claims 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yee et al. (US 20240096722 A1), hereinafter Y1, in view of Im et al. (US 20190229100 A1), hereinafter as Im1.
Regarding Claim 6, Y1 discloses the electronic package of Claim 1. Y1 does not explicitly disclose wherein the heat dissipation member is flush with a side surface of the carrier structure.
Im1 discloses wherein the heat dissipation member (element 500) is flush with a side surface of the carrier structure (element 200) (see Fig. 8, elements 500 and 200 are aligned, and [0068] “the heat spreader 500 may be aligned with the interposer 200” where interposer is a synonym for carrier surface).
The alignment of the heat dissipation member compared with the side surface of carrier structure as taught by Im1 is incorporated as the alignment of the heat dissipation member compared to the alignment of the side surface of the carrier structure of Y1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to combine the teachings of Y1 and Im1 because the combination is a simple substitution of a known element for another to obtain a predictable outcome – simple substitution of piece alignment for better package performance and management will obtain predictable results (see [0002] of Y1 and [0071] of Im1).
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yee et al. (US 20240096722 A1), hereinafter Y1, in view of Vincent et al. (US 20220181230 A1), hereinafter as V1.
Regarding Claim 7 Y1 discloses the electronic package of Claim 1. Y1 does not explicitly disclose wherein the heat dissipation member protrudes from a side surface of the carrier structure.
V1 discloses wherein the heat dissipation member (elements 1004, 1006, 1012, and 1010) protrudes from a side surface of the carrier structure (element 204) (see Fig. 10A and [0037] “A thermal interface material 1006 is disposed between the package 1000 and the heatsink structure 1004 forming a continuous thermal conduction path from the semiconductor die 102 to the heatsink structure 1004”, which can be seen attached to elements 1212 and 1010 in Fig. 10A that extend over the edge of the carrier structure 204).
The protrusion of the heat dissipating member compared to the side surface of the carrier structure as taught in V1 is incorporated as the protrusion of the heat dissipating member compared to the side surface of Y1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Y1 and V1 because the combination is a simple substitution of one known element for another to obtain a predictable result – simple substitution of one known number of heat dissipation devices contained within the package for a heat dissipation device not contained withing the package would yield predictable results.
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to BRENNEN STUART CUDA whose telephone number is (571)272-6563. The examiner can normally be reached Monday - Friday, 8:00 am - 5 pm.
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/BRENNEN STUART CUDA/Examiner, Art Unit 2818
/SAMUEL PARK/Examiner, Art Unit 2818