DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim(s) 3-7, 9, 11, and 17 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 03/23/2026.
Foreign Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 09/12/2023 and 05/22/2026 are in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 202, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 8, 10, 12-16, and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shirou Ozaki et al, (hereinafter OZAKI), US 20210384340 A1, in view of Takeshi Takahashi et al, (hereinafter TAKAHASHI), JP 2016042537 A, and Takuya Tsutsumi et al, (hereinafter TSUTSUMI), JP 2019009321 A.
Regarding Claim 1, OZAKI teaches a semiconductor device (Fig. 21, 500) comprising:
a semiconductor layer (Fig. 6, 206, semiconductor stack structure) including a first layer (Fig. 6, 202, electron transit layer) and a second layer (Fig. 6, 204, electron supply layer) laminated over the first layer (Fig. 6, 202, electron transit layer);
a source electrode (Fig. 6, 213) and a drain electrode (Fig. 6, 214) provided on a first surface side (annotated Figure 6) of the semiconductor layer (Fig. 6, 206, semiconductor stack structure) where a first surface (annotated Figure 6) of the semiconductor layer (Fig. 6, 206, semiconductor stack structure) is located;
a gate electrode (Fig. 6, 230) provided on the first surface side (annotated Figure 6) of the semiconductor layer (Fig. 6, 206, semiconductor stack structure) between the source electrode (Fig. 6, 213) and the drain electrode (Fig. 6, 214); and
a first insulating film (Fig. 6, 221) provided on the first surface side (annotated Figure 6) of the semiconductor layer (Fig. 6, 206, semiconductor stack structure) and on a source electrode side (annotated Figure 6), where the source electrode (Fig. 6, 213) is provided, from the gate electrode (Fig. 6, 230), the first insulating film (Fig. 6, 221) containing aluminum oxide having oxygen vacancies ([0054]).
PNG
media_image1.png
991
911
media_image1.png
Greyscale
Though OZAKI teaches the first layer of the semiconductor layer is made of GaN (Gallium Nitride of i-GaN) [0051], OZAKI does not explicitly disclose a semiconductor device comprising: a semiconductor layer including a first layer containing indium, gallium, and arsenic.
TAKAHASHI teaches a semiconductor device (Fig. 3A, 200) comprising: a semiconductor layer (Fig. 3A, 202-206) including a first layer (Fig. 3A, 204, channel layer) containing indium, gallium, and arsenic ([0018]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified OZAKI to incorporate the teachings of TAKAHASHI, such that a semiconductor device comprising: a semiconductor layer including a first layer containing indium, gallium, and arsenic, so that a type II heterojunction between the barrier layer, 205 and the channel layer, 204 is formed and therefore, there is no barrier against holes (TAKAHASHI, [0019]).
Though OZAKI teaches the electron supply layer, 204 that are compound semiconductors (n-type AlGaN layer) and TAKAHASHI teaches a carrier supply layer, 203 is made of InAlAs, which is below a channel layer, 204, OZAKI as modified by TAKAHASHI does not explicitly disclose a semiconductor device comprising: a semiconductor layer including a second layer laminated over the first layer and containing indium, aluminum, and arsenic.
TSUTSUMI teaches a semiconductor device (Fig. 1, field-effect transistor, [0010]) comprising: a semiconductor layer (Fig. 3, 102-106) including a second layer (Fig. 3, 105, carrier supply layer) laminated over the first layer (Fig. 3, 103, conduction channel layer) and containing indium, aluminum, and arsenic ([0029]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have OZAKI as modified by TAKAHASHI to incorporate the teachings of TSUTSUMI, such that a semiconductor device comprising: a semiconductor layer including a second layer laminated over the first layer and containing indium, aluminum, and arsenic, so that the semiconductor devices that comprise the carrier supply layers, possess good high-frequency characteristics to realize terahertz wave applications (TSUTSUMI, [0003]).
Regarding Claim 2, OZAKI as modified by TAKAHASHI and TSUTSUMI teaches the semiconductor device according to claim 1.
OZAKI further teaches the semiconductor device (Fig. 21, 500), further comprising a second insulating film (Fig. 6, 221) which connects (annotated Figure 6) with the first insulating film (Fig. 6, 221), which is provided between the first surface (annotated Figure 6) of the semiconductor layer (Fig. 6, 206, semiconductor stack structure) and an end surface (annotated Figure 6) of the gate electrode (Fig. 6, 230) that faces the first surface (annotated Figure 6), and which contains aluminum oxide ([0053]).
PNG
media_image2.png
1134
916
media_image2.png
Greyscale
Regarding Claim 8, OZAKI as modified by TAKAHASHI and TSUTSUMI teaches the semiconductor device according to claim 2.
OZAKI further teaches the semiconductor device (Fig. 21, 500), further comprising a third insulating film (Fig. 6, 221) which connects (annotated Figure 6) with the second insulating film (Fig. 6, 221), which is provided on a drain electrode side (annotated Figure 6), where the drain electrode (Fig. 6, 214) is provided, from the gate electrode (Fig. 6, 230), and which contains aluminum oxide ([0053]).
PNG
media_image3.png
1134
916
media_image3.png
Greyscale
Regarding Claim 10, OZAKI as modified by TAKAHASHI and TSUTSUMI teaches the semiconductor device according to claim 1.
OZAKI further teaches the semiconductor device (Fig. 21, 500), wherein:
the semiconductor layer (Fig. 6, 206, semiconductor stack structure) further includes, on the first surface side (Fig. 6, top side close to layer 205, capping layer), a third layer (Figs. 16/23, 205, capping layer) including a recess (Figs. 16/17/23, 320/420, opening / 507, recess) and a first mesa (Fig. 27, 1226s, source pad) and a second mesa (Fig. 27, 1226d, drain pad) opposite each other with the recess therebetween (Figs. 16/17/23, 320/420, opening / 507, recess);
the source electrode (Fig. 27, 1232s, source lead) and the drain electrode (Fig. 27, 1232d, drain lead) are provided over the first mesa (Fig. 27, 1226s, source pad) and the second mesa (Fig. 27, 1226d, drain pad), respectively; and
the gate electrode (Fig. 27, 1232g, gate lead) is provided apart from the first mesa (Fig. 27, 1232s, source lead) and the second mesa (Fig. 27, 1226d, drain pad) in the recess (Figs. 16/17, 320/420, opening).
TSUTSUMI further teaches the semiconductor device (Fig. 1, field-effect transistor, [0010]), wherein:
the semiconductor layer (Fig. 3, 102-106) further includes, on the first surface side (Fig. 3, top side close to 106, barrier layer), a third layer (Fig. 3, 107, ohmic cap layer) including a recess (Fig. 3, 113, recess region) and a first mesa (Fig. 3, 114, ohmic region) and a second mesa (Fig. 3, 114, ohmic region) opposite each other with the recess therebetween (Fig. 3, 113, recess region);
the source electrode (Fig. 3, 108) and the drain electrode (Fig. 3, 109) are provided over the first mesa (Fig. 3, 114, ohmic region) and the second mesa (Fig. 3, 114, ohmic region), respectively; and
the gate electrode (Fig. 3, 110) is provided apart from the first mesa (Fig. 3, 114, ohmic region) and the second mesa (Fig. 3, 114, ohmic region) in the recess (Fig. 3, 113, recess region).
Regarding Claim 12, OZAKI as modified by TAKAHASHI and TSUTSUMI teaches the semiconductor device according to claim 10.
TSUTSUMI further teaches the semiconductor device (Fig. 1, field-effect transistor, [0010]), wherein the semiconductor layer (Fig. 3, 102-106) further includes a fourth layer (Fig. 3, etching stop layer, [0040]) provided under a bottom of the recess (Fig. 3, 113, recess region).
Regarding Claim 13, OZAKI as modified by TAKAHASHI and TSUTSUMI teaches the semiconductor device according to claim 1.
OZAKI further teaches the semiconductor device (Fig. 21, 500), further comprising a substrate located (Fig. 6, 201) on a second surface side (annotated Figure 6) of the semiconductor layer (Fig. 6, 206, semiconductor stack structure) opposite to the first surface side (annotated Figure 6), the substrate (Fig. 6, 201).
PNG
media_image4.png
991
918
media_image4.png
Greyscale
TAKAHASHI further teaches a semiconductor device (Fig. 3A, 200), further comprising a substrate located (Fig. 3, 201) on a second surface side (annotated Figure 3) of the semiconductor layer (Fig. 3, 202-206) opposite to the first surface side (annotated Figure 3), the substrate (Fig. 3, 201) containing indium and phosphorus (Fig. 3, 201, the substrate, 201 is a semi-insulating InP substrate, [0018]).
PNG
media_image5.png
752
812
media_image5.png
Greyscale
Regarding Claim 14, OZAKI as modified by TAKAHASHI and TSUTSUMI teaches the semiconductor device according to claim 1.
OZAKI further teaches the semiconductor device (Fig. 21, 500), wherein the second layer (Fig. 6, 204, electron supply layer), of the first layer (Fig. 6, 202, electron transit layer) and the second layer (Fig. 6, 203/204, spacer layer/electron supply layer) of the semiconductor layer (Fig. 6, 206, semiconductor stack structure), is provided on the first surface side (annotated Figure 6).
Regarding Claim 15, OZAKI teaches a semiconductor device (Fig. 21, 500) manufacturing method ([0042]) comprising:
forming a semiconductor layer (Fig. 6, 206, semiconductor stack structure) including a first layer (Fig. 6, 202, electron transit layer) and a second layer (Fig. 6, 204, electron supply layer) laminated over the first layer (Fig. 6, 202, electron transit layer);
forming a source electrode (Fig. 6, 213) and a drain electrode (Fig. 6, 214) provided on a first surface side (annotated Figure 6) of the semiconductor layer (Fig. 6, 206, semiconductor stack structure) where a first surface (annotated Figure 6) of the semiconductor layer (Fig. 6, 206, semiconductor stack structure) is located;
forming a gate electrode (Fig. 6, 230) on the first surface side (annotated Figure 6) of the semiconductor layer (Fig. 6, 206, semiconductor stack structure) between the source electrode (Fig. 6, 213) and the drain electrode (Fig. 6, 214); and
forming a first insulating film (Fig. 6, 221) containing aluminum oxide having oxygen vacancies ([0054]) on the first surface side (annotated Figure 6) of the semiconductor layer (Fig. 6, 206, semiconductor stack structure) and on a source electrode side (Fig. 6, 213), where the source electrode (Fig. 6, 213) is formed, from the gate electrode (Fig. 6, 230).
PNG
media_image1.png
991
911
media_image1.png
Greyscale
Though OZAKI teaches the first layer of the semiconductor layer is made of GaN (Gallium Nitride of i-GaN) [0051], OZAKI does not explicitly disclose a semiconductor device manufacturing method comprising: forming a semiconductor layer including a first layer containing indium, gallium and arsenic.
TAKAHASHI teaches a semiconductor device (Fig. 3A, 200) manufacturing method ([0001]) comprising: forming a semiconductor layer (Fig. 3A, 202-206) including a first layer (Fig. 3A, 204, channel layer) containing indium, gallium, and arsenic ([0018]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified OZAKI to incorporate the teachings of TAKAHASHI, such that a semiconductor device manufacturing method comprising: forming a semiconductor layer including a first layer containing indium, gallium, and arsenic, so that a type II heterojunction between the barrier layer, 205 and the channel layer, 204 is formed and therefore, there is no barrier against holes (TAKAHASHI, [0019]).
Though OZAKI teaches the electron supply layer, 204 that are compound semiconductors (n-type AlGaN layer) and TAKAHASHI teaches a carrier supply layer, 203 is made of InAlAs, which is below a channel layer, 204, OZAKI as modified by TAKAHASHI does not explicitly disclose a semiconductor device manufacturing method comprising: forming a semiconductor layer including a second layer laminated over the first layer and containing indium, aluminum, and arsenic.
TSUTSUMI teaches a semiconductor device (Fig. 1, field-effect transistor, [0010]) manufacturing method ([0003]) comprising: forming a semiconductor layer (Fig. 3, 102-106) including a second layer (Fig. 3, 105, carrier supply layer) laminated over the first layer (Fig. 3, 103, conduction channel layer) and containing indium, aluminum, and arsenic ([0029]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have OZAKI as modified by TAKAHASHI to incorporate the teachings of TSUTSUMI, such that a semiconductor device manufacturing method comprising: forming a semiconductor layer including a second layer laminated over the first layer and containing indium, aluminum, and arsenic, so that the semiconductor devices that comprise the carrier supply layers, possess good high-frequency characteristics to realize terahertz wave applications (TSUTSUMI, [0003]).
Regarding Claim 16, OZAKI as modified by TAKAHASHI and TSUTSUMI teaches the semiconductor device manufacturing method according to claim 15.
OZAKI further teaches the semiconductor device (Fig. 21, 500) manufacturing method ([0042]), further comprising forming a second insulating film (Fig. 6, 221) which connects (annotated Figure 6) with the first insulating film (Fig. 6, 221), between the first surface (annotated Figure 6) of the semiconductor layer (Fig. 6, 206, semiconductor stack structure) and an end surface (annotated Figure 6) of the gate electrode (Fig. 6, 230) that faces the first surface (annotated Figure 6), the second insulating film (Fig. 6, 221) containing aluminum oxide ([0053]).
PNG
media_image2.png
1134
916
media_image2.png
Greyscale
Regarding Claim 18, OZAKI as modified by TAKAHASHI and TSUTSUMI teaches the semiconductor device according to claim 16.
OZAKI further teaches the semiconductor device (Fig. 21, 500) manufacturing method ([0042]), further comprising forming a third insulating film (Fig. 6, 221) which connects (annotated Figure 6) with the second insulating film (Fig. 6, 221), on a drain electrode side (annotated Figure 6), where the drain electrode (Fig. 6, 214) is provided, from the gate electrode (Fig. 6, 230), the third insulating film (Fig. 6, 221) containing aluminum oxide ([0053]).
PNG
media_image3.png
1134
916
media_image3.png
Greyscale
Regarding Claim 19, OZAKI teaches an electronic device (Fig. 21, 500) comprising a semiconductor device (Fig. 21, 500) including:
a semiconductor layer having (Fig. 6, 206, semiconductor stack structure) a first layer (Fig. 6, 202, electron transit layer) and a second layer (Fig. 6, 204, electron supply layer) laminated over the first layer (Fig. 6, 202, electron transit layer);
a source electrode (Fig. 6, 213) and a drain electrode (Fig. 6, 214) provided on a first surface side (annotated Figure 6) of the semiconductor layer (Fig. 6, 206, semiconductor stack structure) where a first surface (annotated Figure 6) of the semiconductor layer (Fig. 6, 206, semiconductor stack structure) is located;
a gate electrode (Fig. 6, 230) provided on the first surface side (annotated Figure 6) of the semiconductor layer (Fig. 6, 206, semiconductor stack structure) between the source electrode (Fig. 6, 213) and the drain electrode (Fig. 6, 214); and
a first insulating film (Fig. 6, 221) provided on the first surface side (annotated Figure 6) of the semiconductor layer (Fig. 6, 206, semiconductor stack structure) and on a source electrode side (annotated Figure 6), where the source electrode (Fig. 6, 213) is provided, from the gate electrode (Fig. 6, 230), the first insulating film (Fig. 6, 221) containing aluminum oxide having oxygen vacancies ([0054]).
PNG
media_image1.png
991
911
media_image1.png
Greyscale
Though OZAKI teaches the first layer of the semiconductor layer is made of GaN (Gallium Nitride of i-GaN) [0051], OZAKI does not explicitly disclose a semiconductor device comprising: a semiconductor layer having a first layer containing indium, gallium, and arsenic.
TAKAHASHI teaches a semiconductor device (Fig. 3A, 200) having a semiconductor layer (Fig. 3A, 202-206) having a first layer (Fig. 3A, 204, channel layer) containing indium, gallium, and arsenic ([0018]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified OZAKI to incorporate the teachings of TAKAHASHI, such that a semiconductor device having a semiconductor layer including a first layer containing indium, gallium, and arsenic, so that a type II heterojunction between the barrier layer, 205 and the channel layer, 204 is formed and therefore, there is no barrier against holes (TAKAHASHI, [0019]).
Though OZAKI teaches the electron supply layer, 204 that are compound semiconductors (n-type AlGaN layer) and TAKAHASHI teaches a carrier supply layer, 203 is made of InAlAs, which is below a channel layer, 204, OZAKI as modified by TAKAHASHI does not explicitly disclose a semiconductor device comprising: a semiconductor layer having a second layer laminated over the first layer and containing indium, aluminum, and arsenic.
TSUTSUMI teaches a semiconductor device (Fig. 1, field-effect transistor, [0010]) comprising: a semiconductor layer (Fig. 3, 102-106) having a second layer (Fig. 3, 105, carrier supply layer) laminated over the first layer (Fig. 3, 103, conduction channel layer) and containing indium, aluminum, and arsenic ([0029]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have OZAKI as modified by TAKAHASHI to incorporate the teachings of TSUTSUMI, such that a semiconductor device comprising: a semiconductor layer having a second layer laminated over the first layer and containing indium, aluminum, and arsenic, so that the semiconductor devices that comprise the carrier supply layers, possess good high-frequency characteristics to realize terahertz wave applications (TSUTSUMI, [0003]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20210036139 A1 – Figure 1
STATEMENT OF RELEVANCE – Cross-sectional view of a compound semiconductor device including a high electron mobility transistor (HEMT).
US 20210091199 A1 – Figure 7
STATEMENT OF RELEVANCE – Schematic diagram of a semiconductor device include a semiconductor layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights