DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election without traverse of Invention I (claims 1-15) in the reply filed on 04/27/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 9, 12-13, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (U.S 2018/0247916 A1).
As to claim 1, Lee et al. disclose in Fig. 3 a package, comprising:
a first substrate (110) and a second substrate (180) above the first substrate (110) (Fig. 3, para. [0032], [0091]);
a first chip (“first semiconductor die” 130) on an upper surface (top surface) of the first substrate (110) and below the second substrate (180) (Fig. 3, para. [0055]-[0056]), first bumps (“conductive bumps” 132) on an active side of the first chip (“first semiconductor die” 130) facing and electrically coupled to the first substrate (110), the first bumps (“conductive bumps” 132) configured to carry signals to and/or from the first chip (“first semiconductor die” 130) (Fig. 3, para. [0055]); a second chip (“second semiconductor die” 160) on a lower surface (bottom surface) of the second substrate (180) and above the first chip (“first semiconductor die” 130) (Fig. 3, para. [0058], [0074]-[0078]), second bumps (“conductive bumps” 162) on an active side of the second chip (“second semiconductor die” 160) facing and electrically coupled to the second substrate (180), the second bumps (“conductive bumps” 162) configured to carry signals to and/or from the second chip (“second semiconductor die” 160) (Fig. 3, para. [0078]); a first mold (“first encapsulating material” 240) on the upper surface (top surface) of the first substrate (110) and below the second substrate (180), the first mold (“first encapsulating material” 240) at least partially encapsulating side surfaces and a non-active side surface of the first chip (“first semiconductor die” 130) (Fig. 3, para. [0118]-[0119]); and a second mold (comprising “second encapsulating material” 170 & “adhesion member” 160a) on the lower surface (bottom surface) of the second substrate (180) and above the first mold (“first encapsulating material” 140), the second mold (comprising “second encapsulating material” 170 & “adhesion member” 160a) at least partially encapsulating side surfaces and a non-active side surface of the second chip (“second semiconductor die” 160) (Fig. 3, para. [0077], [0080]-[0081]), wherein the first chip (“first semiconductor die” 130) and the second chip (“second semiconductor die” 160) are vertically aligned with each other, at least partially (see Fig. 3).
As to claim 9, as applied to claim 1 above, Lee et al. disclose in Fig. 3 all claimed limitations including the package further comprising: one or more through-mold vias (TMV) (comprising “first metal pillar” 120 & “second metal pillar” 150) between the first and second substrates (110, 180) within the first and second molds (240, 170), the one or more TMVs (comprising “first metal pillar” 120 & “second metal pillar” 150) electrically coupling the first and second substrates (110, 180) with each other (Fig. 3, para. [0067]-[0068]).
As to claim 12, as applied to claim 1 above, Lee et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein the second substrate (180) is a coreless substrate (Fig. 3).
As to claim 13, as applied to claim 1 above, Lee et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein the first and second molds (240, 170) are separate molds that are in contact with each other (see Fig. 3).
As to claim 15, as applied to claim 1 above, Lee et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein the package (Fig. 3) is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device (“die” 160 may perform “communication function”, para. [0076]), a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S 2018/0247916 A1).
As to claim 14, as applied to claim 1 above, Lee et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein a thermal conductivity of the first mold (“first encapsulating material” 240/140 comprise “polymer”, para. [0060]) is equal to or greater than 0.1 W/m-K, a thermal conductivity of the second mold (comprising at least “second encapsulating material” 170 which comprises “polymer”, para. [0081]) is equal to or greater than 0.1 W/m-K, or both.
Lee et al. do not disclose the first and second molds having a thermal conductivity which is equal to or greater than 1 W/m-K, or both. However, at the time of the invention was made; it would have been obvious to one of ordinary skill in the art to use the first and second molds having a thermal conductivity which is equal to or greater than 1 W/m-K, or both in the teaching of Lee et al. in order to allow faster heat transfer from the mold materials to the cooling system, and reduce production costs, because such material substitution or replacement would have been considered a mere substitution of art-recognized equivalent values, MPEP 2144.06.
Claim(s) 2-4, 5 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S 2018/0247916 A1) in view of Yu et al. (U.S 2016/0049385 A1).
As to claims 2, 3 and 4, as applied to claim 1 above, Lee et al. disclose in Fig. 3 all claimed limitations including the package further comprising: a third chip (“component” 191) on an upper surface (top surface) of the second substrate (180) (Fig. 3, para. [0112]), third bumps (see bumps underneath “component” 191) on an active side of the third chip (“component” 191) facing and electrically coupled to the second chip (160) through one or more signal connections (“land layer” 184) within the second substrate (180), the third bumps (see bumps underneath “component” 191) configured to carry signals to and/or from the third chip (“component” 191) (Fig. 3, para. [0112]).
Lee et al. do not disclose a third mold on the upper surface of the second substrate, the third mold at least partially encapsulating side surfaces and a non-active side surface of the third chip; wherein the first chip is a logic chip, the second chip is a processing near memory (PNM) chip, the third chip is a memory chip, or any combination thereof; and wherein the memory chip is a dynamic random- access memory (DRAM) chip.
Yu et al. disclose in Fig. 1A a package, comprising:
a first substrate (124), second substrate (122), a first chip (110), a second chip (116), and a third chip (134); and a third mold (136) on the upper surface of the second substrate (122), the third mold (136) at least partially encapsulating side surfaces and a non-active side surface of the third chip (134) (Fig. 1A, para. [0025], [0043], [0051]);
wherein the first chip (110) is a logic chip (see para. [0016], chip 110 can be a logic chip), the second chip (116) is a processing near memory (PNM) chip (chip 116 can be a memory chip or a random access memory chip, para. [0025]), the third chip (134) is a memory chip (para. [0042]), or any combination thereof; and
wherein the memory chip (134) is a dynamic random- access memory (DRAM) chip (“a dynamic random access memory chip”, para. [0042]) (Fig. 1A, para. [0042]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify reference of Lee et al. by having a third mold on the upper surface of the second substrate, the third mold at least partially encapsulating side surfaces and a non-active side surface of the third chip, the first chip is a logic chip, the second chip is a processing near memory (PNM) chip, the third chip is a memory chip, or any combination thereof; and the memory chip is a dynamic random- access memory (DRAM) chip, as taught by Yu et al., in order to protect the third chip in the package without being damaged by having a third mold, improve high speed and high-performance by having a logic chip, and provide fast access by having a processing near memory (PNM) chip or a memory chip.
As to claim 5, as applied to claim 1 and 2 above, Lee et al. disclose in Fig. 3 all claimed limitations including pitches between adjacent second bumps (“conductive bumps” 162) and between adjacent third bumps (see bumps underneath “component” 191), wherein one or more second bumps (“conductive bumps” 162) are vertically connected to one or more third bumps (see bumps underneath “component” 191) through corresponding one or more vertical signal connections {comprising “signal distribution layer” 182, “pad (or via) layer” 183, “lands” 184} within the second substrate (180), and wherein the second chip (160) is configured to access the third chip (191) through the one or more vertical signal connections {comprising “signal distribution layer” 182, “pad (or via) layer” 183, “lands” 184} (Fig. 3, para. [0091], [0099]).
Lee et al. in view of Yu et al. do not disclose pitches between adjacent second bumps and between adjacent third bumps are less than 1 µm.
However, it would have been obvious to one of ordinary skill in the art to use the teaching of Lee et al. with Yu et al. by having pitches between adjacent second bumps and between adjacent third bumps are less than 1 µm as claimed, in order to increase number of interconnects and reduce bump size so as to improve device performance, because it has been held that where the general conditions of the claims are disclosed in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See In re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955); Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. Denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); MPEP 2144.05. There is no evidence indicating the range of pitches between adjacent second bumps and between adjacent third bumps is critical. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
As to claim 8, as applied to claims 1, 2 and 5 above, Lee et al. and Yu et al. disclose all claimed limitations. Lee et al. are silent to disclose a thickness of the second substrate is 70 µm or less. However, it would have been obvious to one of ordinary skill in the art to use the teaching of Lee et al. with Yu et al. in the range (70 µm or less for a thickness of the second substrate) as claimed, in order to reduce the size and minimize warpage of the substrate, because it has been held that where the general conditions of the claims are disclosed in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See In re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955); Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. Denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); MPEP 2144.05. There is no evidence indicating the thickness range of the second substrate is critical. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over over Lee et al. (U.S 2018/0247916 A1) in view of Yu et al. (U.S 2016/0049385 A1) as applied to claims 1, 2, and 5 above, and further in view of Keeth (U.S 2019/0341370 A1).
As to claim 6, as applied to claims 1, 2 and 5 above, Lee et al. do not disclose the second chip is a processing near memory (PNM) chip and the third chip is a memory chip, and wherein the PNM chip is configured to perform memory built-in self-test (MBIST) of the memory chip through the one or more vertical signal connections within the second substrate.
Yu et al. disclose in Fig. 1A a package comprising:
a first substrate (124), second substrate (122), a first chip (110), a second chip (116), and a third chip (134), wherein the second chip (116) is a processing near memory (PNM) chip and the third chip (134) is a memory chip (Fig. 1A, para. [0025], [0042]), and wherein the PNM chip (116) is configured to memory function through the one or more vertical signal connections (122r) within the second substrate (122) (Fig. 1A, para. [0031]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify reference of Lee et al. by having the second chip is a processing near memory (PNM) chip and the third chip is a memory chip, as taught by Yu et al., in order to provide fast access by having a processing near memory (PNM) chip or a memory chip.
Yu et al. do not disclose the PNM chip is configured to perform memory built-in self-test (MBIST) of the memory chip.
However, Keeth discloses in Fig. 3 a package comprising: a memory chip (a PNM chip) is configured to perform memory built-in self-test (MBIST) of the memory chip (Fig. 3, para. [0050]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify reference of Yu et al with Lee et al. by having a memory chip (a PNM chip) configured to perform memory built-in self-test (MBIST) of the memory chip, as taught by Keeth, in order to allow the memory chip can be tested within the package.
Allowable Subject Matter
Claims 7, and 10-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: JOO et al. (U.S 2021/0265274 A1).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 July 11, 2026
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