DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/1/26 has been entered.
Response to Amendment/Arguments
With the reply filed 6/1/26, claims 1 and 21 have been amended. In view of Applicant’s amendment and associated arguments, see pages 3-5, the rejection of claims 1-4, 21, 22 and 24 have overcome and has been withdrawn. However, those claims are rejected in view of a new ground of rejection based on newly applied prior art, as indicated below.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 1 is rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Xia et al. U.S. Pat. App. Pub. No. 2023/0049670.
Regarding claim 1, Xia discloses a receiver circuit (i.e. 201 receiving output from filter circuit 200 – Fig. 2) comprising: a first comparator circuit 218; a second comparator circuit 220; and an inverter circuit (comprising inverters 224 and 226), having a first input terminal (I/P of 226) and a second input terminal (I/P of 224), wherein a first output terminal of the first comparator circuit 218 is electrically connected to the first input terminal of the inverter circuit 226, and the first input terminal of the inverter circuit is configured to receive a first voltage generated at the first output terminal of the first comparator circuit (see Fig. 2), wherein a second output terminal of the second comparator circuit 220 is electrically connected to the second input terminal of the inverter circuit 224, and the second input terminal of the inverter circuit is configured to receive a second voltage generated at the second output terminal of the second comparator circuit (see Fig. 2).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 2, 4, 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Xia et al. in view of Sugimoto U.S. Pat. App. Pub. No. 2023/0030235.
Regarding claim 2, Xia discloses a receiver circuit as described above, and further discloses that the first comparator circuit comprises a first active load (i.e. logic gate circuit 228) and the second comparator circuit comprises a second active load (i.e. logic gate circuit 230), where each of the comparator circuits are considered to be single-ended, but Xia does not expressly disclose that the first comparator circuit comprises a first single-ended differential amplifier and the second comparator circuit comprises a single-ended differential amplifier.
Sugimoto discloses that a comparator circuit may be implemented using a differential amplifier (¶ [0153]). It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to implement the comparator of Xia using a differential amplifier as indicated by Sugimoto, as it is a well-known implementation of a comparator circuit, yielding predictable results (see MPEP § 2143.I.A).
Regarding claim 4, in the proposed combination, Xia discloses that the first single-ended comparator 218 comprises a first input terminal (218 +) receiving an input voltage 250, and a second input terminal (218 –) receiving a reference voltage 254, and the second single-ended comparator 218 comprises a third input terminal (220 +) receiving an input voltage 252, and a fourth input terminal (220 –) receiving the reference voltage 254 (see Fig. 2).
Regarding claim 21, Xia discloses a receiver circuit (i.e. 201 receiving output from filter circuit 200 – Fig. 2) comprising: a first amplifier circuit 218, configured to, in response to an input voltage 250 and a reference voltage 254; generate a first voltage at a first output terminal of the first amplifier; a first active load (i.e. logic gate circuit 228), coupled to the output terminal of the first amplifier 218; a second amplifier circuit 220; configured to, in response to an input voltage 252 and a reference voltage 254; generate a second voltage at a second output terminal of the second amplifier; a second active load (i.e. logic gate circuit 230), coupled to the output terminal of the second amplifier 218; and an inverter circuit (comprising inverters 224 and 226), having a first input terminal (I/P of 226) electrically connected to the first output terminal of the first amplifier circuit 218, and a second input terminal (I/P of 224), electrically connected to the second output terminal of the second amplifier circuit 220, wherein the first input terminal of the inverter circuit is configured to receive the first voltage generated at the first output terminal of the first amplifier circuit (see Fig. 2), and the second input terminal of the inverter circuit is configured to receive the second voltage generated at the second output terminal of the second amplifier circuit (see Fig. 2).
Xia does not expressly disclose that the first amplifier circuit comprises a differential amplifier and the second amplifier circuit comprises a differential amplifier.
Sugimoto discloses that comparator circuits may be implemented using differential amplifiers (¶ [0153]). It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to implement the comparator of Xia using a differential amplifier as indicated by Sugimoto, as it is a well-known implementation of a comparator circuit, yielding predictable results (see MPEP § 2143.I.A).
Regarding claim 22, in the proposed combination, the comparator circuits 218/220 of Xia are considered single-ended comparator circuits as they both have single-ended outputs (Fig. 2).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Xia et al. in view of Huffman et al. U.S. Pat. App. Pub. No. 2010/0176855.
Regarding claim 3, Xia discloses a receiver circuit as described above, and further discloses that the inverter circuit comprises a third active load (i.e. switching circuit 202), but does not expressly disclose that the inverter circuit comprises a CMOS inverter.
Huffman discloses that an inverter circuit can be implemented using CMOS technology (¶ [0048]). It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to implement the inverter of Xia using CMOS technology as suggested by Huffman, as it is a well-known low-cost implementation for inverter circuits, yielding predictable results (see MPEP § 2143.I.A).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Xia et al. in view of Sugimoto, as applied to claim 21 above, and further in view of Huffman et al.
Regarding claim 24, Xia in combination with Sugimoto disclose a receiver circuit as described above, and Xia further discloses that the inverter circuit comprises a third active load (i.e. 202), but do not expressly disclose that the inverter circuit comprises a CMOS inverter.
Huffman discloses that an inverter circuit can be implemented using CMOS technology (¶ [0048]). It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to implement the inverter of Xia in the receiver of the proposed combination with Sugimoto, using CMOS technology as suggested by Huffman, as it is a well-known low-cost implementation for inverter circuits, yielding predictable results (see MPEP § 2143.I.A).
Allowable Subject Matter
Claims 17, 18, 20 and 29 are allowed.
Claims 5-8, 23 and 25-28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/DAVID B LUGO/Primary Examiner, Art Unit 2631 6/20/2026
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