DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
With the reply filed 12/11/25, Applicant has amended claim 17, canceled claim 19 and added new claim 29. In view of claim 17 being amended to include subject matter from claim 19 previously indicated as being allowable, the rejection of claims 17 and 18 is withdrawn.
Applicant's arguments filed 12/11/25 regarding the rejection of claims 1-4, 21, 22 and 24 as anticipated under 35 U.S.C. § 102(a)(1) have been fully considered but are not persuasive.
Regarding claim 1, Applicant argues that Jiang does not teach or suggest the claim limitation: “wherein a first output terminal of the first comparator circuit is electrically connected to the first input terminal of the inverter circuit, and a second output terminal of the second comparator circuit is electrically connected to the second input terminal of the inverter circuit.” In particular, Applicant argues that, since “the electrical connections of amplifiers 316 and inverter 312 form a gate-driven switch path, which is not a direct electrical connection between amplifier 316’s output terminal and the inverter 312’s input terminal…There is no continuous conductive path between amplifier 316’s output terminal and the inverter 312’s input terminal. Similarly, there is also no continuous conductive path between amplifier 366’s output terminal and the inverter 362’s input terminal” (emphasis in original). In response, it is noted that the claim requires that the first and second output terminals of the respective comparator circuits are “electrically connected” to the corresponding first and second input terminals of the respective inverter circuits. Circuit elements being electrically connected require them to be “connected by means of a conducting path…as distinguished from merely through electromagnetic conduction” (see attached definition: https://encylcopedia2.thefreedictionary.com/electrically+connected). Any other requirement attached to such an electrical connection is not recited in the claims. Accordingly, the circuit arrangement of Jiang where an electrical connection exists between the output of a comparator circuit and an input of an inverter circuit through a transistor, is considered to meet the definition of being “electrically connected” as would be understood by one having ordinary skill in the art, and thus Jiang is still considered to teach all the limitations of and thus anticipate claim 1, and the rejection of claims 1-4 are maintained.
Regarding claim 21, Applicant argues that transistors 308 and 358 “cannot” serve as the first active load and the second active load, respectively. The Examiner respectfully disagrees. A transistor is not a passive device, but is well understood in the art to be an active device. Further, an electrical load is understood to a device that consumes electric power. Accordingly, the transistors 308 and 358 are considered to be active loads, claim 21 is still considered to be anticipated by Jiang, and the rejection of claims 21, 22 and 24 is maintained.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 21, 22 and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jiang et al. U.S. Pat. No. 9,794,001.
Regarding claim 1, Jiang discloses a receiver circuit 300 (Fig. 3) comprising: a first comparator circuit (i.e. 316); a second comparator circuit (i.e. 366); and an inverter circuit (i.e. including inverters 312 and 362 – see col. 9, ll. 55-60), having a first input terminal (I/P of 312) and a second input terminal (I/P of 362), wherein a first output terminal of the first comparator 316 is electrically connected to the first input terminal of the inverter circuit, and a second output terminal of the second comparator circuit is electrically connected to the second input terminal of the inverter circuit (see Fig. 3).
Regarding claim 2, the first comparator comprises first single-ended differential amplifier 316 (col. 10, ll. 4-6) and a first active load 308, and the second comparator comprises second single-ended differential amplifier 366 (col. 10, ll. 4-6) and a second active load 358.
Regarding claim 3, the inverter circuit comprises a CMOS inverter 312/362 and a third active load 314 (see col. 9, ll. 55-67).
Regarding claim 4, the first single-ended differential amplifier 316 comprises a first input terminal (+) receiving an input voltage (DOP), and a second input terminal () receiving a reference voltage (DON), and the second single-ended differential amplifier 366 comprises a first input terminal (–) receiving an input voltage (DOB), and a second input terminal (+) receiving a reference voltage (Vcmref) (see Fig. 3).
Regarding claim 21, Jiang discloses a receiver circuit 300 (Fig. 3) comprising: a first differential amplifier (i.e. 316), configured to, in response to an input voltage and a reference voltage, generate a first voltage at a first output terminal of the first differential amplifier; a first active load 308, coupled to the output terminal of the first differential amplifier; a second differential amplifier (i.e. 366), configured to, in response to an input voltage and a reference voltage, generate a second voltage at a second output terminal of the second differential amplifier; a second active load 358, coupled to the output terminal of the second differential amplifier; and an inverter circuit (i.e. including inverters 312 and 362 – see col. 9, ll. 55-60), having a first input terminal (I/P of 312) electrically connected to the first output terminal of the first differential amplifier 316, and a second input terminal (I/P of 362) electrically connected to t second output terminal of the second differential amplifier (see Fig. 3).
Regarding claim 22, the first differential amplifier and the second differential amplifier are a first single-ended differential amplifier 316 and a second single-ended differential amplifier 366, respectively (see col. 10, ll. 4-6).
Regarding claim 24, the inverter circuit comprises a CMOS inverter 312/362 and a third active load 314 (see col. 9, ll. 55-67).
Allowable Subject Matter
Claims 17, 18, 20 and 29 are allowed.
Claims 5-8, 19, 23 and 25-28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David B. Lugo whose telephone number is 571-272-3043. The examiner can normally be reached M-F, 9-6.
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/DAVID B LUGO/Primary Examiner, Art Unit 2631
3/30/2026