DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species 1 (encompassing claims 1, 2, and 6-17) in the reply filed on 1/20/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted 9/13/23, 4/8/25, and 8/13/25. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements have been considered by the examiner.
Specification
The title of the invention is not descriptive as it is generic. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6, and 9-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakano (U.S. 2016/0241018 A1).
Regarding claim 1, Nakano discloses a semiconductor device, comprising:
A semiconductor layer (6, Fig. 5B) ([0085]);
An insulation film (16, Fig. 5B) formed on a surface of the semiconductor layer ([0085]);
A main cell region (7, Fig. 3) including a main cell disposed on the semiconductor layer ([0071]-[0073]); and
A temperature sensing diode (20, Fig. 5B) disposed in a region different from the main cell region and configured to detect a temperature, wherein the temperature sensing diode includes a diode cell including a first semiconductor region (22, Fig. 5B) of a first conductive type formed as a thin film on a surface of the insulation film and a second semiconductor region (23, Fig. 5B) of a second conductive type formed as a thin film on the surface of the insulation film, the second semiconductor region (23, Fig. 5B) annularly surrounds the first semiconductor region (22, Fig. 5B), and the second semiconductor region (23, Fig. 5B) includes an inner surface joined to the first semiconductor region (22, Fig. 5B) ([0088]).
Regarding claim 6, Nakano discloses
An intermediate insulation film (18, Fig. 5B) covering the temperature sensing diode ([0092]);
A first interconnect (10, fig. 5A) and a second interconnect (11, Fig. 5A) formed on a surface of the intermediate insulation film ([0092]);
A first through interconnect (32, Fig. 5B) extending through the intermediate insulation film and [electrically] connecting the first interconnect (10, Fig. 5A) and the first semiconductor region (22, Fig. 5B) ([0092]); and
A second through interconnect (30, Fig. 5B) extending through the intermediate insulation film and connecting the second interconnect (11, Fig. 5A) and the second semiconductor region (23, Fig. 5B) ([0092]).
Regarding claim 9, Nakano discloses the temperature sensing diode includes multiple diode cells arranged in one direction and connected in series to each other ([0126]).
Regarding claim 10, Nakano discloses the multiple diode cells include a first diode cell and a second diode cell that are adjacent to each other in an arrangement direction of the multiple diode cells ([0126]), wherein the structure of the diode cells are identical ([0125]-[0126]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakano (U.S. 2016/0241018 A1) as applied to claim 1 above, and further in view of Umeki (U.S. 2021/0210485 A1).
Regarding claim 2, Nakano discloses the second semiconductor region (23, Fig. 5B) annularly surrounds the first semiconductor region (22, Fig. 5B), and the second semiconductor region (23, Fig. 5B) includes an inner surface joined to the first semiconductor region (22, Fig. 5B) ([0088]). Yet, Nakano does not disclose the first semiconductor region is circular. However, Umeki discloses a first semiconductor region (116, Fig. 14) is circular ([0268]) and a second semiconductor region (116, Fig. 14) includes an inner circumferential surface joined to a circumferential surface of the first semiconductor region along an entire perimeter of the circumferential surface of the first semiconductor region, and an outer surface being quadrangular (Fig. 14) ([0269]). Because both Nakano and Umeki teach methods of forming anode and cathode regions of diode devices, it would have been obvious to one skilled in the art at the time the invention was effectively filed to substitute one method for the other to achieve the predictable result of forming the first semiconductor region as circular as viewed in a thickness direction. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim(s) 13 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakano (U.S. 2016/0241018 A1) as applied to claim 1 above, and further in view of Pluntke et al. (WO 2016066329; “Pluntke”; references to English translation).
Regarding claims 13 and 16, Nakano discloses the temperature sensing diode includes multiple diode cells wherein the structure of the diode cells are identical ([0125]-[0126]). Yet, Nakano does not disclose the diode cells includes a third semiconductor region of the first conductive type formed as a thin film on the surface of the insulation film and a fourth semiconductor region of the second conductive type formed as a thin film on the surface of the insulation film, the third semiconductor region annularly surrounds the second semiconductor region and includes an inner surface joined to an outer surface of the second semiconductor region, and the fourth semiconductor region annularly surrounds the third semiconductor region and includes an inner surface joined to an outer surface of the third semiconductor region. However, Pluntke discloses forming diode cells with multiple semiconductor circular regions annularly surrounding or concentric with each other in alternating conductivity types ([0052], [0084]-[0088]; Fig. 3d). Because both Nakano and Pluntke teach methods of forming temperature sensing diodes, it would have been obvious to one skilled in the art at the time the invention was effectively filed to substitute one method for the other to achieve the predictable result of arranging the diode cells with multiple semiconductor circular regions annularly surrounding or concentric with each other in alternating conductivity types. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakano (U.S. 2016/0241018 A1) as applied to claim 1 above, and further in view of Kmetec et al. (U.S. 2012/0248988 A1; “Kmetec”).
Regarding claim 17, Nakano discloses a temperature sensing diode (20, Fig. 5B) ([0088]) but does not disclose a protection diode connected in antiparallel to the temperature sensing diode. However, Kmetec discloses antiparallel connecting a protection diode to another diode ([0002]) to protect the latter against static electricity or reversed voltage. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Nakano with a protection diode connected in antiparallel, as taught by Kmetec, so as to protect the temperature sensing diode against static electricity or reversed voltage.
Allowable Subject Matter
Claims 7-8, 11-12 and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/REEMA PATEL/Primary Examiner, Art Unit 2812 2/2/2026