DETAIL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Applicant’s filing on 09/13/2023.
Claim Objections
Claims 1, 26, 28 and 52 are objected to because of the following informalities:
Regarding independent claim 1, please amend phrase “silicon carbide” to – “silicon-carbide”-.
Regarding independent claim 26, please amend phrase “silicon carbide” to – “silicon-carbide”-.
Regarding claim 28, please amend phrase “silicon carbide” to – “silicon-carbide”-.
Regarding independent claim 52, please amend phrase “silicon carbide” to – “silicon-carbide”-.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6, 10 and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsuzuki et al. (“Ref 434”, US Pat 4760434, from Applicant’s submitted IDS).
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Above annotated Fig. 2, 13, 16a and 20 are from Applicant’s own invention provided for comparison purposes
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Above annotated Fig. 1-3 are from Tsuzuki et al. (“Ref 434”, US Pat 4760434)
Regarding independent claim 1, Ref 434 teaches (Fig. 1-9; col. 2 L59-col. 6 L55) a transistor (Fig. 3; vertically overlapping arranged power MOSFET: Transistor 22, minimum gate-to-source voltage clamp circuit ‘resistor 271, cathode-to-anode connected Zener diode 28’, 22’s gate resistance 272 and short-circuit protection circuit ‘series connected anode-to-cathode diode(s) 25, resistor 273, transistor 26’), comprising:
a silicon-carbide based semiconductor layer structure (Fig. 2; SiC layered Fig. 3, wherein the semiconductor layer includes 22’s source at the top and 22’s drain being at the bottom);
a first current terminal (22’s drain);
a second current terminal (22’s source, which is connecting 28’s anode);
a gate terminal (22’s gate, which is connecting 28’s cathode, via 271); and
a minimum gate terminal-to-second current terminal voltage clamp circuit (minimum gate-to-source voltage clamp circuit ‘resistor 271, cathode to anode connected Zener diode 28’. Note that a forward voltage drop of the taught clamp circuit’s, corresponds to a voltage to which the 22’s minimum gate terminal-to-second (i.e., source) current terminal voltage is clamped) that is coupled between the gate terminal (22’s gate) and the second current terminal (22’s source terminal).
Regarding claim 2, Ref 434 teaches (Fig. 1-9; col. 2 L59-col. 6 L55)
wherein the minimum gate terminal-to-second current terminal voltage clamp circuit comprises at least one diode (minimum gate-to-source voltage clamp circuit ‘resistor 271, cathode to anode connected Zener diode 28’. Note that a forward voltage drop of the taught clamp circuit’s, corresponds to a voltage to which the 22’s minimum gate terminal-to-second (i.e., source) current terminal voltage is clamped), and
the first current terminal and the second current terminal are on opposed major surfaces of the semiconductor layer structure (Fig. 2; SiC layered Fig. 3, wherein the semiconductor layer includes 22’s source at the top and 22’s drain being at the bottom).
Regarding claim 3, Ref 434 teaches (Fig. 1-9; col. 2 L59-col. 6 L55)
wherein a cathode of the at least one diode is coupled to the gate terminal (22’s gate, which is connecting 28’s cathode, via 271) and an anode of the at least one diode is coupled to the second current terminal (22’s source, which is connecting 28’s anode).
Regarding claim 6, Ref 434 teaches (Fig. 1-9; col. 2 L59-col. 6 L55)
wherein the at least one diode comprises a single diode, and a forward voltage drop of the single diode corresponds to a voltage to which the minimum gate terminal-to-second current terminal voltage is clamped (minimum gate-to-source voltage clamp circuit ‘resistor 271, cathode to anode connected Zener diode 28’. Note that a forward voltage drop of the taught clamp circuit’s, corresponds to a voltage to which the 22’s minimum gate terminal-to-second (i.e., source) current terminal voltage is clamped).
Regarding claim 10, Ref 434 teaches (Fig. 1-9; col. 2 L59-col. 6 L55)
wherein the semiconductor layer structure (Fig. 3) comprises:
a drift region having a first conductivity type (N- type 112 operating as a drift region, which is same as Applicant’s Fig. 14’s 120);
a first well region (i.e., p type 292)
having a second conductivity type (p type)
in an upper portion of the drift region (N- type 112 operating as a drift region, which is same as Applicant’s Fig. 14’s 120);
a first implanted region (i.e., each diode 25 & 28’s included pn/junction region is implanted on gate oxide 45) in the first well region (i.e., p type 292),
the first implanted region (i.e., each diode 25 & 28’s included pn/junction region is implanted on gate oxide 45)
having the first conductivity type (i.e., p type junction); and
a second implanted region (i.e., each diode 25 & 28’s included pn/junction region is implanted on gate oxide 45) that has the second conductivity type (n type junction);
at least one diode comprises a first diode (i.e., both Zener diode 25 and diode 28 is interposed between regions 13 and 12) that comprises the first and second implanted regions (i.e., each diode 25 & 28’s included pn/junction region is implanted on gate oxide 45).
Regarding independent claim 26, Ref 434 teaches (Fig. 1-9; col. 2 L59-col. 6 L55) a transistor (Fig. 3; vertically overlapping arranged power MOSFET: Transistor 22, minimum gate-to-source voltage clamp circuit ‘resistor 271, cathode-to-anode connected Zener diode 28’, 22’s gate resistance 272 and short-circuit protection circuit ‘series connected anode-to-cathode diode(s) 25, resistor 273, transistor 26’), comprising:
a silicon-carbide based semiconductor layer structure (Fig. 2; SiC layered Fig. 3, wherein the semiconductor layer includes 22’s source at the top and 22’s drain being at the bottom);
a first current terminal (22’s drain);
a second current terminal (22’s source, which is connecting 28’s anode);
a gate terminal (22’s gate, which is connecting 28’s cathode, via 271); and
a circuit (any one of a) minimum gate-to-source voltage clamp circuit ‘resistor 271, cathode-to-anode connected Zener diode 28’ or b) short-circuit protection circuit ‘series connected anode-to-cathode diode(s) 25, resistor 273, transistor 26’) comprising at least one diode that is coupled anode-to-cathode between the second current terminal (22’s source’s coupled to 28’s anode) and the gate terminal (22’s gate coupled to 28’s cathode).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 28 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Ref 434 (US Pat 4760434).
Regarding claim 28, Ref 434 teaches (Fig. 1-9; col. 2 L59-col. 6 L55) wherein the at least one diode (zener diode 25 or diode 28 both arranged on 112) is in the silicon carbide based semiconductor layer structure (112), and wherein the at least one diode is a single diode and a forward voltage drop of the single diode having a value (i.e., 28 formed using or more series connected diodes and included anticipated forward voltage drop), except that the value exceeds 4.5 volts.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ref 434’s transistor to include taught forward voltage drop of the single diode’s value to exceed a specific value, as disclosed by Ref 434, as doing so would have provided an improved targeted temperature based detection and protection for overall transistor or device, as taught by Ref 434 (abstract), since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Please note that in the instant application, applicant has not disclosed any criticality for the claimed limitations.
Regarding claim 30, Ref 434 teaches (Fig. 1-9; col. 2 L59-col. 6 L55) wherein an absolute value of a reverse voltage drop of the single diode exceeds a maximum on-state gate terminal-to-second current terminal voltage of the transistor (minimum gate-to-source voltage clamp circuit ‘resistor 271, cathode to anode connected Zener diode 28’. Note that 28 is known to have usual reverse voltage drop, but with the aid of resistor performing a forward voltage drop of the taught clamp circuit’s, corresponds to a voltage to which the 22’s minimum gate terminal-to-second (i.e., source) current terminal voltage is clamped).
Claims 42, 45-47 are rejected under 35 U.S.C. 103 as being unpatentable over Ref 434 (US Pat 4760434), in view of Wendt et al. (“Wendt”, US Pub 2007/0290738).
Regarding claim 42, Ref 434 teaches (Fig. 1-9; col. 2 L59-col. 6 L55) the at least one diode comprises a plurality of bidirectional diodes (i.e., Zener diode 25. Applicant also claims Zener diode or associated antiparallel connected diode Dfw having the same bidirectional characteristics; see Spec., Para 65, 93, 95, 132).
However, Ref 434 fails to teach the use of plurality of bidirectional diodes.
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Above annotated Fig. 4-8, from Wendt et al. (“Wendt”, US Pub 2007/0290738); see Para 63-68, 72-99
However, Wendt teaches (Fig. 4-8; Para 63-68, 72-79) the use of plurality of bidirectional diodes (Fig. 4-8; protection circuit includes in series connected plural diodes (for example, between gate to drain of LDOMOS includes series connected diode(s) (MV3, MV2, MV1, LV1, D1, D2, D3’)).
[Additional Examiner’s NOTE: Wendt teaches (Fig. 4-8; Para 63-68, 72-79) a transistor semiconductor die (Fig. 4; use of semiconductor substretae die; Para 27, 72) comprising: short circuit protection circuitry (Fig. 4-8; protection circuit includes in series connected plural diodes (for example, between gate to drain of LDOMOS includes series connected diode(s) (MV3, MV2, MV1, LV1, D1, D2, D3’) of zener/pn-junctions types with corresponding associated ‘+’ and ‘-‘ temperature coefficient with respect to a voltage drop across the respective diode; and the taught protection circuit is used to control on/off of LDMOS) comprising at least a first diode (Fig. 4-8; protection circuit includes in series connected plural diodes (for example, between gate to drain of LDOMOS includes series connected diode(s) (MV3, MV2, MV1, LV1, D1, D2, D3’)) coupled in series between the control terminal (Fig. 4-8; i.e., LDMOS’s gate terminal with voltage Vg connecting anode of a Zener diode, such as MV3-4) and the second current terminal (Fig. 4-8; LDMOS’s drain terminal with voltage Vd), wherein the first diode (Fig. 4-8; protection circuit includes in series connected plural diodes (for example, between gate to drain of LDOMOS includes series connected diode(s) (MV3, MV2, MV1, LV1, D1, D2, D3’)) has a negative temperature coefficient (p-n junction are always to known include – temp. coeff.; Para 83) with respect to a voltage drop across the first diode so that the first diode turns on in a short circuit protection mode of operation (Fig. 4-8; protection circuit includes in series connected plural diodes (for example, between gate to drain of LDOMOS includes series connected diode(s) (MV3, MV2, MV1, LV1, D1, D2, D3’))].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ref 434’s transistor’s included diode to further include the use of plurality of bidirectional diodes, as disclosed by Wendt, as doing so would have provided a varied clamping voltage capabilities to control the switching operation of the transistor device wherein the required clamping voltage won’t exceed the maximum rating of any temperature, thus improving the overall lifespan of the transistor semiconductor die, while maintaining reduced scape use of such transistor semiconductor die, as taught by Min (abstract, Para 4-9, 66, 68, 73-74, 83).
Regarding claim 45, Ref 434 teaches (Fig. 1-9; col. 2 L59-col. 6 L55)
wherein the semiconductor layer structure (Fig. 3) comprises:
a drift region having a first conductivity type (N- type 112 operating as a drift region, which is same as Applicant’s Fig. 14’s 120);
a first well region (i.e., p type 292) having a second conductivity type (p type) in an upper portion of the drift region (N- type 112 operating as a drift region, which is same as Applicant’s Fig. 14’s 120);
a first implanted region (i.e., each diode 25 & 28’s included pn/junction region is implanted on gate oxide 45, where junction being p-type region vs. n type region) in the first well region (i.e., p type 292), the first implanted region having the first conductivity type (i.e., p type junction),
a second implanted region (i.e., each diode 25 & 28’s included pn/junction region is implanted on gate oxide 45, where junction being p-type region vs. n type region) that has the second conductivity type (n type junction),
wherein the plurality of diodes comprises a first diode (i.e., both Zener diode 25 and diode 28 is interposed between regions 13 and 12) that comprises the first and second implanted regions (i.e., each diode 25 & 28’s included pn/junction region is implanted on gate oxide 45).
Regarding claim 46, Ref 434 teaches (Fig. 1-9; col. 2 L59-col. 6 L55) wherein the first implanted region (i.e., each diode 25 & 28’s included pn/junction region is implanted on gate oxide 45, where junction being p-type region vs. n type region) directly contacts a gate structure (See, Fig. 1-3; transistor 22 residing in power region 12 and transistor 26 residing in control region 13. Note that transistor 26 includes ‘gate terminal 26, gate oxide 46’ and transistor 22 includes ‘gate terminal 40 & gate oxide’. Both diode 28 and Zener diode 25 are arranged between control region 13 included transistor 26’s gate structure and power region 12 included transistor 22’s gate structure. Fig. 1 shows gate pad 14 and source bonding pad 15), where the gate structure comprises the gate terminal or a structure that is electrically connected to the gate terminal (See, Fig. 1-3; transistor 22 residing in power region 12 and transistor 26 residing in control region 13. Note that transistor 26 includes ‘gate terminal 26, gate oxide 46’ and transistor 22 includes ‘gate terminal 40 & gate oxide’. Both diode 28 and Zener diode 25 are arranged between control region 13 included transistor 26’s gate structure and power region 12 included transistor 22’s gate structure. Fig. 1 shows gate pad 14 and source bonding pad 15).
Regarding claim 47, Ref 434 teaches (Fig. 1-9; col. 2 L59-col. 6 L55) wherein the second implanted region (i.e., each diode 25 & 28’s included pn/junction region is implanted on gate oxide 45, where junction being p-type region vs. n type region) directly contacts a metal connector (i.e., respective wire/terminals or aluminum electrodes) that is between the gate structure (See, Fig. 1-3; transistor 22 residing in power region 12 and transistor 26 residing in control region 13. Note that transistor 26 includes ‘gate terminal 26, gate oxide 46’ and transistor 22 includes ‘gate terminal 40 & gate oxide’. Both diode 28 and Zener diode 25 are arranged between control region 13 included transistor 26’s gate structure and power region 12 included transistor 22’s gate structure. Fig. 1 shows gate pad 14 and source bonding pad 15) and a source/drain contact that is electrically connected to the second current terminal (Fig. 2-3; see, above annotated 22 &/or 25’s respective source/drain electrical contacts being aluminum electrodes connected to respective source/drain terminals, arranged on top of respective layers).
Claims 52-53 are rejected under 35 U.S.C. 103 as being unpatentable over Ref 434 (US Pat 4760434), in view of Sabri et al. (“Sabri”, US Pub 2020/0295174).
Regarding independent claim 52, Ref 434 teaches (Fig. 1-9; col. 2 L59-col. 6 L55) a transistor (Fig. 3; vertically overlapping arranged power MOSFET: Transistor 22, minimum gate-to-source voltage clamp circuit ‘resistor 271, cathode-to-anode connected Zener diode 28’, 22’s gate resistance 272 and short-circuit protection circuit ‘series connected anode-to-cathode diode(s) 25, resistor 273, transistor 26’), comprising:
a silicon-carbide based semiconductor layer structure (Fig. 2; SiC layered Fig. 3, wherein the semiconductor layer includes 22’s source at the top and 22’s drain being at the bottom);
a first current terminal (22’s drain);
a second current terminal (22’s source, which is connecting 28’s anode) that is electrically connected to a first source/drain contact (Fig. 2-3; see, above annotated 22 &/or 25’s respective source/drain electrical contacts being aluminum electrodes connected to respective source/drain terminals, arranged on top of respective layers); and
a gate structure (See, Fig. 1-3; transistor 22 residing in power region 12 and transistor 26 residing in control region 13. Note that transistor 26 includes ‘gate terminal 26, gate oxide 46’ and transistor 22 includes ‘gate terminal 40 & gate oxide’. Both diode 28 and Zener diode 25 are arranged between control region 13 included transistor 26’s gate structure and power region 12 included transistor 22’s gate structure. Fig. 1 shows gate pad 14 and source bonding pad 15) that includes a gate pad (Fig. 1; 14), …, and one or more gate buses (i.e., gate terminals 40, 47) that electrically connect … to the gate pad (Fig. 1; 14),
wherein the semiconductor layer structure (Fig. 3) comprises:
a drift region having a first conductivity type (N- type 112 operating as a drift region, which is same as Applicant’s Fig. 14’s 120);
a first well region (i.e., p type 292)
having a second conductivity type (p type)
in an upper portion of the drift region (N- type 112 operating as a drift region, which is same as Applicant’s Fig. 14’s 120);
a first implanted region (i.e., each diode 25 & 28’s included pn/junction region is implanted on gate oxide 45) in the first well region (i.e., p type 292),
the first implanted region (i.e., each diode 25 & 28’s included pn/junction region is implanted on gate oxide 45)
having the first conductivity type (i.e., p type junction) and
directly contacting the gate structure (See, Fig. 1-3; transistor 22 residing in power region 12 and transistor 26 residing in control region 13. Note that transistor 26 includes ‘gate terminal 26, gate oxide 46’ and transistor 22 includes ‘gate terminal 40 & gate oxide’. Both diode 28 and Zener diode 25 are arranged between control region 13 included transistor 26’s gate structure and power region 12 included transistor 22’s gate structure. Fig. 1 shows gate pad 14 and source bonding pad 15); and
a second implanted region (i.e., each diode 25 & 28’s included pn/junction region is implanted on gate oxide 45) that has the second conductivity type (n type junction);
wherein the first and second implanted regions (i.e., each diode 25 & 28’s included pn/junction region is implanted on gate oxide 45) comprise
a first diode (i.e., both Zener diode 25 and diode 28 is interposed between regions 13 and 12)
that is interposed in between
the first source/drain contact (Fig. 2-3; see, above annotated 22 &/or 25’s respective source/drain electrical contacts being aluminum electrodes connected to respective source/drain terminals, arranged on top of respective layers) and
the gate structure (See, Fig. 1-3; transistor 22 residing in power region 12 and transistor 26 residing in control region 13. Note that transistor 26 includes ‘gate terminal 26, gate oxide 46’ and transistor 22 includes ‘gate terminal 40 & gate oxide’. Both diode 28 and Zener diode 25 are arranged between control region 13 included transistor 26’s gate structure and power region 12 included transistor 22’s gate structure. Fig. 1 shows gate pad 14 and source bonding pad 15).
However, Ref 434 fails to teach a gate structure that also include a plurality of gate fingers, and the one or more gate buses that electrically connect at least some of the gate fingers to the gate pad.
However, Ref 434 teaches (Fig. 10, 12; col. 7 L3-col. 8 L32) a gate structure (See, Fig. 1-3, 10& 12; transistor 22 residing in power region 12 and transistor 26 residing in control region 13. Note that transistor 26 includes ‘gate terminal 26, gate oxide 46’ and transistor 22 includes ‘gate terminal 40 & gate oxide’. Both diode 28 and Zener diode 25 are arranged between control region 13 included transistor 26’s gate structure and power region 12 included transistor 22’s gate structure. Fig. 1 shows gate pad 14 and source bonding pad 15) that includes a gate pad (Fig. 1; 14), a … gate finger (i.e., although, not explicitly spelled out, but to one of ordinary skill in the art, it appears that Fig. 10’s transistor 70 or Fig. 12’s transistor 74’s sharing gate (i.e., fingering) contact with transistor 22’s gate terminal/bus 40 being a design choice), and one or more gate buses (i.e., gate terminals 40, 47) that electrically connect … the gate finger (i.e., although, not explicitly spelled out, but to one of ordinary skill in the art, it appears that Fig. 10’s transistor 70 or Fig. 12’s transistor 74’s sharing gate (i.e., fingering) contact with transistor 22’s gate terminal/bus 40 being a design choice) to the gate pad (Fig. 1; 14).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ref 434’s gate structure to use gate bus, which is larger conductive lines to connect at least one individual gate finger to a single gate pad, as disclosed by Ref 434, as doing so would have an improved steady hysteresis performance by evenly distributing of the gate voltage/signal, as taught by Ref 434 (col. 8 L L3-27 and col. 8 L19-32).
[Additional Examiner’s NOTE: To one of ordinary skill in the art, following differences are well-known and established difference(s)-
(a) Gate Buses are larger, conductive lines that connect individual gate fingers to a single gate pad, distributing the signal evenly;
(b) Gate Finger (individual, narrow gate electrodes) is a design choice, utilizing an old & established technique for splitting single large transistor into multiple smaller parallel transistors (fingers), sharing a common gate connection. Instead of one long, resistive gate, it’s basically a design choice to have shorter ones, making it easier to lay out high-performance device with better electrical characteristics. Benefit of the gate fingers are following allowance(s) of
increasing total device width (i.e., large transistor’s total width is divided into several smaller widths, each part forming a finger),
while reducing
gate resistance (i.e., sharing same gate input, using same metal wire, connecting all of the SiC gate striped/fingers, but having separate source/drain regions),
parasitic, and
improving matching, which is crucial for analog/RF designs.]
However, Ref 434 explicitly fails to teach a gate structure that also include a plurality of gate fingers, and the one or more gate buses that electrically connect at least some of the gate fingers to the gate pad.
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Above annotated Fig. 3a-d are from Sabri et al. (“Sabri”, US Pub 2020/0295174)
However, Sabri explicitly teaches a gate structure (Fig. 3; Para 40-45, 53-72) that also include a plurality of gate fingers (134), and the one or more gate buses (136) that electrically connect at least some of the gate fingers (134) to the gate pad (132).
[Additional Examiner’s NOTE: From above annotated Fig. d, it is also evident that Sabri furthermore explicitly teaches N type SiC substrate layer 122, N type SiC drift regions 124, well regions 126, source region 128 and drain contact 128]
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ref 434’s gate structure to use one or more gate buses, which is larger conductive lines to electrically connect at least some of the plurality of gate fingers to the gate pad, as disclosed by Sabri, as doing so would have provided an improved steady performance, using compact sizing design choice, while evenly distributing of the gate voltage/signal, as taught by Sabri (Para 5-6).
Regarding claim 53, Ref 434 teaches the first diode (i.e., both Zener diode 25 and diode 28 is interposed between regions 13 and 12) is coupled anode-to-cathode (i.e., 25) between the gate structure (i.e., 22’s gate) and the second current terminal (22’s source).
Allowable Subject Matter
Claims 11, 15-16, 31-32, 35-37, 39-40, 48-50 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 11, cited prior art(s) failed to teach, “the first implanted region directly contacts a gate structure that is electrically connected to the gate terminal and wherein the second implanted region directly contacts a metal connector that is between the gate structure and a source/drain contact that is electrically connected to the second current terminal (source/emitter)”.
Claims 15-16 are depending from claim 11.
Regarding claim 31, cited prior art(s) failed to teach along with other arrangements the semiconductor layer structure further comprises: “a third implanted region that has the second conductivity type and that has a doping concentration that is at least an order of magnitude less than a doping concentration of the second implanted region, where the third implanted region is in between the first implanted region and the second implanted region”.
Claims 32, 35-37, 39-40 are depending from claim 31.
Regarding claim 48, cited prior art(s) failed to teach, “wherein the plurality of diodes further comprises a second diode that is formed in the semiconductor layer structure and that at least partially vertically overlaps the metal connector”.
Claims 49-50 are depending from claim 48.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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Williams et al. (“Williams”, EP 1041634) teaches (Fig. 8, 12-13, 19; Para 71-85, 92-95. Also, see above Figures provided from Williams vs. Applicant’s own invention related Figures for comparison purposes) a transistor semiconductor die (Figs. 8, 12-13, 19; i.e., ‘transistor semiconductor 800’ various connection and die layers are shown; abstract) comprising: a first current terminal (Fig. 19; drain_D of 800) and a second current terminal (Fig. 19; source_S of 800); a control terminal (Fig. 19; gate_G of 800); a semiconductor structure (800 is shown to be connected in anti-parallel with freewheeling diode. Additionally, Fig. 12 shows 800 comprising a drift layer, such as, N+substrate 1222 has an N-epi layer 1220. Note that William’s taught drift layer is same as Applicant’s drift layer 22) between the first current terminal (Fig. 19; drain_D of 800) and the second current terminal (Fig. 19; source_S of 800); and a short circuit protection circuitry (Fig. 8, 12, 19; series connected diodes, generating ‘Vclamp1, Vclamp2’ coupled between control terminal gate_G of min transistor 802 and the 2nd current terminal ‘source_S or drain_D’ of 802; and a current limiting resistor R1; Para 83-85) comprising at least a first diode (Fig. 19; series connected at least one or more diodes) coupled in series between the control terminal (Fig. 19; gate_G of 800) and the second current terminal (Fig. 19; source_S of 800), wherein the first diode… with respect to a voltage drop across the first diode so that the first diode turns on in a short circuit protection mode of operation.
[Additional NOTE. William furthermore teaches
the semiconductor structure (800) configured such that a resistance (i.e., R1) between the first current terminal (Fig. 19; drain_D of 800) and the second current terminal (Fig. 19; source_S of 800) is based on a control signal (i.e. Fig. 20, Vlogic passed thru gate_G of 2000 (which is similar to 800), abstract) provided at the control terminal (Fig. 19; gate_G of 800);
a short circuit protection circuitry (Fig. 8, 12, 19; series connected diodes, generating ‘Vclamp1, Vclamp2’ coupled between control terminal gate_G of min transistor 802 and the 2nd current terminal ‘source_S or drain_D’ of 802; and a current limiting resistor R1; Para 83-85) that resides on (See, Fig. 12A; shows diodes and R1 being on the same drift layer, too; Para 83-85) the drift layer (Fig. 12; N+substrate 1222 has an N-epi layer 1220. Note that this is same as Applicant’s drift layer 22. Furthermore, from Williams Fig. 12A, it is apparent that there has to be some type of wire/cable connection of the short circuit protection circuitry elements (i.e. of the diode (which are generating Vclamp1, Vclamp2) and resistor R1) with corresponding 1st-3rd current terminals of the transistor semiconductor die (800), wherein the transistor’s current terminals are in direct contact with the taught drift layer, and therefore one way or another the short circuit protection circuit’s elements are establishing some type of connection with the taught drift layer, not to mention they are located on top of the drift layer, even if there is a gate-oxide region)]
Min (US Pub 2008/0272828) teaches old and established use of pn-junction diode(s) having a negative temperature coefficient with respect to a voltage drop across the diode(s) (See, Para 4).
Sakurai et al. (“Sakurai”, US Pat 5631494) teaches (Fig. 1; col. 5 L28-col. 6 L46 & col. 14 L66-col. 15 L9) short circuit protection circuitry (DZ, R1, S3) comprising at least a first diode(s) (i.e., Dz coupling between gate/base (via R3, same as Applicant’s Rig) and a 2nd current terminal of semiconductor structure S1) turns on in a short circuit protection mode of operation (i.e., when ON-signal voltage at terminal T3 applied to Dz & S3; col. 6. L17-46).
Briere (US Pub 2015/0162321) teaches (Fig. 1-3, 220, para 3, 16, 21, 25, 30 and 35-36) the semiconductor structure comprises silicon carbide (para 3, 25, 21, 16).
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to NUSRAT QUDDUS whose telephone number is (571)270-7921. The examiner can normally be reached on M-TH 9-4 PM ET.
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/NUSRAT QUDDUS/Examiner, Art Unit 2838