CTNF 18/466,215 CTNF 92321 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Continued Examination Under 37 CFR 1.114 07-42-04 AIA A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/22/2026 has been entered. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1, 3-8, 10-16, 21, and 24-25 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by CHENG et al. (US 20200044061 A1, hereinafter Cheng ) With regards to claim 1 , Cheng discloses a transistor (FIGS. 1A-21B) comprising: a substrate; (substrate 11) a gate (gate structure 108 including spacers 62) around a plurality of channels (semiconductor wire channels 20) and directly upon the substrate; and a tapered inner spacer (spacer 60) directly upon the substrate and below a bottommost channel of the plurality of channels, the tapered inner spacer comprising a base region (region contacting gate 108) that extends inwardly beyond a plane that is coplanar with a sidewall of the gate, and into a region occupied by the gate such that conductive material of the gate is reduced adjacent to the base region (See Annotated FIG. 1A, where the base region extends into the gate 108 and reduces the amount of gate region from a rectangle into a “dented” rectangle. See also Response to Arguments.) wherein the inward extension of the base region reduces a gate length of the gate adjacent to the base region relative to a gate length of the gate above the bottommost channel.. (See Annotated FIG. 1A, showing the spacer 60 extending inwardly beyond the plane that is coplanar with a sidewall of the gate, See also response to Arguments) PNG media_image1.png 804 522 media_image1.png Greyscale With regards to claim 3 , Cheng discloses the transistor of claim 1, further comprising: a source/drain (S/D) region (source/drain 80) directly upon the tapered inner spacer and directly upon respective end surface of the plurality of channels. (See FIG. 1A) With regards to claim 4 , Cheng discloses the transistor of claim 1, further comprising a gate spacer (gate dielectric 104) that is located above a topmost channel of the plurality of channels. (See FIG. 1A) With regards to claim 5 , Cheng discloses the transistor of claim 4, wherein the gate comprises a first gate length (vertical length adjacent to the gate spacer 104) and a second gate length (length adjacent to the spacer 60) adjacent to the base region and wherein the second gate length is less than the first gate length. (See FIG. 1A, showing the second length less than the first length) With regards to claim 6 , Cheng discloses the transistor of claim 4, wherein the tapered inner spacer comprises a mirrored inner spacer region (mirrored top portions of the spacer 60) and wherein respective sidewalls of the mirrored inner spacer region are coplanar with respective sidewalls of the gate spacer. (See FIG. 1A, showing the coplanarity) With regards to claim 7 , Cheng discloses the transistor of claim 1, wherein the base region comprises a bottom surface (bottom surface of spacer 60) and a tapered surface (tapered sidewall of spacer 60) with a vertical thickness therebetween that decreases in proportion to a degree to which the base region extends inwardly beyond the plane that is coplanar with the sidewall of the gate. (See FIG. 1A) With regards to claim 8 , Cheng discloses a transistor comprising: (gate structure 108 including spacers 62) around a plurality of channels (semiconductor wire channels 20) a first tapered inner spacer (spacer 60) below a bottommost channel of the plurality of channels, the first tapered inner spacer comprising a first base region (left region contacting gate 108) that extends inwardly beyond a first plane that is coplanar with a first sidewall of the gate and into a region occupied by the gate such that conductive material of the gate is reduced adjacent to the base region (See Annotated FIG. 1A, where the base region extends into the gate 108 and reduces the amount of gate region from a rectangle into a “dented” rectangle. See also Response to Arguments.); and a second tapered inner spacer (bottommost layer 102) below a bottommost channel of the plurality of channels, the second tapered inner spacer comprising a second base region (right region contacting gate 108) that extends inwardly beyond a second plane that is coplanar with a second sidewall of the gate that is opposing the first sidewall of the gate, herein relative to a gate length of the gate above the bottommost channel, the first base region and the second base region reduce a gate length of the gate between the first base region and the second base region. (See Annotated FIG. 1A, showing the extension coplanar with the second sidewall of the gate 108, see also response to Arguments) With regards to claim 10 , Cheng discloses the transistor of claim 8, further comprising: a first source/drain (S/D) region (left source/drain 80) directly upon the first tapered inner spacer and directly upon respective first end surfaces of the plurality of channels; and a second S/D region (right source/drain 80) directly upon the second tapered inner spacer and directly upon respective second end surfaces of the plurality of channels. With regards to claim 11 , Cheng discloses the transistor of claim 8, further comprising a gate spacer (gate dielectric 104) that is located above a topmost channel of the plurality of channels. (See FIG. 1A) With regards to claim 12 , Cheng discloses the transistor of claim 11, wherein the gate comprises a first gate length (vertical length adjacent to the gate spacer 104) and a second gate length (length adjacent to the spacer 60) adjacent to the base region and wherein the second gate length is less than the first gate length. (See FIG. 1A, showing the second length less than the first length) With regards to claim 13 , Cheng discloses the transistor of claim 11, wherein the first tapered inner spacer comprises a first mirrored inner spacer region, (left mirrored top portions of the spacer 60) wherein the second tapered inner spacer comprises a second mirrored inner spacer region, (right mirrored top portions of the spacer 60) wherein respective sidewalls of the first mirrored inner spacer region are coplanar with respective sidewalls of the gate spacer, (See FIG. 1A, showing the coplanarity) and wherein respective sidewalls of the second mirrored inner spacer region are coplanar with respective sidewalls of the gate spacer. (See FIG. 1A, showing the coplanarity) With regards to claim 14 , Cheng discloses the transistor of claim 8, wherein the first base region comprises a first bottom surface (bottom surface of spacer 60) and a tapered surface (tapered sidewall of spacer 60) with a vertical thickness therebetween that decreases in proportion to a degree to which the first base region extends inwardly beyond the first plane. (See FIG. 1A) With regards to claim 15 , Cheng discloses the transistor of claim 8, wherein the first base region and the second base region are merged. (See FIG. 1A, where the regions are merged via the gate 108) With regards to claim 16 , Cheng discloses the transistor of claim 15, wherein the merged first base region and second base region is between the gate and a substrate. (see Fig. 1A, showing the merged area between the gate 108 and the substrate 11) With regards to claim 21 , Cheng discloses a transistor comprising: a gate (gate 108) around a channel (channel 20) that extends beyond both a first sidewall of the gate and a second sidewall of the gate; (See FIG. 1A) and a tapered inner spacer (spacer 60) directly upon the gate and directly upon a bottom surface of the channel, the tapered inner spacer comprising a base region that protrudes beyond the first sidewall of the gate toward the second sidewall of the gate, and into a region occupied by the gate such that conductive material of the gate is reduced adjacent to the base region (See Annotated FIG. 1A, where the base region extends into the gate 108 and reduces the amount of gate region from a rectangle into a “dented” rectangle. See also Response to Arguments.) wherein the base region reduces a gate length of the gate adjacent to the base region relative to a gate length of the gate above the channel. (See Annotated FIG. 1A, showing the protrusion reducing the gate length, see also Response to Arguments) With regards to claim 22 , Cheng discloses the transistor of claim 21, wherein the base region reduces a gate length of the gate adjacent to the base region. (See FIG. 1A, showing the reduction of the gate 108 by the base region of the spacer 60 by cutting into the gate 108) With regards to claim 23 , Cheng discloses the transistor of claim 21, wherein the gate has a first gate length (vertical length adjacent to the gate spacer 104) above the channel and a second gate length (length adjacent to the spacer 60) adjacent to the base region and wherein the second gate length is less than the first gate length. (See FIG. 1A, showing the second length less than the first length) With regards to claim 24 , Cheng discloses the transistor of claim 23, wherein the tapered inner spacer further comprises a mirrored inner spacer region (mirrored top portions of the spacer 60) and wherein the gate has the first gate length adjacent to the mirrored inner spacer region. (see FIG. 1A, where every portion of the device is adjacent to each other) With regards to claim 25 , Cheng discloses the transistor of claim 21, wherein the base region comprises a bottom surface(bottom surface of spacer 60) and a tapered surface (tapered sidewall of spacer 60) with a vertical thickness therebetween that decreases in proportion to a degree to which the base region protrudes beyond the first sidewall of the gate toward the second sidewall of the gate. (See FIG. 1A) Response to Arguments 07-37 AIA Applicant's arguments filed 05/22/2026 have been fully considered but they are not persuasive. Applicant argues that there is no region that extends beyond a plane of the gate. Examiner has annotated FIG. 1A, clearly showing the spacer 60/base region extending beyond a plane of the gate into a region occupied by the gate. Examiner notes that the term “region” is incredibly broad, and a ‘region occupied by the gate” could be interpreted as the whole device, which would still meet the requirements of claims 1, 8, and 21. Therefore, claims 1, 3-8, 10-16, 21, and 24-25 are properly rejected . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yang et al. (US 20210296439 A1) – gate all around device with tapered sidewalls . Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812 Application/Control Number: 18/466,215 Page 2 Art Unit: 2812 Application/Control Number: 18/466,215 Page 3 Art Unit: 2812 Application/Control Number: 18/466,215 Page 4 Art Unit: 2812 Application/Control Number: 18/466,215 Page 5 Art Unit: 2812 Application/Control Number: 18/466,215 Page 6 Art Unit: 2812 Application/Control Number: 18/466,215 Page 7 Art Unit: 2812 Application/Control Number: 18/466,215 Page 8 Art Unit: 2812 Application/Control Number: 18/466,215 Page 9 Art Unit: 2812
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