Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see page 5, lines 6-12, filed 7/21/2026, with respect to the drawings have been fully considered and are persuasive. The objections of the drawings has been withdrawn.
Applicant's arguments filed 7/23/2026 with respect to claims 12-14 under 35 USC § 102 have been fully considered but they are not persuasive.
Applicant argues that Watanabe does not disclose the base of groove 11 being situated in body region 4. However, under broadest reasonable interpretation, the trench base is interpreted to mean the lower portion of the trench, not only its bottom surface. Therefore, a portion of the trench base is within the body region 4, while a portion of the trench base is laterally enclosed by the n-doped region as required by the subsequent limitation of claim 12 “and provided below the trench base and the gate trench is an n-doped region, the n-doped region at least partially laterally enclosing the trench base.”
NOTE: Applicant may overcome the rejection as written by restating it to read, in part “the source region including a gate trench that extends from the source region into the barrier layer, wherein a trench base of the gate trench is entirely situated in the barrier layer, and provided below the trench base and the gate trench is an n-doped region, the n-doped region protruding into the barrier layer and at least partially laterally enclosing the trench base.”
However, this will not place it in condition for allowance, as Darwish et al. (US Pub 20040227182), hereinafter referred to as Darwish, in Fig. 22 teaches a gate trench (Darwish, 174, Fig. 22) wherein the trench is entirely within the body (Darwish, 103, Fig. 22) and the N-doped region (Darwish, 120, Fig. 22) protrudes into the body region to partially laterally surround the trench.
Applicant’s arguments filed 7/17/2026 with regards to claims 15-18 have been fully considered but they are not persuasive Applicants arguments regarding claims 15-18 are dependent on their argument to claim 12. Argument to claim 12 was found unpersuasive, rendering these arguments moot.
Claim Rejections -- 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 12-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Watanabe (US Pub 20190081171), hereinafter referred to as Watanabe.
Regarding claim 12, Watanabe teaches a semiconductor component (Watanabe, 100c, Fig. 20, para. 97) configured as a trench metal insulator semiconductor field effect transistor (MISFET), comprising:
a substrate made of gallium nitride (GaN) (Watanabe, SB, Fig. 20, paara.45);
a drift layer situated on the substrate (Watanabe, 3, Fig. 20, para. 57);
a barrier layer (Watanabe, 4, Fig. 20, para. 50);
and a source region situated above the barrier layer (Watanabe, 5, Fig. 20, para. 72),
the source region including a gate trench that extends from the source region into the barrier layer (Watanabe, 11, Fig. 20 para. 54, 55),
wherein a trench base of the gate trench is situated in the barrier layer, and provided below the trench base and the gate trench is an n-doped region (Watanabe, Fig. 20, the trench base extends through barrier label 4 and into 13) ,
the n-doped region at least partially laterally enclosing the trench base (Watanabe, Fig. 20, 13 partially laterally encloses the base of 11),
the n-doped region is created using implantation and extends into the drift layer (Watanabe, para. 91, 100).
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Regarding claim 13, Watanabe teaches the semiconductor component as recited in claim 12, wherein the n-doped region laterally encloses a lower section of the gate trench up to a predefined height that is above a gate oxide layer that is formed in the trench base (Watanabe, para. 91. discusses the lower end of the groove (trench) terminating in the n-doped region and Fig. 20 shows the n-doped region terminating at a height above the gate oxide layer (Watanabe, 7, Fig. 20))
Regarding claim 14, Watanabe teaches the semiconductor component as recited in claim 12, wherein the n-doped region is formed at a boundary region between the barrier layer and the drift layer (Watanabe, Fig. 20, shows 13 between 3 and 4 in the z axis (see diagram above)), and the n-doped region has a larger width extension than the gate trench (Watanabe, Fig. 20, 13 is wider than 11).
Claim Rejections -- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe as applied to claim 12 above, and further in view of JIANG, et al.: "A Novel SiC Trench MOSFET Structure with Enhanced Short Circuit Robustness," IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDS Asia), (2021), pp. 440-443, hereinafter referred to as Jiang.
Regarding claim 15, Watanabe teaches the semiconductor component as recited in claim 12, but does not teach, wherein the barrier layer includes an area, neighboring the drift layer, with increased p-doping compared to a remaining portion of the barrier layer.
However, Jiang teaches a MOSFET structure with a gate structure (Jiang, Gate oxide, Fig. 1) in a barrier layer (Jiang, Pwell, Fig 1.(b)) where the gate structure is partially laterally surrounded by and n-doped region (Jiang, N-implanted, Fig. 1(b)), which contacts the drift layer (Jiang, SiC N-epi layer, Fig. 1(b)) wherein the barrier layer includes an area (Jiang, P 1*1018 cm-3 Fig. 1 (b)), neighboring the drift layer, with increased p-doping compared to a remaining portion of the barrier layer (Jiang, Fig. 1, the ratio is approximately 20:3).
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Therefore, it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the MOSFET of Watanabe with the heavily p-doped layer of Jiang, thereby optimizing on-resistance, breakdown voltage and maximum electric field in the gate oxide (Jiang, I. A. Key Parameters of Device).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe as applied to claim 12 above, and further in view of Jiang and Darwish.
Regarding claim 16, Watanabe teaches the semiconductor component as recited in claim 12, but does not teach wherein an n-doping of then-doped region is selected to be so high that it overcompensates for a p-doping of the barrier layer.
However, Darwish teaches a heavily n-doped region (Darwish, 130, Fig. 12O) below a gate structure where the increased doping decreases the on-resistance and increases current spreading (Darwish, paras. 65 and 77).
Additionally, Jiang teaches that the on-resistance is reduced and the electrical field is increased as the n-dopant concentration is increased, with the optimal performance occurring where the n-dopant concentration is 2*1017 cm-3. This is higher than the P-well value of 1.5*1017 cm-3.
Thus, the dopant concentration of the n-doped region is not merely a process parameter but a result-effective variable:If too low, the p-dopants in the barrier level will overcome it.If too high, the maximum electric field in the gate oxide will be too high and potentially damage the device (Jiang, I. Introduction and Fig. 7). Within the optimal window, the on resistance, electric field and breakdown voltage are mutually optimized. Because the prior art recognizes that the dopant levels in the n-doped region directly affects on-resistance, electric field strength and breakdown voltage, and the prior art shows the electric field strength rising as the dopant concentration increases (Jiang, Fig. 7), leading to damage to the device, the dopant concentration is a result-effective variable. Therefore, it wouldhave been obvious for one of ordinary skill in the art to optimize this variable through routineexperimentation. The selection of a concentration sufficient to overcome the barrier layer, while avoiding damage would be a predictable result of such optimization, absent evidence of unexpected results or criticality associated specifically with overcoming the p-doped region.(See MPEP 2144.05 II).
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe as applied to claim 12 above, and further in view of Darwish.
Regarding claim 17, Watanabe teaches the semiconductor component as recited in claim 12, but does not teach wherein the drift layer, except for n-doped regions that extend into the drift layer, is free of deeper p-doped regions, situated therein.
However, Darvish teaches a MOSFET device, with an n-doped region (Darwish, 130, 116, Fig. 12O) below the gate structure, and there are no p-doped regions below the drift layer (Darwish, 116, 12O).
Therefore, it would have been obvious to one having ordinary skill in the art to combine the MOSFET of Watanabe with the arrangement of Darwish in order to decreases the on-resistance and increases current spreading (Darwish, paras. 65 and 77).
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Regarding claim 18, Watanabe teaches the semiconductor component as recited in claim 12, wherein the n-doped region is created using implantation into an epitaxial layer (Watanabe, EP, Fig. 20, paras 83, 91).
Watanabe is silent on whether the material of the epitaxial layer is silicon.
However, Darwish teaches a MOSFET where the substrate may be silicon (Darwish, para. 3).
Therefore, it would be obvious to one having ordinary skill in the art before the filing date of the invention to select the silicon of Darwish as the epitaxial layer of Watanabe, allowing cells to be more densely packed and reducing the on-resistance of the device (Darwish, para. 3).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fuergut et al. (U. S. 20200013723) teaches a gate trench which passes through a p body and a p-emitter layer and is partially laterally enclosed by an n-type layer.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:30-5:30.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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