Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to an Office action mailed on 12/31/2025 (“12-31-25 OA”), the Applicant amended claims 1, 3, 10, 12, 19 and 20 and amended the title on 03/31/2026.
Currently, claims 1-20 are pending.
Information Disclosure Statement
The Applicant submitted an information disclosure statement (IDS) on 03/31/2026 ("03-31-26 IDS") after the 12-31-25 OA. Since the Applicant has met the provisions of 37 CFR 1.97, the 03-31-26 IDS is in compliance and is being considered by the examiner.
Response to Arguments
Applicant’s amendments to the title have overcome the objection to the Specification as set forth on page 2 under line item number 1 of the 12-31-25 OA.
Applicant’s amendments to claims 3, 12 and 19 have overcome the 35 U.S.C. 112(b) rejection of claims 3-5, 12-14, 19 and 20 as set forth on page 3 under line item number 2 of the 12-31-25 OA.
Substantive amendments to the independent claims 1, 10 and 19 required further consideration and search. New grounds of rejections are provided below.
Despite the substantive amendments to the independent claims 1, 10 and 19, previously-cited Lee still reads at least on the amended independent claims 1, 10 and 19.
On page 12 of the 03-26-26 Response, the Applicant argues that “Nowhere does Lee teach providing a positive polarity pin with an intersecting structure to improve its visual distinguishability from negative polarity pins” as “Lee’s solution is to designate certain pads as dummy pads in high-speed signal regions so that the signal pads transmitting positive and negative signals are placed side by side in the same row. Nowhere does Lee address or even recognize signals are placed side by side in the same row.”
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (as argued on page 12 of the 03-26-26 Response) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The Applicant’s arguments appear to be directed to the operational characteristics of a chip-on-film which may not structurally distinguish the claimed chip-on-film over the chip-on-film taught by Lee. As currently amended, since Lee teaches the amended feature “wherein a shape (L-shaped) of the positive polarity pin is different from a shape (not L-shaped) of each of the plurality of negative polarity pins,” the amended independent claims 1, 10 and 19 remain anticipated by Lee.
The Applicant further argues on page 13 of the 03-26-26 Response that Lee does not teach a positive polarity pin having a first extension portion that intersects a second extension portion. The examiner respectfully disagrees.
As shown in Fig. 2 of Lee, the first extension portion 521a intersects the second extension portion 520a. Alternatively, the first extension portion 520a intersects the second extension portion 521a.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-8, 10-17, 19 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (previously-cited Pub. No. US 2015/0228706 A1 to Lee et al.).
Fig. 2 of Lee has been provided and Fig. 5 has been annotated to support the rejection below:
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Regarding independent claim 1, Lee teaches a chip-on-film 500, 600 (see Figs. 2, 12 and 5) comprising:
a flexible substrate 600 (para [0057] - “FIG. 1 is a view showing a connection relationship of a display panel 300, a chip on film 500, and a flexible printed circuit board (FPCB) 600 in a display device according to an example embodiment of the present invention. FIG. 2 is a cross-sectional view of the display device FIG. 1 taken along the line II-II.”);
a plurality of negative polarity pins N1, N2 or N1, N2, N3 (para [0087] - “[0087] However, the negative (-) signal is transmitted through the wire 521b, and is then transmitted to the wire 522b at a different layer through the first hole V1. The wire 522b is bent to pass over the pad 520a, and then couples with the pad 520b through the second hole V2 on the pad 520b. That is, the negative (-) signal is transmitted to the wire 522b at a different layer through the hole to be transmitted to the pad 520b.”) arranged in a row in a first direction D1 or D2 on the flexible substrate 600, and two adjacent negative polarity pins 521b, 521b of the plurality of negative polarity pins N1, N2 or N1, N2, N3 arranged in an interval (in the D2 direction); and
a positive polarity pin P1 (para [0086] - “Referring to FIG. 5, the positive (+) signal is directly transmitted to the pad 520a through the wire 521a.”) disposed on the flexible substrate 600, the positive polarity pin P1 being at least partially located between two adjacent negative polarity pins N1, N2 or N1, N2, N3 of the plurality of negative polarity pins N1, N2 or N1, N2, N3, the positive pin P1 comprising a first extension portion 521a or 520a and a second extension portion 520a or 521a, the first extension portion 521a or 520a intersecting the second extension portion 520a or 521a,
wherein a shape (L-shape) of the positive polarity pin P1 is different from a shape of each of the plurality of negative polarity pins N1, N2 (not L-shape) or N1, N2, N3 (not L-shape).
Regarding claim 2, Lee teaches the first extension portion 521a or 520a that extends in the first direction D1 or D2, the second extension portion 520a or 521a that extends in a second direction D2 or D1, and the first direction D1 or D2 is perpendicular to the second direction D2 or D1.
Regarding claim 3, Lee teaches two pin groups (521b and 520b)(521b and 520b) disposed along the first direction D1 or D2 at an interval, each of the two pin groups (521b and 520b)(521b and 520b) comprises multiple negative polarity pins 521b, 520b of the plurality of negative polarity pins N1, N2, and two adjacent (near) negative polarity pins 521b and 520b in each of the two pin groups (521b and 520b)(521b and 520b) are disposed along the first direction D1 at an interval,
wherein the positive polarity pin P1 is at least partially located between the two pin groups (521b and 520b)(521b and 520b) that are adjacent (near) to each other, and in the direction D1, a distance between two adjacent negative polarity pins N1, N2 is less than a distance between two pin groups (521b and 520b)(521b and 520b).
Regarding claim 4, Lee teaches both the first extension portion 521a and the second extension portion 520a are located between two adjacent negative polarity pins 521b, 521b of the plurality of negative polarity pins N1, N2.
Regarding claim 5, Lee teaches a middle portion of the first extension portion 521a that is connected with a middle portion of the second extension portion 520a.
Regarding claim 6, Lee teaches the first extension portion 521a or 520a that is connected to one terminal + of the second extension portion 520a or 521a.
Regarding claim 7, Lee teaches the plurality of negative polarity pins N1, N2 are arranged in a plurality of rows, and the negative polarity pins in two adjacent rows of the plurality of rows are arranged at an interval (along D2 direction) to form an accommodation area (space between N1 and N2), and
wherein the first extension portion 521a or 520a is located in the accommodation area, and the second extension portion 520a or 521a is located between two adjacent negative polarity pins of the plurality of negative polarity pins N1, N2.
Regarding claim 8, Lee teaches the number of positive polarity pins P1, P2 is two, the two positive polarity pins P1, P2 are disposed at an interval (along D2 direction), each of the positive polarity pins P1, P2 is located between two adjacent negative polarity pins N1, N3 of the plurality of negative polarity pins N1, N2, N3.
Regarding independent claim 10, Lee teaches a display device (see Figs. 1, 2 and 15) comprising:
a light-emitting substrate 100 (para [0058] - “According to an embodiment of the present invention, the display panel 300 may include a lower substrate 100 and an upper substrate 200. The display panel may be a liquid crystal display or an organic light emitting display (or organic light emitting diode (OLED) display).”); and
a chip-on-film 500, 600, one terminal of the chip-on-film 500, 600 is bonded to the light-emitting substrate 100, the chip-on-film 500, 600 comprising:
a flexible substrate 600 (para [0057] - “FIG. 1 is a view showing a connection relationship of a display panel 300, a chip on film 500, and a flexible printed circuit board (FPCB) 600 in a display device according to an example embodiment of the present invention. FIG. 2 is a cross-sectional view of the display device FIG. 1 taken along the line II-II.”);
a plurality of negative polarity pins N1, N2 or N1, N2, N3 (para [0087] - “[0087] However, the negative (-) signal is transmitted through the wire 521b, and is then transmitted to the wire 522b at a different layer through the first hole V1. The wire 522b is bent to pass over the pad 520a, and then couples with the pad 520b through the second hole V2 on the pad 520b. That is, the negative (-) signal is transmitted to the wire 522b at a different layer through the hole to be transmitted to the pad 520b.”) arranged in a row in a first direction D1 (along the lengths of the wire 521b and wire 522b) on the flexible substrate 600, and two adjacent negative polarity pins 521b, 521b of the plurality of negative polarity pins N1, N2 or N1, N2, N3 arranged in an interval (in the D2 direction); and
a positive polarity pin P1 (para [0086] - “Referring to FIG. 5, the positive (+) signal is directly transmitted to the pad 520a through the wire 521a.”) disposed on the flexible substrate 600, the positive polarity pin P1 being at least partially located between two adjacent negative polarity pins N1, N2 or N1, N2, N3 of the plurality of negative polarity pins N1, N2 or N1, N2, N3, the positive pin P1 comprising a first extension portion 521a or 520a and a second extension portion 520a or 521a, the first extension portion 521a or 520a intersecting the second extension portion 520a or 521a,
wherein a shape (L-shape) of the positive polarity pin P1 is different from a shape of each of the plurality of negative polarity pins N1, N2 (not L-shape) or N1, N2, N3 (not L-shape).
Regarding claim 11, Lee teaches the first extension portion 521a or 520a that extends in the first direction D1, the second extension portion 520a or 521a that extends in a second direction D2, and the first direction D1 is perpendicular to the second direction D2.
Regarding claim 12, Lee teaches the chip-on-film 500, 600 that further comprises two pin groups disposed along the first direction D1 at an interval, each of the two pin groups (521b and 520b)(521b and 520b) comprises multiple negative polarity pins 521b, 520b of the plurality of negative polarity pins N1, N2, and two adjacent (near) negative polarity pins 521b and 520b in each of the two pin groups (521b and 520b)(521b and 520b) are disposed along the first direction D1 at an interval,
wherein the positive polarity pin P1 is at least partially located between the two pin groups (521b and 520b)(521b and 520b) that are adjacent (near) to each other, and in the direction D1, a distance between two adjacent negative polarity pins N1, N2 is less than a distance between two pin groups (521b and 520b)(521b and 520b).
Regarding claim 13, Lee teaches both the first extension portion 521a and the second extension portion 520a are located between two adjacent negative polarity pins 521b, 521b of the plurality of negative polarity pins N1, N2.
Regarding claim 14, Lee teaches a middle portion of the first extension portion 521a that is connected with a middle portion of the second extension portion 520a.
Regarding claim 15, Lee teaches the first extension portion 521a or 520a that is connected to one terminal + of the second extension portion 520a or 521a.
Regarding claim 16, Lee teaches the plurality of negative polarity pins N1, N2 are arranged in a plurality of rows, and the negative polarity pins in two adjacent rows of the plurality of rows are arranged at an interval (along D2 direction) to form an accommodation area (space between N1 and N2), and
wherein the first extension portion 521a or 520a is located in the accommodation area, and the second extension portion 520a or 521a is located between two adjacent negative polarity pins of the plurality of negative polarity pins N1, N2.
Regarding claim 17, Lee teaches the number of positive polarity pins P1, P2 is two, the two positive polarity pins P1, P2 are disposed at an interval (along D2 direction), each of the positive polarity pins P1, P2 is located between two adjacent negative polarity pins N1, N3 of the plurality of negative polarity pins N1, N2, N3.
Regarding independent claim 19, Lee teaches a chip-on-film 500, 600 (see Figs. 2, 12 and 5) comprising:
a flexible substrate 600 (para [0057] - “FIG. 1 is a view showing a connection relationship of a display panel 300, a chip on film 500, and a flexible printed circuit board (FPCB) 600 in a display device according to an example embodiment of the present invention. FIG. 2 is a cross-sectional view of the display device FIG. 1 taken along the line II-II.”);
a plurality of negative polarity pins N1, N2 or N1, N2, N3 (para [0087] - “[0087] However, the negative (-) signal is transmitted through the wire 521b, and is then transmitted to the wire 522b at a different layer through the first hole V1. The wire 522b is bent to pass over the pad 520a, and then couples with the pad 520b through the second hole V2 on the pad 520b. That is, the negative (-) signal is transmitted to the wire 522b at a different layer through the hole to be transmitted to the pad 520b.”) arranged in a row in a first direction D1 (along the lengths of the wire 521b and wire 522b) on the flexible substrate 600, each of the plurality of negative polarity pins N1, N2 or N1, N2, N3 extending in a second direction D2;
a positive polarity pin P1 (para [0086] - “Referring to FIG. 5, the positive (+) signal is directly transmitted to the pad 520a through the wire 521a.”) disposed on the flexible substrate 600 and located between two adjacent (near) negative polarity pins N1, N2 or N1, N3 of the plurality of negative polarity pins N1, N2 or N1, N2, N3, wherein a shape (L-shape) of the positive polarity pin P1 is different from a shape (not L-shape) of each of the plurality of negative polarity pins N1, N2 or N1, N2, N3.
Regarding claim 20, Lee teaches the positive polarity pin P1 that comprises a first extension portion 521a or 520a that extending in the first direction D1 and a second extension portion 520a or 521a that extending in a second direction D2 perpendicular to the first direction D1, the first extension portion 521a or 520a intersecting the second extension portion 520a or 521a.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee.
Regarding claims 9 and 18, Lee teaches a general condition of a length of the first extension portion 520a that is shorter than a length of the second extension portion 521a, but does not specify their respective lengths being 0.5 mm to 5 mm and 0.7 mm to 1.5 mm.
According to Section 2144.05 of the MPEP, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F. 2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Here, Moon teaches the general condition of a length of the first extension portion 520a that is shorter than a length of the second extension portion 521a. Unless the Applicant can show that the claimed specific condition of their respective lengths being 0.5 mm to 5 mm and 0.7 mm to 1.5 mm produces unexpected results that are different in kind and not different in degree over said general condition as taught by Lee, claim 9 (or claim 18) would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, because it would not be inventive to discover the optimum or workable ranges by routine experimentation. The burden shifts to the Applicant to show that the claimed range provides unexpected result that is difference in kind and not difference in degree. See In re Aller, 220 F. 2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Moreover, in Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Court held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device, and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (see MPEP 2144.04).
Since the only difference between the claimed chip-on-film and the chip-on-film taught by Lee is a relative dimension of the first extension portion ranging from 0.5 mm to 5 mm, and a length of the second extension portion ranging from 0.7 mm to 1.5 mm, the Court would be more likely than not hold that the claimed chip-on-film is not patentably distinct from the chip-on-film aught by Lee. Also, before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art modify the chip-on-film such that the first extension portion ranging from 0.5 mm to 5 mm, and a length of the second extension portion ranging from 0.7 mm to 1.5 mm with a reasonable expectation of providing a chip-on-film that is small as possible as the one of ordinary skill in the semiconductor art is incentivized to make adjustments to size to fit an intended purpose of making device smaller as market forces demand that the device scale down with Moore's Law.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408)918-7554. The examiner can normally be reached 8:30 A.M. to 7 P.M.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano, can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL JUNG/Primary Examiner, Art Unit 2817 30 April 2026
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