DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/13/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “a second semiconductor structure including gate electrodes including a first gate electrode and a second gate electrode, spaced apart from each other and stacked on the second semiconductor structure in a first direction” (emphasis added) in lines 7-9 of the claim, which is indefinite and unclear, because it is unclear how the gate electrodes can be both part of the second semiconductor structure and be stacked on the second semiconductor structure at the same time. In other words, it is unclear how a component (i.e., gate electrodes) of the second semiconductor structure can be stacked on top of itself.
Note the dependent claims 2-12 necessarily inherit the indefiniteness of the claims on which they depend.
Allowable Subject Matter
Claims 1-12 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Regarding independent claim 1, Figures 4 and 9M of Jung et al. (US 2016/0343725 A1, hereinafter “Jung”) disclose a semiconductor device comprising:
a first semiconductor structure including a substrate 105 (“substrate”- ¶0046, specifically the portion of 105 in region P), circuit elements 200, 210 (“transistors”- ¶0053) on the substrate 105, a lower interconnection structure 240 (“contact plug”- ¶0058) including a first lower interconnection structure 241 and a second lower interconnection structure 242 electrically connected to the circuit elements 200, 210, and a peripheral region insulating layer 153 (“insulating layer”- ¶0059) on the circuit elements 200, 210; and
a second semiconductor structure including gate electrodes 130 (“gate electrode layers”- ¶0039) including a first gate electrode 131 and a second gate electrode 132, spaced apart from each other and stacked on each other in a first direction, interlayer insulating layers 140 (“insulating layers”- ¶0046) alternately stacked with the gate electrodes 130, contact plugs 170 (“contact plugs”- ¶0038) including a first contact plug 171 and a second contact plug 172 passing through the gate electrodes 130, and contact plug insulating layers 162 (“blocking layer”- ¶0047) alternately disposed with the interlayer insulating layers 140, the contact plug insulating layers 162 extending around the contact plugs 170.
Jung does not expressly disclose the first lower interconnection structure and the second lower interconnection structure having different electric potentials, the first gate electrode and the second gate electrode having different electric potentials, the contact plugs extending into the first semiconductor structure in the first direction, the first contact plug and the second contact plug having different electric potentials and wherein the second semiconductor structure further includes a first capacitor structure including the first gate electrode, at least one of the contact plug insulating layers, and the second contact plug, or including the second gate electrode, at least one of the contact plug insulating layers, and the first contact plug, a second capacitor structure including the first gate electrode, at least one of the interlayer insulating layers, and the second gate electrode, and the first semiconductor structure further includes a third capacitor structure including the first lower interconnection structure, the peripheral region insulating layer, and the second lower interconnection structure.
Thus, regarding independent claim 1 (which claims 2-12 depend from), the prior art of record including Jung, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “the first lower interconnection structure and the second lower interconnection structure having different electric potentials”, “the first gate electrode and the second gate electrode having different electric potentials”, “the contact plugs… extending into the first semiconductor structure in the first direction”, “the first contact plug and the second contact plug having different electric potentials”, “wherein the second semiconductor structure further includes: a first capacitor structure including the first gate electrode, at least one of the contact plug insulating layers, and the second contact plug, or including the second gate electrode, at least one of the contact plug insulating layers, and the first contact plug; and a second capacitor structure including the first gate electrode, at least one of the interlayer insulating layers, and the second gate electrode” and “the first semiconductor structure further includes: a third capacitor structure including the first lower interconnection structure, the peripheral region insulating layer, and the second lower interconnection structure”.
Claims 13-20 are allowed.
Regarding independent claim 13, Figures 4 and 9M of Jung disclose a semiconductor device comprising:
a first semiconductor structure including circuit elements 200, 210 (“transistors”- ¶0053) disposed on a first substrate 105 (“substrate”- ¶0046, specifically the portion of 105 in region P), a lower interconnection structure 240 (“contact plug”- ¶0058) electrically connected to the circuit elements 200, 210, and a peripheral region insulating layer 153 (“insulating layer”- ¶0059) on the circuit elements 200, 210; and
a second semiconductor structure including a second substrate 105 (“substrate”- ¶0046, specifically the portion of 105 in region C), a first stack structure including a first gate electrode 131 (“gate electrode layers”- ¶0038) and a second gate electrode 132 (“gate electrode layers”- ¶0038) spaced apart from each other and stacked on the second substrate 105 in a first direction, interlayer insulating layers 140 (“insulating layers”- ¶0046) alternately stacked with the first and second gate electrodes 131, 132, contact plugs 170 (“contact plugs”- ¶0038) including a first contact plug 171 and a second contact plug 172 passing through the first and second gate electrodes 131, 132, and contact plug insulating layers 162 (“blocking layer”- ¶0047) alternately disposed with the interlayer insulating layers 140, the contact plug insulating layers 162 extending around the contact plugs 170.
Jung does not expressly disclose the second substrate on the first substrate, the first gate electrode and the second gate electrode having different electric potentials, the first contact plug and the second contact plug having different electric potentials and wherein the second semiconductor structure further includes a first capacitor structure including the first gate electrode, at least one of the contact plug insulating layers, and the second contact plug, or the second gate electrode, at least one of the contact plug insulating layers, and the first contact plug.
Thus, regarding independent claim 13, the claim is allowed, because the prior art of record including Jung, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “a second substrate on the first substrate”, “the first gate electrode and the second gate electrode having different electric potentials”, “the first contact plug and the second contact plug having different electric potentials” and “wherein the second semiconductor structure further includes a first capacitor structure including the first gate electrode, at least one of the contact plug insulating layers, and the second contact plug, or the second gate electrode, at least one of the contact plug insulating layers, and the first contact plug”.
Claims 14-18 are allowed as being dependent on allowed claim 13.
Regarding independent claim 19, Figures 1, 4 and 9M of Jung disclose an electronic system comprising:
a semiconductor device including a first semiconductor structure including circuit elements 200, 210 (“transistors”- ¶0053) on a first substrate 105 (“substrate”- ¶0046, specifically the portion of 105 in region P), a lower interconnection structure 240 (“contact plug”- ¶0058) electrically connected to the circuit elements 200, 210, and a peripheral region insulating layer 153 (“insulating layer”- ¶0059) on the circuit elements 200, 210; and a second semiconductor structure including a second substrate 105 (“substrate”- ¶0046, specifically the portion of 105 in region C), a first stack structure including a first gate electrode 131 (“gate electrode layers”- ¶0038) and a second gate electrode 132 (“gate electrode layers”- ¶0038) spaced apart from each other and stacked on the second substrate 105 in a first direction, interlayer insulating layers 140 (“insulating layers”- ¶0046) alternately stacked with first and second gate electrodes 131, 132, contact plugs 170 (“contact plugs”- ¶0038) including a first contact plug 171 and a second contact plug 172 passing through the first and second gate electrodes 131, 132, contact plug insulating layers 162 (“blocking layer”- ¶0047) alternately disposed with the interlayer insulating layers 140, the contact plug insulating layers 162 extending around the contact plugs 170, and an input/output pad (i.e., the input/output connections of driving circuit 30- ¶¶0028, 0053) electrically connected to the circuit elements 200, 210; and
a controller 50 (“control circuit”- ¶0025) electrically connected to the semiconductor device through the input/output pad, wherein the controller is configured to control the semiconductor device (¶0028).
Jung does not expressly disclose the second substrate on the first substrate, the first gate electrode and the second gate electrode having different electric potentials, the first contact plug and the second contact plug having different electric potentials and wherein the second semiconductor structure further includes a first capacitor structure including the first gate electrode, at least one of the contact plug insulating layers, and the second contact plug, or the second gate electrode, at least one of the contact plug insulating layers, and the first contact plug.
Thus, regarding independent claim 19, the claim is allowed, because the prior art of record including Jung, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “a second substrate on the first substrate”, “the first gate electrode and the second gate electrode having different electric potentials”, “the first contact plug and the second contact plug having different electric potentials” and “wherein the second semiconductor structure further includes a first capacitor structure including the first gate electrode, at least one of the contact plug insulating layers, and the second contact plug, or the second gate electrode, at least one of the contact plug insulating layers, and the first contact plug”.
Claim 20 is allowed as being dependent on allowed claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Park (US 2016/0211363 A1), which discloses a semiconductor device comprising a capacitor structure including a gate electrode, a contact plug insulating layer and a contact plug.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm.
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/JAY C CHANG/ Primary Examiner, Art Unit 2817