DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 7-13, filed 03/03/2026, with respect to the rejection(s) of claims 1-20 under 102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Challa et al. (US 20050167742 A1).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 1 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Challa et al. (US 20050167742 A1).
Regarding claim 1, Challa Fig. 2A discloses a semiconductor device, comprising:
a semiconductor region (206) of a first conductivity type (n) having a main surface;
a capacitor region (204) of a second conductivity type (p) formed in a surface layer portion of the main surface;
at least one trench structure (202), including:
a trench (202) formed in the main surface to penetrate the capacitor region (201),
an insulating film (226) covering a wall surface of the trench (202), and
a region isolation structure (220), including:
an isolation trench (220) formed in the main surface,
an isolation insulating film (222) covering a wall surface of the isolation trench (220), and
an isolation electrode (224) embedded in the isolation trench (220),
the isolation electrode (224) is longer than the upper electrode (210) in a depth direction of the semiconductor device (200), in a cross-sectional view of the semiconductor device (200). ([0112], Fig. 2A)
Challa Fig. 2A does not show:
embedded electrodes embedded in the trench so as to form capacitive coupling with the capacitor region through the insulating film; and
wherein the embedded electrodes have a multi-electrode structure including:
an upper electrode embedded in the trench at an opening side with respect to a bottom portion of the capacitor region so as to form the capacitive coupling with the capacitor region through the insulating film, the upper electrode being disposed between portions of the insulating film, and
a lower electrode embedded in the trench at a bottom wall side with respect to the bottom portion of the capacitor region so as to face the semiconductor region through the insulating film, the lower electrode being disposed between portions of the insulating film;
However, Challa Fig. 3B shows:
embedded electrodes (310/311) embedded in the trench (302) so as to form capacitive coupling with the capacitor region through the insulating film; and
wherein the embedded electrodes (310/311) have a multi-electrode structure including:
an upper electrode (310) embedded in the trench (302) at an opening side with respect to a bottom portion of the capacitor region (not labeled in Fig. 3A but similar region labeled 204 in Fig. 2A) so as to form the capacitive coupling with the capacitor region through the insulating film (not labeled but in Fig. 3A but similar region labeled 222 in Fig. 2A), the upper electrode (310) being disposed between portions of the insulating film (not labeled but in Fig. 3A but similar region labeled 222 in Fig. 2A), and
a lower electrode (311) embedded in the trench (302) at a bottom wall side with respect to the bottom portion of the capacitor region (not labeled in Fig. 3A but similar region labeled 204 in Fig. 2A) so as to face the semiconductor region (306 in Fig. 3A) through the insulating film (not labeled but in Fig. 3A but similar region labeled 222 in Fig. 2A), the lower electrode (311) being disposed between portions of the insulating film (not labeled but in Fig. 3A but similar region labeled 222 in Fig. 2A); ([0116], Fig. 3B)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Challa’s Fig. 2A and 3B to arrive at the claimed invention in order to improve “the voltage performance of the transistor while maintaining a low drain-to-source on-resistance.” (Challa, [0021])
Regarding claim 7, Challa discloses the semiconductor device of Claim 1, wherein the at least one trench structure (202) includes a plurality of trench structures (202) formed at intervals in the main surface. (Fig. 2A)
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Challa et al. (US 20050167742 A1) as applied to claim 1 above, and further in view of Okuda et al. (US 20160133742 A1).
Regrading claim 4, Challa discloses the semiconductor device of Claim 1. Challa does not disclose wherein the insulating film includes an upper insulating film covering the wall surface of the trench at the opening side, and a lower insulating film covering the wall surface of the trench at the bottom wall side with a thickness larger than a thickness of the upper insulating film, wherein the upper electrode is disposed between portions of the upper insulating film, and wherein the lower electrode is disposed between portions of the lower insulating film.
However, Okuda discloses:
the insulating film (20) includes an upper insulating film (22) covering the wall surface of the trench (14) at the opening side, and a lower insulating film (21) covering the wall surface of the trench (14) at the bottom wall side with a thickness larger than a thickness of the upper insulating film ([0078], Fig. 4), wherein
the upper electrode (30) is disposed between portions of the upper insulating film (22), ([0078], Fig. 4), and wherein
the lower electrode (26) is disposed between portions of the lower insulating film (21). ([0078], Fig. 4)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Challa and Okuda to arrive at the claimed invention in order to “provide a semiconductor device that is capable of avoiding a complex structure and that is capable of lowering resistance” (Okuda, [0005])
Regarding claim 5, Challa discloses the semiconductor device of Claim 1. Challa does not disclose wherein the at least one trench structure includes an intermediate insulating layer disposed between the upper electrode and the lower electrode.
However, Okuda discloses:
the at least one trench (14) structure includes an intermediate insulating layer (24) disposed between the upper electrode (30) and the lower electrode (26). ([0076], Fig. 4)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Challa and Okuda to arrive at the claimed invention in order to “improve the reliability of the trench gate structure and, consequently, to improve the reliability of the semiconductor device.” (Okuda, [0032])
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Okuda et al. (US 20160133742 A1) as applied to claim 5 above, and further in view of Aoki et al. (US 20080012610 A1).
Regarding claim 6, Okuda discloses the semiconductor device of claim 5. Okuda does not disclose wherein the at least one trench structure includes an intermediate insulating layer disposed between the upper electrode and the lower electrode.
However, Aoki discloses:
wherein a first electric potential (ground potential) is applied to the capacitor region (in 2), and wherein a second electric potential (electric power input) different from the first electric potential (ground potential) is applied to the upper electrode (in 19). ([0104])
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Challa and Aoki to arrive at the claimed invention in order to “ make the switching circuits compact.” (Aoki, [0005])
Claims 8-11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Challa et al. (US 20050167742 A1) as applied to claim 1 above, and further in view of Aoki et al. (US 20080012610 A1).
Regarding claim 8, Challa discloses the semiconductor device of Claim 1. Challa does not disclose further comprising:
a high-concentration capacitor region of the second conductivity type having an impurity concentration higher than an impurity concentration of the capacitor region and being formed in a surface layer portion of the capacitor region, wherein the trench is formed in the main surface so as to penetrate the capacitor region and the high-concentration capacitor region, and wherein the embedded electrodes form the capacitive coupling with the capacitor region and the high-concentration capacitor region through the insulating film.
However, Aoki discloses:
a high-concentration capacitor region (132) of the second conductivity type (P) having an impurity concentration higher than an impurity concentration of the capacitor region (138) and being formed in a surface layer portion (top) of the capacitor region (138), ([0221], Fig. 16A) wherein
the trench (36+34) is formed in the main surface (top) so as to penetrate the capacitor region (138) and the high-concentration capacitor region (132), and wherein
the embedded electrodes (36) form the capacitive coupling (per [0221]) with the capacitor region (138) and the high-concentration capacitor region (132) through the insulating film (34). (Fig. 16A)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Challa and Aoki to arrive at the claimed invention in order to “ make the switching circuits compact.” (Aoki, [0005])
Regarding claim 9, Challa discloses the semiconductor device of Claim 1. Challa does not disclose further comprising:
a first wiring electrically connected to the at least one trench structure on the main surface; and a second wiring electrically connected to the capacitor region on the main surface.
However, Aoki discloses:
a first wiring (annotated below) electrically connected to the at least one trench structure (36+34) on the main surface (top); (Fig. 16A) and
a second wiring (annotated below) electrically connected to the capacitor region (138) on the main surface (top). (Fig. 16A)
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It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Challa and Aoki to arrive at the claimed invention in order to “ make the switching circuits compact.” (Aoki, [0005])
Regarding claim 10, Challa discloses the semiconductor device of claim 1. Challa does not disclose further comprising:
a capacitive device region provided on the main surface
wherein the capacitor region is formed on the capacitive device region, and
wherein the at least one trench structure is formed on the capacitive device region.
However, Aoki discloses:
a capacitive device region (annotated above) provided on the main surface; (Fig. 16A) and
wherein the capacitor region (132) is formed on the capacitive device region (annotated below)
the at least one trench structure (36+34) is formed on the capacitive device region (annotated below). (Fig. 16A)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Challa and Aoki to arrive at the claimed invention in order to “ make the switching circuits compact.” (Aoki, [0005])
Regarding claim 11, Challa discloses the semiconductor device of claim 1. Challa does not disclose further comprising:
a transistor region provided on the main surface; and
a capacitive device region provided on the main surface,
wherein the capacitor region is formed on the capacitive device region, and
wherein the at least one trench structure is formed on the capacitive device region.
However, Aoki discloses:
a transistor region (element region) provided on the main surface (top); (Fig. 16A) and
a capacitive device region (annotated above) provided on the main surface (top), wherein
the capacitor region (132) is formed on the capacitive device region (annotated above), and wherein the at least one trench structure (36+34) is formed on the capacitive device region (annotated above). (Fig. 16A)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Challa and Aoki to arrive at the claimed invention in order to “ make the switching circuits compact.” (Aoki, [0005])
Regarding claim 13, Aoki discloses the semiconductor device of claim 11, wherein the transistor region (element region) includes:
a body region (76) of the second conductivity type (P) formed in the surface layer portion (top) of the main surface (top); ([0204], Fig. 16A) and
at least one trench gate structure (64+62) including a gate trench (64+62) formed in the main surface (top) to penetrate the body region (76), a gate insulating film (62) covering a wall surface of the gate trench (64), and gate electrodes (64) embedded in the gate trench (64+62) and disposed between portions of the gate insulating film (62). ([0205], Fig. 16A)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Challa and Aoki to arrive at the claimed invention in order to “ make the switching circuits compact.” (Aoki, [0005])
Claims 12 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Aoki et al. (US 20080012610 A1) as applied to claim 11 above, and further in view of Okuda et al. (US 20160122742 A1).
Regarding claim 12, Aoki discloses the semiconductor device of claim 11. Aoki does not disclose wherein the capacitive device region has a plan-view area smaller than a plan-view area of the transistor region.
However, Okuda discloses:
the capacitive device region (4) has a plan-view area smaller than a plan-view area of the transistor region (2). (Fig. 1)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Aoki and Okuda for the capacitive device region has a plan-view area smaller than a plan-view area of the transistor region in order to “is to provide a semiconductor device that is capable of avoiding a complex structure.” (Okuda, [0005])
Regrading claim 14, Aoki discloses the semiconductor device of claim 13. Aoki does not disclose wherein the gate electrodes have a multi-electrode structure including a gate upper electrode embedded in the gate trench at an opening side and disposed between portions of the gate insulating film, and a gate lower electrode embedded in the gate trench at a bottom wall side and disposed between portions of the gate insulating film.
However, Okuda discloses:
the gate electrodes (25) have a multi-electrode structure including a gate upper electrode (30) embedded in the gate trench (14) at an opening side and disposed between portions of the gate insulating film (20), and a gate lower electrode (26) embedded in the gate trench (14) at a bottom wall side and disposed between portions of the gate insulating film (20). ([0076], Fig. 2-4)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Aoki and Okuda for the gate electrodes have a multi-electrode structure including a gate upper electrode embedded in the gate trench at an opening side and disposed between portions of the gate insulating film, and a gate lower electrode embedded in the gate trench at a bottom wall side and disposed between portions of the gate insulating film in order to “provide a semiconductor device that is capable of avoiding a complex structure and that is capable of lowering resistance” (Okuda, [0005])
Regarding claim 15, Okuda discloses the semiconductor device of claim 14, wherein the gate upper electrode (30) is embedded in the gate trench (14) at the opening side with respect to a bottom portion of the body region (15) so as to face the body region (15) through the gate insulating film (20), and wherein
the gate lower electrode (26) is embedded in the gate trench (14) at the bottom wall side with respect to the bottom portion of the body region (15) so as to face the semiconductor region (12+16) through the gate insulating film (20). ([0071], Fig. 20)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Okuda for similar reasons mentioned beforehand.
Regarding claim 16, Okuda discloses the semiconductor device of claim 14, wherein the gate insulating film (20) includes a gate upper insulating film (22) covering the wall surface of the gate trench (14) at the opening side, and a gate lower insulating film (21) covering the wall surface of the gate trench (14) at the bottom wall side with a thickness larger than a thickness of the gate upper insulating film (22), ([0078], Fig. 4) wherein
the gate upper electrode (30) is embedded in the gate trench (14) at the opening side and disposed between portions of the gate upper insulating film (22), ([0078], Fig. 4) and wherein
the gate lower electrode (26) is embedded in the gate trench (14) at the bottom wall side and disposed between portions of the gate lower insulating film (21). ([0078], Fig. 4)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Okuda for similar reasons mentioned beforehand.
Regarding claim 17, Okuda discloses the semiconductor device of claim 14, wherein the at least one trench gate structure (19) includes a gate intermediate insulating film (24) disposed between the gate upper electrode (30) and the gate lower electrode (76). ([0076], Fig. 4)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Okuda for similar reasons mentioned beforehand.
Regarding claim 18, Aoki discloses the semiconductor device of claim 13. Aoki does not disclose further comprising:
The semiconductor device of Claim 13, further comprising: a source region of the first conductivity type formed in a region provided along the at least one trench gate structure at the surface layer portion of the body region.
However, Okuda discloses:
a source region (17) of the first conductivity type (N) formed in a region provided along the at least one trench gate structure (19) at the surface layer portion of the body region (15). ([0071], Fig. 2-4)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Okuda for similar reasons mentioned beforehand.
Regarding claim 19, Aoki discloses the semiconductor device of claim 13. Aoki does not disclose
further comprising: a high-concentration body region of the second conductivity type having an impurity concentration higher than an impurity concentration of the body region and being formed in a region provided along the at least one trench gate structure at the surface layer portion of the body region.
However, Okuda discloses:
a high-concentration body region (18) of the second conductivity type (P) having an impurity concentration higher than an impurity concentration of the body region (15) and being formed in a region provided along the at least one trench gate structure (19) at the surface layer portion (top) of the body region (15). ([0075], Fig. 2)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Okuda for similar reasons mentioned beforehand.
Regarding claim 20, Aoki discloses the semiconductor device of claim 13. Aoki does not disclose
further comprising: The semiconductor device of Claim 13, wherein the at least one trench gate structure includes a plurality of trench gate structures formed at intervals in the main surface.
However, Okuda discloses:
the at least one trench gate structure (19) includes a plurality of trench gate structures (see Fig. 2) formed at intervals in the main surface. (Fig. 2-3)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Okuda for similar reasons mentioned beforehand.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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