DETAILED ACTION
Examiner’s Note
The prior arts cited in PTO-892 but not used in the current rejection are related to the claimed novelty and can also be used to reject the claims 1-18.
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Election/Restrictions
Applicant’s election without traverse of species A/fig. 1-6, reflected in claims 1-18 in the reply filed on 01/09/2026 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5 and 7-18 are rejected under 35 U.S.C. 103 as being unpatentable over Hayashi (WO 2020031553 A1, Hayashi‘553) in view of Kimura et al. (US 20180269799 A1, hereinafter Kimura‘799).
Regarding independent claim 1, Hayashi‘553 teaches, “A semiconductor device (100, fig. 1-3, related description) comprising: a first MOSFET (350, fig. 2); and a first IGBT (page 9, ‘an IGBT connected in parallel to the MOSFET 350), wherein a drain (350a) of the first MOSFET (350) and ((a collector of)) the first IGBT are electrically connected to each other, a source (350b) of the first MOSFET (350) and ((an emitter of)) the first IGBT are electrically connected to each other, and an element withstand voltage of the first MOSFET is larger than an element withstand voltage of the first IGBT (page 9)”.
But Hayashi‘553 may be silent upon the provision of wherein
the drain of the first MOSFET is electrically connected to a collector of the first IGBT and the source of the first MOSFET is electrically connected to an emitter of the first IGBT.
However, Kimura‘799 teaches a similar inverter circuit (fig. 1), the drain of a MOSFET (22) is electrically connected to a collector of a IGBT (23) and the source of the MOSFET (22) is electrically connected to an emitter of the IGBT (23).
Hayashi‘553 and Kimura‘799 are analogous art because they both are directed to power inverter circuit and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hayashi‘553 with the features of Kimura‘799 because they are from the same field of endeavor.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Hayashi‘553 and Kimura‘799 to connect the source and drain of the MOSFET to the emitter and the collector of the IGBT respectively according to the teachings of Kimura‘799 as this is convention for the similar circuit in the semiconductor field.
Regarding claim 2, Hayashi‘553 modified with Kimura‘799 further teaches, “The semiconductor device according to claim 1, wherein the first MOSFET comprises SiC, and the first IGBT comprises Si” (¶ 0045, Kimura‘799).
Regarding claim 3, Hayashi‘553 modified with Kimura‘799 further teaches, “The semiconductor device according to claim 1, further comprising: a first power terminal electrically connected to the drain of the first MOSFET (22) and the collector of the first IGBT (23); and a second power terminal electrically connected to the source of the first MOSFET (22) and the emitter of the first IGBT (23), wherein an inductance of a first conduction path from the drain of the first MOSFET (22) to the first power terminal is smaller than an inductance of a second conduction path from the collector of the first IGBT (23) to the first power terminal (fig. 11; ¶ [0090], Kimura‘799)”.
Regarding claim 4, Hayashi‘553 modified with Kimura‘799 further teaches, “The semiconductor device according to claim 3, further comprising a first Schottky barrier diode electrically connected in parallel to the first MOSFET and the first IGBT (fig. 7; ¶ [0070], Kimura‘799)”.
Regarding claim 5, Hayashi‘553 modified with Kimura‘799 further teaches, “The semiconductor device according to claim 4, wherein the first Schottky barrier diode comprises SiC (fig. 7; ¶ [0070], Kimura‘799)”.
Regarding claim 7, Hayashi‘553 modified with Kimura‘799 further teaches, “The semiconductor device according to claim 3, further comprising: a second MOSFET (321/350, fig. 1-2, Hayashi‘553); and a second IGBT (321/page 9, ‘an IGBT connected in parallel to the MOSFET 350, Hayashi‘553), wherein a drain of the second MOSFET and a collector of the second IGBT are electrically connected to each other, a source of the second MOSFET and an emitter of the second IGBT are electrically connected to each other, and an element withstand voltage of the second MOSFET is larger than an element withstand voltage of the second IGBT fig. 1, Kimura‘799)”.
Regarding claim 8, Hayashi‘553 modified with Kimura‘799 further teaches, “The semiconductor device according to claim 7, wherein the second MOSFET comprises SiC, and the second IGBT comprises Si” (¶ 0045, Kimura‘799).
Regarding claim 9, Hayashi‘553 modified with Kimura‘799 further teaches, “The semiconductor device according to claim 7, further comprising a third power terminal electrically connected to the source of the second MOSFET and the emitter of the second IGBT, wherein the second power terminal is electrically connected to the drain of the second MOSFET and the collector of the second IGBT, and an inductance of a fourth conduction path from the source of the second MOSFET to the first power terminal is smaller than an inductance of a fifth conduction path from the emitter of the second IGBT to the first power terminal (fig. 24, ¶ [0117], Kimura‘799)”.
Regarding claim 10, Hayashi‘553 modified with Kimura‘799 further teaches, “The semiconductor device according to claim 9, further comprising a second Schottky barrier diode electrically connected in parallel to the second MOSFET and the second IGBT” (fig. 7; ¶ [0070], Kimura‘799).
Regarding claim 11, Hayashi‘553 modified with Kimura‘799 further teaches, “The semiconductor device according to claim 10, wherein the first Schottky barrier diode comprises SiC (fig. 7; ¶ [0070], Kimura‘799)”.
Regarding claim 12, Hayashi‘553 modified with Kimura‘799 further teaches, “The semiconductor device according to claim 10, wherein a sixth conduction path from the second Schottky barrier diode to the first power terminal is longer than the fourth conduction path and shorter than the fifth conduction path (fig. 7; ¶ [0070], Kimura‘799)”.
Regarding claim 13, Hayashi‘553 modified with Kimura‘799 further teaches, “The semiconductor device according to claim 9, further comprising: a first conductor (55H, fig. 23, 25, 26; ¶ [0120 - ¶ [0122]], Kimura‘799) to which the first power terminal is connected; a second conductor (55L) to which the second power terminal is connected; and a third conductor (553) to which the third power terminal is connected, wherein the first conductor includes a first pad portion (fig. 26) electrically connected to the drain of the first MOSFET (22, fig. 23, 25-26, Kimura‘799) and the collector of the first IGBT, the second conductor includes a second pad portion electrically connected to the source of the first MOSFET (22, fig. 23, 25-26, Kimura‘799), the emitter of the first IGBT (23, fig. 23, 25-26, Kimura‘799), the drain of the second MOSFET (22, fig. 23, 25-26, Kimura‘799), and the collector of the second IGBT, and the third conductor includes a third pad portion electrically connected to the source of the second MOSFET (22, fig. 23, 25-26, Kimura‘799) and the emitter of the second IGBT (23, fig. 23, 25-26, Kimura‘799)”.
Regarding claim 14, Hayashi‘553 modified with Kimura‘799 further teaches, “The semiconductor device according to claim 13, wherein each of the first MOSFET (22, fig. 23, 25-26) and the second MOSFET (22) has a vertical structure (fig. 26) in which the drain and the source are spaced apart from each other in a thickness direction thereof, and each of the first IGBT (23) and the second IGBT (23) has a vertical structure in which the collector and the emitter are spaced apart from each other in a thickness direction thereof”.
Regarding claim 15, Hayashi‘553 modified with Kimura‘799 further teaches, “The semiconductor device according to claim 14, further comprising: a first connecting member that electrically connects the source of the first MOSFET (22, fig. 23, 25-26, Kimura‘799) and the second pad portion; and a second connecting member that electrically connects the emitter of the first IGBT (23, fig. 23, 25-26, Kimura‘799) and the second pad portion, wherein the drain of the first MOSFET (22, fig. 23, 25-26, Kimura‘799) and the collector of the first IGBT (23, fig. 23, 25-26, Kimura‘799) are electrically bonded to the first pad portion”.
Regarding claim 16, Hayashi‘553 modified with Kimura‘799 further teaches, “The semiconductor device according to claim 15, further comprising: a third connecting member that electrically connects the source of the second MOSFET (22, fig. 23, 25-26, Kimura‘799) and the third pad portion; and a fourth connecting member that electrically connects the emitter of the second IGBT (23, fig. 23, 25-26, Kimura‘799) and the third pad portion, wherein the drain of the second MOSFET and the collector of the second IGBT (23, fig. 23, 25-26, Kimura‘799) are electrically bonded to the second pad portion”.
Regarding claim 17, Hayashi‘553 modified with Kimura‘799 further teaches, “The 17. The semiconductor device according to claim 16, wherein the first MOSFET (22, fig. 23, 25-26, Kimura‘799) and the first IGBT (23, fig. 23, 25-26, Kimura‘799) are arranged in a first arrangement direction intersecting with a thickness direction of the first pad portion, the second MOSFET (22, fig. 23, 25-26, Kimura‘799) and the second IGBT (23, fig. 23, 25-26, Kimura‘799) are arranged in a second arrangement direction intersecting with a thickness direction of the second pad portion, and the first arrangement direction and the second arrangement direction are the same direction”.
Regarding claim 18, Hayashi‘553 modified with Kimura‘799 further teaches, “The 18. The semiconductor device according to claim 17, wherein the first power terminal and the third power terminal are located opposite from the first IGBT (23, fig. 23, 25-26, Kimura‘799) with respect to the first MOSFET (22, fig. 23, 25-26, Kimura‘799) in the first arrangement direction, and are located opposite from the second IGBT (23, fig. 23, 25-26, Kimura‘799) with respect to the second MOSFET (22, fig. 23, 25-26, Kimura‘799) in the second arrangement direction”.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hayashi‘553 modified with Kimura‘799 as applied to claim 4 as above, and further in view of Shimizu et al. (US 20170302182 A1, hereinafter Shimizu‘182).
Regarding claim 6, Hayashi‘553 modified with Kimura‘799 teaches all the limitations described in claim 4.
But Hayashi‘553 modified with Kimura‘799 is silent upon the provision of wherein a third conduction path from the first Schottky barrier diode to the first power terminal is longer than the first conduction path and shorter than the second conduction path.
However, Shimizu‘182 teaches a similar device (fig. 13, 15; ¶ [0079] - ¶ [0081]) wherein a third conduction path from the first Schottky barrier diode to the first power terminal is longer than the first conduction path and shorter than the second conduction path.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Hayashi‘553 modified with Kimura‘799 and Shimizu‘182 to configure the Schottky barrier diode to have a longer conduction path according to the teachings of Shimizu‘182 with a motivation of reducing the surface area of the MOSFET element and thus, reducing the manufacturing cost. See Shimizu‘182, ¶ [0006] - ¶ [0011].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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