DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 01/21/2026 is acknowledged.
Response to Amendment
The response filed 01/21/2026 is accepted, in which, Applicant cancels claims 6-16 and newly adds claims 21-31. Claims 1, 17, and 21 are independent. Claims 1-5 and 17-31 await an action on the merits as follows.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 25 and 27 are rejected for indefiniteness.
Regarding claims 25 and 27, the claims state inter alia, "… remains on only …"
The claims are indefinite because it is well known in the art that "on" refers to two elements in direct contact and/or two elements in indirect contact. Any element that is in indirect contact with any other portion of the invention as well as the identified component, X, in the statement, "… remains on only X" is indefinite because it is impossible for the identified component to only be on one element in the invention. Once in direct contact with any portion of the device, that component is indirect contact will all the elements of the device.
Therefore, it is impossible for "the electron barrier layer remains on only the metal-oxide channel layer in the recess" as claimed in claim 25, and impossible for "the oxide insertion layer remains on only the electron barrier layer" as claimed in claim 27.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 17-24, 26, and 28-31 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20220285519 A1), and further in view of Murray (US 20230029955 A1).
Regarding claim 1, Huang teaches a non-volatile memory cell structure (200H, Fig 2H), comprising:
a bottom gate electrode (104);
a memory layer (108) above (shown above) the bottom gate electrode (104);
a metal-oxide channel layer (110) above (shown above) the memory layer (108); and
a plurality of source/drain regions (SD: layers 112/114/118) in (shown in) a dielectric layer (120) above (shown above) the metal-oxide channel layer (110),
wherein a source/drain region (SD) of the plurality of source/drain regions (SD) comprises:
an electron barrier layer (114) on (shown on) the metal-oxide channel layer (110);
an oxide insertion layer (112) on (shown on) the electron barrier layer (114); and
a source/drain electrode (118).
Huang fails to explicitly teach a metal glue layer on the oxide insertion layer; and a source/drain electrode on the metal glue layer.
However, Murray teaches a metal glue layer (1602, Fig 16) on (shown on) the oxide insertion layer; and
a source/drain electrode on (shown on) the metal glue layer (1602).
Huang and Murray are considered analogous to the claimed invention because both are from the same field of endeavor of non-volatile memory cell structure devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Huang with the features of Murray to create a metal glue layer on the oxide insertion layer; and a source/drain electrode on the metal glue layer because the glue layer may assist in adhering the source electrode material and the drain electrode material to the semiconducting material (Murray, [0096]).
Regarding claim 2, the combination of Huang and Murray discloses the device of claim 1. Huang goes on to teach wherein the oxide insertion layer (112, Fig 2H) comprises an oxide-semiconductor material (silicon oxide, [0036]).
Regarding claim 3, the combination of Huang and Murray discloses the device of claim 1. Huang goes on to teach wherein the oxide insertion layer (112, Fig 2H) comprises a metal-oxide material (aluminum oxide, [0036]).
Regarding claim 4, the combination of Huang and Murray discloses the device of claim 1. Huang goes on to teach wherein the oxide insertion layer (112, Fig 2H) comprises a high dielectric constant dielectric material (aluminum oxide, [0036]).
Regarding claim 17, Huang teaches a non-volatile memory cell structure (200H, Fig 2H), comprising:
a seed layer (216);
a ferroelectric layer (108) above (shown above) the seed layer (216);
a metal-oxide channel layer (110) above (shown above) the ferroelectric layer (108); and
a plurality of source/drain regions (SD: layers 112/114/118) in (shown in) a dielectric layer (120) above (shown above) the metal-oxide channel layer (110),
wherein a source/drain region (SD) of the plurality of source/drain regions (SD) comprises:
an electron barrier layer (114) on (shown on) the metal-oxide channel layer (110);
an oxide insertion layer (112) on (shown on) the electron barrier layer (114); and
a source/drain electrode (118).
Huang fails to explicitly teach a metal glue layer on the oxide insertion layer; and a source/drain electrode on the metal glue layer.
However, Murray teaches a metal glue layer (1602, Fig 16) on (shown on) the oxide insertion layer; and
a source/drain electrode on (shown on) the metal glue layer (1602).
Huang and Murray are considered analogous to the claimed invention because both are from the same field of endeavor of non-volatile memory cell structure devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Huang with the features of Murray to create a metal glue layer on the oxide insertion layer; and a source/drain electrode on the metal glue layer because the glue layer may assist in adhering the source electrode material and the drain electrode material to the semiconducting material (Murray, [0096]).
Regarding claim 18, the combination of Huang and Murray disclose the device of claim 17. Huang goes on to teach wherein the oxide insertion layer (112, Fig 2H) comprises at least one of:
gallium oxide (GaO), silicon oxide (SiOx) (silicon oxide, [0036]), hafnium oxide (HfOx), aluminum oxide (AlxOy), or zirconium oxide (ZrOx).
Regarding claim 19, the combination of Huang and Murray discloses the device of claim 17. Huang teaches the source/drain electrode (118, Fig 2H) and the dielectric layer (120).
Murray goes on to teach wherein the metal glue layer (1602, Fig 16) is further located between (shown between), and in contact (shown in contact) with, sidewalls (1104SW: sidewalls of S/D electrodes 1102/1104; 802cSW: sidewall of dielectric layer 802c) of the source/drain electrode and the dielectric layer.
Regarding claim 20, the combination of Huang and Murray discloses the device of claim 17. Murray teaches the metal glue layer (1602, Fig 16).
Huang goes on to teach wherein the electron barrier layer (114, Fig 2H; shown as 302 in Fig 4), the oxide insertion layer (112), and … are further located between (shown between, Fig 4) sidewalls (118SW: sidewalls of S/D electrode 118; 120SW: sidewalls of dielectric layer 120) of the source/drain electrode (118) and the dielectric layer (120).
Huang teaches a base product of a source/drain region comprising an electron barrier layer on a metal-oxide channel layer with an oxide insertion layer on the electron barrier, all within a dielectric layer which the claimed invention can be seen as an improvement in that by including the carrier barrier layer along sidewalls of the pair of source/drain electrodes, the carrier barrier layer prevents carriers from going around the carrier barrier layer and to sidewalls of the pair of source/drain electrodes.
Murray teaches a known technique of surrounding the source/drain region with a metal glue layer that contacts the semiconductor layer that is comparable to the base product.
Murray’s known technique, as cited above, would have been recognized by one skilled in the art as applicable to the base product of Huang and the results would have been predictable and resulted in
the glue layer assisting in adhering the source electrode material and the drain electrode material to the semiconducting material (Murray, [0096]), which results in an improved process/product.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time of the effective filing date of the invention, and when combined, Huang and Murray disclose the electron barrier layer, the oxide insertion layer, and the metal glue layer are further located between sidewalls of the source/drain electrode and the dielectric layer.
The rationale to support a conclusion that the claim would have been obvious is that a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. One of ordinary skill in the art would have been capable of applying this known technique to a known device that was ready for improvement and the results would have been predictable to one of ordinary skill in the art.
Regarding claim 21, Huang teaches a non-volatile memory cell structure (200H, Fig 2H), comprising:
a ferroelectric layer (108) above (shown above) a bottom gate electrode (104);
a metal-oxide channel layer (110) above (shown above) the ferroelectric layer (108);
a dielectric layer (120) above (shown above) the metal-oxide channel layer (110);
an electron barrier layer (114; shown as 302 in Fig 4) on (shown on) the metal-oxide channel layer (110) in (shown in, Fig 4) a recess (120R: recess in 120 for 112/302/118) of the dielectric layer (120);
an oxide insertion layer (112) on (shown on) the electron barrier layer (114/302); and
a source/drain electrode (118).
Huang fails to explicitly teach a metal glue layer on the oxide insertion layer; and a source/drain electrode on the metal glue layer.
However, Murray teaches a metal glue layer (1602, Fig 16) on (shown on) the oxide insertion layer; and
a source/drain electrode on (shown on) the metal glue layer (1602).
Huang and Murray are considered analogous to the claimed invention because both are from the same field of endeavor of non-volatile memory cell structure devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Huang with the features of Murray to create a metal glue layer on the oxide insertion layer; and a source/drain electrode on the metal glue layer because the glue layer may assist in adhering the source electrode material and the drain electrode material to the semiconducting material (Murray, [0096]).
Regarding claims 22 and 23, the combination of Huang and Murray discloses the device of claim 21. Murray teaches the metal glue layer (1602, Fig 16).
Huang goes on to teach wherein at least one of the electron barrier layer (114; shown as 302, Fig 4), the oxide insertion layer (112), or … are formed on (both 114 and 112 shown on sidewalls of the recess) sidewalls (120RSW: sidewalls of 120R) of the recess (120R).
Furthermore, Murray teaches the metal glue layer 1602 on the sidewalls of the recess in Fig 16, so when combined with Huang, the electron barrier, oxide insertion, and metal glue layers would all be formed on the sidewalls of the recess. Therefore, the combination discloses the limitations of claim 23 as well.
Regarding claim 24, the combination of Huang and Murray discloses the device of claim 22. Huang goes on to teach wherein the electron barrier layer (114; shown as 302, Fig 4) is formed on (shown on) sidewalls (120RSW: sidewalls of 120R) of the recess (120R).
Regarding claim 26, although claim 25 was rejected under USC112b as discussed above, the combination of Huang and Murray discloses the device of claim 24 upon which claim 25 depends. Huang goes on to teach wherein the oxide insertion layer (112, Fig 2H) is formed on (shown on) the sidewalls (120RSW: sidewalls of 120R) of the recess (120R).
Regarding claim 28, although claim 27 was rejected under USC112b as discussed above, the combination of Huang and Murray discloses the device of claim 26 upon which claim 27 depends. Huang teaches sidewalls (120RSW: sidewalls of 120R) of the recess (120R).
Murray goes on to teach wherein the metal glue layer (1602, Fig 16) is formed on (shown on) sidewalls of the recess.
Regarding claim 29, although claim 27 was rejected under USC112b as discussed above, the combination of Huang and Murray discloses the device of claim 26 upon which claim 27 depends. Huang teaches the source/drain electrode (118, Fig 2H) and sidewalls (120RSW: sidewalls of 120R) of the recess (120R).
Murray goes on to teach wherein the metal glue layer (1602, fig 16) is formed between (shown between) the source/drain electrode and sidewalls of the recess.
Regarding claim 30, the combination of Huang and Murray discloses the device of claim 21. Huang goes on to teach wherein the oxide insertion layer (112, Fig 2H) comprises an oxide-semiconductor material (silicon oxide, [0036]).
Regarding claim 31, the combination of Huang and Murray discloses the device of claim 21. Huang goes on to teach wherein the oxide insertion layer (112, Fig 2H) comprises a metal-oxide material (aluminum oxide, [0036]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20220285519 A1), in view of Murray (US 20230029955 A1), and further in view of Jhaveri (US 20200161440 A1).
Regarding claim 5, the combination of Huang and Murray discloses the device of claim 1. Huang teaches the oxide insertion layer (112, Fig 2H).
The combination fails to explicitly teach a thickness of the oxide insertion layer is included in a range of approximately 0.5 angstroms to approximately 5 nanometers.
However, Jhaveri teaches wherein a thickness (4 nm; no more than 5 nm, [claim 59]) of the oxide insertion layer is included in (conformal layer 118 comprises a semiconductor material lining the source/drain region that is then filled with contact metal, [0017]) a range (included in the range) of approximately 0.5 angstroms to approximately 5 nanometers.
Huang, Murray, and Jhaveri are considered analogous to the claimed invention because all are from the same field of endeavor of non-volatile memory cell structure devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Huang and Murray with the features of Jhaveri to create a thickness of the oxide insertion layer is included in a range of approximately 0.5 angstroms to approximately 5 nanometers because the nucleation layer provides a greater surface area to interface with contact metal (Jhaveri, [0017]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dewey (US 20200411692 A1) - contact buffer metal oxide layer around S/D contacts with less than 5 nm thickness
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeremy D Watts whose telephone number is (703)756-1055. The examiner can normally be reached M-R 8:00am-4:30pm, F 8:00-3pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897