DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-13 and 17-25) in the reply filed on 01/21/2026 is acknowledged.
Claims 14-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/21/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 5, and 17-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "the conditions of depositing of the second silicon layer in line 2. There is insufficient antecedent basis for this limitation in the claim and therefore this limitaiton renders the claim indefinite.
Claim 5 recites the limitation "the same deposition" in line 2. There is insufficient antecedent basis for this limitation in the claim and therefore this limitaiton renders the claim indefinite.
Claim 17 recites the limitaiton “when depositing the second silicon layer.” This limitaiton renders the claim indefinite because it is unclear whether the recitations following the phrase “when” are parts of the claimed inventions or optional steps.
Claims 18-21 are indefinite due to their dependance on indefinite claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 4-7, 11-13, 17-19, 21-23, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Brouillette (US 5, 913, 125) in view of Sawada (US 4, 977, 104) and Im (US 2022/0165608).
Regarding claim 1, Brouillette discloses a method of forming a semiconductor device, the method comprising: depositing a first silicon layer (Fig.5, numeral 40) in a trench (38) of a semiconductor substrate (22),; depositing a second silicon layer (Fig.7, numeral 24) on top of and in contact with the first silicon layer (40), the second silicon layer being deposited as a polysilicon layer (column 6, lines 10-15),; and depositing a third semiconductor layer (Fig.8, numeral 26) on top of and in contact with the second silicon layer (24) to fill the trench.
Brouillette does not disclose (1) the first silicon layer being deposited as an amorphous layer; (2) wherein, after depositing the second silicon layer, the first silicon layer comprises polysilicon having an average grain size different than an average grain size of the second silicon layer.
Regarding element (1), Brouillette discloses that the first silicon layer (40) is polycrystalline. And Im discloses forming a polycrystalline layer (Fig. 2C, numeral 123) by deposing the first silicon layer being deposited as an amorphous layer (Fig.2B, numeral 121; [0031]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Brouillette with Im to deposit the first silicon layer as an amorphous layer because this is a typical method for forming polysilicon layers (Im, [0037]).
Regarding element (2), Brouillette discloses that the first silicon layer is intrinsic polysilicon layer (column 5, lines 65-67) and the second polysilicon layer is a p-doped polysilicon layer (column 6, lines 9-12). And Sawada discloses that the grain size in polysilicon layer depends on doping concentration (Fig.8b).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Brouillette with Sawada to have after depositing the second silicon layer, the first silicon layer comprises polysilicon having an average grain size different than an average grain size of the second silicon layer because this a typical result of different doping concentrations in polysilicon films.
Regarding claim 3, Im discloses after depositing of the first silicon layer and before depositing the second silicon layer, annealing the first silicon layer to crystallize and transition the first silicon layer from an amorphous state to a polycrystalline state ([0031]).
Regarding claim 4, Brouillette does not disclose after depositing the third semiconductor layer, the first silicon layer is tensile and the second silicon layer is compressive.
Brouillette however discloses controlling stress leave in the substate regions (column 3, lines 30-35).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was field to have the stress in the first and second silicon layers to be in the claimed range for the purpose controlling forces applied to the deposited layers (Brouillette, column 3, lines 41-50).
Regarding claim 5, Brouillette discloses wherein depositing the first silicon layer and depositing the second silicon layer comprises depositing the first silicon layer and depositing the second silicon layer in situ in the same deposition chamber without removing the substrate from the chamber between depositing the first silicon layer and depositing the second silicon layer (column 6, lines 1-10).
Regarding claim 6, Brouillette discloses depositing a dielectric layer in the trench before the depositing of the first silicon layer (column 7, lines 1-15).
Regarding claim 7, Brouillette discloses depositing the first silicon layer comprises depositing the first silicon layer on top of and in contact with the dielectric layer (column 7, lines 1-15).
Regarding claim 11, Brouillette discloses wherein the third semiconductor layer comprises a third doped silicon layer, and wherein depositing the third semiconductor layer comprises depositing the third doped silicon layer in amorphous deposition conditions (column 4, lines 26-40).
Regarding claim 12, Sawada discloses the first silicon layer comprises polysilicon having an average grain size larger than the grain size of the second silicon layer (Fig.8B).
Regarding claim 13, Brouillette in view of Sawada does not discloses wherein the average grain size of the first silicon layer is in the range from 50 to 120 nm, and the average grain size of the second silicon layer is in the range from 10 to 30 nm.
It would have been however obvious to one of ordinary skill in the art at the time the invention was filed to adjust the average grain size to be in the claimed range for the purpose for the purpose of optimizing doping concentrations (Sawada, Abstract).
Regarding claim 17, Brouillette discloses a method of forming a semiconductor device, the method comprising: depositing a dielectric layer on lateral walls and at a bottom of a trench of a semiconductor substrate (column 7, lines 1-15); depositing a first silicon layer (Fig.6, numeral 40) over the dielectric layer(column 7, lines 1-15,; depositing a second silicon layer (Fig.7, numeral 24) in contact with the first silicon layer (40), the second silicon layer being deposited in polysilicon deposition conditions as a polysilicon layer (column 6, lines 10-15),; and depositing a third semiconductor layer (26) in contact with the second silicon layer (24) to fill the trench, the third semiconductor layer (26) being deposited in amorphous deposition conditions (column 4, lines 14-20).
Brouillette does not disclose (1) the first silicon layer being deposited as an amorphous layer, wherein silicon of the first silicon layer crystallizes and transition from an amorphous state to a polycrystalline state when depositing the second silicon layer; (2) that the first silicon layer comprises polysilicon having an average grain size different than an average grain size of the second silicon layer
Regarding element (1), Brouillette discloses that the first silicon layer (40) is polycrystalline. And Im discloses forming a polycrystalline layer (Fig. 2C, numeral 123) by deposing the first silicon layer being deposited as an amorphous layer wherein silicon of the first silicon layer crystallizes and transition from an amorphous state to a polycrystalline state when depositing the second silicon layer (Fig.2B, numeral 121; [0031]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Brouillette with Im to deposit the first silicon layer as an amorphous layer wherein silicon of the first silicon layer crystallizes and transition from an amorphous state to a polycrystalline state when depositing the second silicon layer because this is a typical method for forming polysilicon layers (Im, [0037]).
Regarding element (2), Brouillette discloses that the first silicon layer is intrinsic polysilicon layer (column 5, lines 65-67) and the second polysilicon layer is a p-doped polysilicon layer (column 6, lines 9-12). And Sawada discloses that the grain size in polysilicon layer depends on doping concentration (Fig.8b).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Brouillette with Sawada to have after depositing the second silicon layer, the first silicon layer comprises polysilicon having an average grain size different than an average grain size of the second silicon layer because this a typical result of different doping concentrations in polysilicon films.
Regarding claim 18, Brouillette does not disclose after depositing the third semiconductor layer, the first silicon layer is tensile and the second silicon layer is compressive.
Brouillette however discloses controlling stress leave in the substate regions (column 3, lines 30-35).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was field to have the stress in the first and second silicon layers to be in the claimed range for the purpose controlling forces applied to the deposited layers (Brouillette, column 3, lines 41-50).
Regarding claim 19, Brouillette discloses wherein depositing the first silicon layer and depositing the second silicon layer comprises depositing the first silicon layer and depositing the second silicon layer in situ in the same deposition chamber without removing the substrate from the chamber between depositing the first silicon layer and depositing the second silicon layer (column 6, lines 1-10).
Regarding claim 21, Brouillette in view of Sawada does not discloses wherein the average grain size of the first silicon layer is in the range from 50 to 120 nm, and the average grain size of the second silicon layer is in the range from 10 to 30 nm.
It would have been however obvious to one of ordinary skill in the art at the time the invention was filed to adjust the average grain size to be in the claim range for the purpose of optimizing doping concentrations (Sawada, Abstract).
Regarding claim 22, Brouillette discloses a method of forming a semiconductor device, the method comprising: depositing a dielectric layer on lateral walls and at a bottom of a trench of a semiconductor substrate (column 5, lines 55-65); depositing a first silicon layer (40) over the dielectric layer (column 5, lines 55-65), after annealing the first silicon layer (40), depositing a second silicon layer (24) in contact with the first silicon layer (40), the second silicon layer (24) being deposited in polysilicon deposition conditions as a polysilicon layer (column 6, lines 10-15),; and depositing a third semiconductor layer (26) in contact with the second silicon layer to at least partially fill the trench, the third semiconductor layer being deposited in amorphous deposition conditions (column 6, lines 20-28).
Brouillette does not disclose (1) the first silicon layer being deposited in amorphous deposition conditions as an amorphous layer ; after depositing of the first silicon layer, annealing the first silicon layer to crystallize and transition the first silicon layer from an amorphous state to a polycrystalline state (2) wherein, after depositing the second silicon layer, the first silicon layer comprises polysilicon having an average grain size different than an average grain size of the second silicon layer.
Regarding element (1), Brouillette discloses that the first silicon layer (40) is polycrystalline. And Im discloses forming a polycrystalline layer (Fig. 2C, numeral 123) by deposing the first silicon layer being deposited as an amorphous layer (Fig.2B, numeral 121; [0031]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Brouillette with Im to deposit the first silicon layer as an amorphous layer because this is a typical method for forming polysilicon layers (Im, [0037]).
Regarding element (2), Brouillette discloses that the first silicon layer is intrinsic polysilicon layer (column 5, lines 65-67) and the second polysilicon layer is a p-doped polysilicon layer (column 6, lines 9-12). And Sawada discloses that the grain size in polysilicon layer depends on doping concentration (Fig.8b).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Brouillette with Sawada to have after depositing the second silicon layer, the first silicon layer comprises polysilicon having an average grain size different than an average grain size of the second silicon layer because this a typical result of different doping concentrations in polysilicon films.
Regarding claim 23, Brouillette does not disclose after depositing the third semiconductor layer, the first silicon layer is tensile and the second silicon layer is compressive.
Brouillette however discloses controlling stress leave in the substate regions (column 3, lines 30-35).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was field to have the stress in the first and second silicon layers to be in the claimed range for the purpose controlling forces applied to the deposited layers (Brouillette, column 3, lines 41-50).
Regarding claim 25, Brouillette in view of Sawada does not discloses wherein the average grain size of the first silicon layer is in the range from 50 to 120 nm, and the average grain size of the second silicon layer is in the range from 10 to 30 nm.
It would have been however obvious to one of ordinary skill in the art at the time the invention was filed to adjust the average grain size to be in the claim range for the purpose of optimizing doping concentrations (Sawada, Abstract).
Allowable Subject Matter
Claims 8-10, 20 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 2 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The search of the prior art does not disclose or reasonably suggest wherein silicon of the first silicon layer crystallizes and transition from an amorphous state to a polycrystalline state during the depositing of the second silicon layer as required by claim 2.
The search of the prior art does not disclose or reasonably suggest wherein the first silicon layer is doped in situ when depositing the first silicon layer as required by claim 8.
The search of the prior art does not disclose or reasonably suggest after depositing the second silicon layer and before depositing the third semiconductor layer, thinning an intermediate structure formed after the depositing of the second silicon layer by removing portions of an upper surface of the intermediate structure as required by claims 9 and 20, and 22.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm.
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/JULIA SLUTSKER/ Primary Examiner, Art Unit 2891
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