DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5-8, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Beinglass (US 5, 141, 892) in view of Sawada (US 4, 977, 104) and Im (US 2022/0165608).
Regarding claim 1, Beinglass discloses a method of forming a semiconductor device, the method comprising: depositing a first doped silicon layer (Fig. 4, numeral 60) (column 3, lines 45-50) in a trench (40) of a semiconductor substrate (30); depositing a second silicon layer (70) on top of and in contact with the first silicon layer (60), the second silicon layer (70) being deposited as a polysilicon layer (column 4, lines 20-25), and depositing a third semiconductor layer (Fig.5, numeral 80) on top of and in contact with the second silicon layer (70) to fill the trench (40).
Beinglass does not disclose (1) the first silicon layer being deposited as an amorphous layer; (2) wherein, after depositing the second silicon layer, the first silicon layer comprises polysilicon having an average grain size different than an average grain size of the second silicon layer.
Regarding element (1), Beinglass discloses that the first silicon layer (60) is polycrystalline (column 3, lines 45-50). And Im discloses forming a polycrystalline layer (Fig. 2C, numeral 123) by deposing the first silicon layer being deposited as an amorphous layer (Fig.2B, numeral 121; [0031]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Beinglass with Im to deposit the first silicon layer as an amorphous layer because this is a typical method for forming polysilicon layers (Im, [0037]).
Regarding element (2), Beinglass discloses that the first silicon layer is doped polysilicon layer (column 3, lines 45-50) and the second polysilicon layer is a undoped polysilicon layer (column 4, lines 16-20). And Sawada discloses that the grain size in polysilicon layer depends on doping concentration (Fig.8b).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Beinglass with Sawada to have after depositing the second silicon layer, the first silicon layer comprises polysilicon having an average grain size different than an average grain size of the second silicon layer because this a typical result of different doping concentrations in polysilicon films.
Regarding claim 3, Im discloses after depositing of the first silicon layer and before depositing the second silicon layer, annealing the first silicon layer to crystallize and transition the first silicon layer from an amorphous state to a polycrystalline state ([0031]).
Regarding claim 5, Beinglass discloses wherein depositing the first silicon layer and depositing the second silicon layer comprises depositing the first silicon layer and depositing the second silicon layer in situ in the same deposition chamber without removing the substrate from the chamber between depositing the first silicon layer and depositing the second silicon layer (column 4, lines 1-30).
Regarding claim 6, Beinglass discloses depositing a dielectric layer in the trench before the depositing of the first silicon layer (column 3, lines 40-45).
Regarding claim 7, Beinglass discloses depositing the first silicon layer comprises depositing the first silicon layer on top of and in contact with the dielectric layer (column 3, lines 40-50).
Regarding claim 8, Beinglass discloses wherein the first silicon layer (60) is doped in situ when depositing the first silicon layer (column 3, lines 50-65).
Regarding claim 12, Sawada discloses the first silicon layer comprises polysilicon having an average grain size larger than the grain size of the second silicon layer (Fig.8B).
Regarding claim 13, Beinglass in view of Sawada does not discloses wherein the average grain size of the first silicon layer is in the range from 50 to 120 nm, and the average grain size of the second silicon layer is in the range from 10 to 30 nm.
It would have been however obvious to one of ordinary skill in the art at the time the invention was filed to adjust the average grain size to be in the claimed range for the purpose for the purpose of optimizing doping concentrations (Sawada, Abstract).
Claim(s) 4 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Beinglass in view of Sawada and Im as applied to claim 1 above, and further in view of Brouillette (US 5, 913, 125).
Regarding claim 4, Beinglass does not disclose wherein, after depositing the third semiconductor layer, the first silicon layer is tensile and the second silicon layer is compressive.
Brouillette however discloses controlling stress leave in the substate regions (column 3, lines 30-35).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was field to have the stress in the first and second silicon layers to be in the claimed range for the purpose controlling forces applied to the deposited layers (Brouillette, column 3, lines 41-50).
Regarding claim 11, Beinglass does not disclose wherein the third semiconductor layer comprises a third doped silicon layer, and wherein depositing the third semiconductor layer comprises depositing the third doped silicon layer in amorphous deposition conditions.
Brouillette however discloses wherein the third semiconductor layer comprises a third doped silicon layer, and wherein depositing the third semiconductor layer comprises depositing the third doped silicon layer in amorphous deposition conditions (column 4, lines 26-40).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Beinglass with Brouillette to have the third semiconductor layer comprises a third doped silicon layer, and wherein depositing the third semiconductor layer comprises depositing the third doped silicon layer in amorphous deposition conditions for the purpose of controlling stress level (Brouillette, column 3, lines 50-61)
Allowable Subject Matter
Claims 2, 9 and 10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 17-28 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The search of the prior art does not disclose or reasonably suggest wherein silicon of the first silicon layer crystallizes and transition transitions from an amorphous state to a polycrystalline state during the depositing of the second silicon layer as required by claim 2.
The search of the prior art does not disclose or reasonably suggest after depositing the second silicon layer and before depositing the third semiconductor layer, thinning an intermediate structure formed after the depositing of the second silicon layer by removing portions of an upper surface of the intermediate structure as required by claim 9.
The search of the prior art does not disclose or reasonably suggest wherein silicon of the first silicon layer crystallizes and transitions from an amorphous state to a polycrystalline state concurrently with depositing the second silicon layer so that the first silicon layer comprises polysilicon having an average grain size different than an average grain size of the second silicon layer as required by amended independent claim 17.
The search of the prior art does not disclose or reasonably suggest removing portions of the second silicon layer from an upper surface of the semiconductor substrate as required by independent claim 22.
The search of the prior art does not disclose or reasonably suggest removing portions of the second polysilicon layer from an upper surface of the semiconductor substrate as required by claim 26.
Response to Arguments
Applicant’s arguments with respect to claims 1, 3-8, and 11- 13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm.
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/JULIA SLUTSKER/Primary Examiner, Art Unit 2891
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