Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/466,744 filed on March 06, 2026.
Specification
3. The title of the invention has been amended as “Semiconductor Structure and Method for Manufacturing the Semiconductor Structure Comprising Etch Stop Layer”.
Claim Objections
4. The objections on claims 1-3, 6-11, 16-20 have been withdrawn per the response dated on 03/06/2026.
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. This application currently names joint inventors. In considering patentability of the claims under pre-AIA 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of pre-AIA 35 U.S.C. 103(c) and potential pre-AIA 35 U.S.C. 102(e), (f) or (g) prior art under pre-AIA 35 U.S.C. 103(a).
8. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or non-obviousness.
9. Claims 1-4, 6, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2019/0131273 A1) in view of Shih (US 2020/0251454 A1).
Regarding independent claim 1, Chen et al. teaches a semiconductor structure comprising (4, Fig. 4):
a first die (101, para [0039]), comprising:
a first substrate (100a, para [0018]) having a first active area at a front surface (upper surface) of the first substrate (100a);
a first redistribution layer (RDL) (RDL2, para [0022]: left segment) disposed over the front surface of the first substrate (100a); and
a first back-side (bottom surface) through via (BSTV) (TSV1, para [0039]) extending from a back surface of the first substrate (100a) toward the front surface of the first substrate (100a);
a second die (201, para [0038]) disposed adjacent to the first die (101), and separated from the first die (101) by a molding material (E1, para [0021]), wherein the second die (201) comprises:
a second substrate (200a, para [0019]) having a second active area at a front surface of the second substrate (200a);
a second RDL (RDL2: right segment) disposed over the front surface of the second substrate (200a); and
a second BSTV (TSV2) extending from a back surface of the second substrate (200a) toward the front surface of the second substrate (200a); and
a third RDL (RDL1) continuously disposed over the back surfaces of the first substrate (100a) and the second substrate (200a), and electrically connected to the first RDL (RDL2 left segment) through the first BSTV (TSV1) and to the second RDL (RDL2 right segment) through the second BSTV (TVS2).
Chen et al. is explicitly silent of disclosing wherein, the first BSTV and the second BSTV are in direct contact with the third RDL.
Shih teaches wherein (Fig. 2I upside down), the first BSTV (120 TSV left, para [0033]) and the second BSTV (120 TSV right) are in direct contact with the third RDL (138, para [0043]).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Shih, and modify the structure of Chen et al., by aligning TSV to the redistribution layers front and back surfaces of the semiconductor substrate, in order to transmit signals from the back side of the semiconductor die to the active side of the semiconductor die via the TSV, therefore, transmission length of the signals transmitted between the back side of the semiconductor die and the active side of the semiconductor die is shortened, and requirement on routing density of the front redistribution structure of the semiconductor package can be alleviated, and reliability of the semiconductor package can be improved (para [0024]).
Regarding claim 2, Chen et al. and Shih teach all of the limitations of claim 1 from which this claim depends.
Chen et al. teaches wherein (Fig. 4), further comprising:
a plurality of connectors (100e, 200e), disposed on the third RDL (RDL1) opposite to the first die (101) and the second die (201), wherein the plurality of connectors (100e, 200e) are electrically connected to the first die (101) through the first BSTV (TSV1) and to the second die (201) through the second BSTV (TVS2) for power supply to the first die and the second die (this is a functional limitation/ an intended use).
Regarding claim 3, Chen et al. and Shih teach all of the limitations of claim 2 from which this claim depends.
Chen et al. teaches wherein (Fig. 4), the first die (101) includes a plurality of first BSTVs (TSV1 left/right), and each of the plurality of first BSTVs in a central region of the first die (101) are electrically coupled to the plurality of connectors (100e) through the third RDL (RDL1).
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Regarding claim 4, Chen et al. and Shih teach all of the limitations of claim 1 from which this claim depends.
Chen et al. teaches wherein (Fig. 4), the first die (101) is one of a plurality of input/output (I/O) dies (input/output signals, para [0034]) configured to receive an I/O signal from the third RDL through the first BSTV (this is a functional limitation/ an intended use), or to transmit an I/O signal to the third RDL through the first BSTV, wherein the first BSTV is in a peripheral region of the first die.
Regarding claim 6, Chen et al. and Shih teach all of the limitations of claim 1 from which this claim depends.
Chen et al. teaches wherein (Fig. 4), the third RDL (RDL1) comprises:
a plurality of dielectric layers (102 polymer layers, para [0015]), each of the dielectric layers being a continuous layer extending over the back surfaces of the first substrate (100a) and the second substrate (200a) and over the molding material (E1) filling a space between the first die (101) and the second die (201); and
a plurality of metal layers (104 made of copper, para [0015]) surrounded by the plurality of dielectric layers (102).
Regarding claim 13, Chen et al. and Shih teach all of the limitations of claim 1 from which this claim depends.
Chen et al. teaches wherein (Fig. 4), a thickness of the first substrate (100a) is substantially equal (100a and 200a are in equal height, see Fig. 4) to a thickness of the second substrate (200a), and the thickness of the first substrate or the second substrate discloses a certain defined thickness according the figure 4.
Even Chen et al. is explicitly silent of disclosing wherein the thickness of the first substrate or the second substrate is less than or equal to 1 micron. It would have been obvious to select intended ‘thickness of the first substrate or the second substrate’ so that the thickness to be within the quoted range of 1 micron or less, to optimize the size of the device or miniature of a packaged device. In addition, to an ordinary artisan practicing the invention, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen thickness or upon another variable recited in a claim, the Applicant must show that the chosen thickness is critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed. Cir. 1990).
10. Claims 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2019/0131273 A1) in view of Shih (US 2020/0251454 A1) as applied to claim 1 above, and further in view of Yu et al. (US 2017/0263518 A1).
Regarding claim 7, Chen et al. and Shih teach all of the limitations of claim 1 from which this claim depends.
Chen et al. and Shih are explicitly silent of disclosing wherein, further comprising:
a support substrate disposed over the first RDL and the second RDL, wherein the support substrate is connected to the first die and the second die by a fusion bonding layer.
Yu et al. teaches wherein (Fig. 16), further comprising:
a support substrate (66B package component, para [0032]) disposed over the first RDL (see the annotated figure below) and the second RDL (see the annotated figure below), wherein the support substrate (66B) is connected to the first die (100B) and the second die (100C) by a fusion bonding layer (para [0032]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Yu et al., and modify the structure of Chen et al. and Shih, by aligning the package component on both of the substrates, in order to minimize the voltage drop caused by the resistance of the metal lines (para [0033]).
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Regarding claim 8, Chen et al. and Shih teach all of the limitations of claim 1 from which this claim depends.
Chen et al. and Shih are explicitly silent of disclosing wherein, further comprising:
a fourth RDL disposed over the first RDL and the second RDL, wherein the fourth RDL is connected to the first die and the second die by a hybrid bonding layer.
Yu et al. teaches wherein (Fig. 16), further comprising:
a fourth RDL (see the annotated figure in claim 7) disposed over the first RDL (see the annotated figure in claim 7) and the second RDL (see the annotated figure in claim 7), wherein the fourth RDL is connected to the first die (100B) and the second die (100C) by a hybrid bonding layer (para [0032]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Yu et al., and modify the structure of Chen et al. and Shih, by aligning the package component along with the redistribution layer on the substrates, in order to minimize the voltage drop caused by the resistance of the metal lines (para [0033]), and regulate the voltage supplies for package components.
Regarding claim 9, Chen et al. and Shih and Yu et al. teach all of the limitations of claim 7 from which this claim depends.
Chen et al. and Shih are explicitly silent of disclosing wherein, further comprising:
the support substrate disposed over the fourth RDL opposite to the third RDL, wherein the fourth RDL is connected to the support substrate by a fusion bonding layer.
Yu et al. teaches wherein (Fig. 16), further comprising:
the support substrate (66B) disposed over the fourth RDL (see the annotated figure in claim 7) opposite to the third RDL (see the annotated figure in claim 7), wherein the fourth RDL is connected to the support substrate (66B) by a fusion bonding layer (para [0032]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Yu et al., and modify the structure of Chen et al. and Shih, by aligning the package component on both of the substrates, in order to minimize the voltage drop caused by the resistance of the metal lines (para [0033]), and regulate the voltage supplies for package components.
Regarding claim 10, Chen et al. and Shih and Yu et al. teach all of the limitations of claim 7 from which this claim depends.
Chen et al. and Shih are explicitly silent of disclosing wherein, further comprising:
a semiconductor substrate disposed over the fourth RDL opposite to the third RDL, wherein the semiconductor substrate includes a third active area at a front surface facing the fourth RDL.
Yu et al. teaches wherein (Fig. 16), further comprising:
a semiconductor substrate (66A) disposed over the fourth RDL (see figure in claim 7) opposite to the third RDL, wherein the semiconductor substrate (66A) includes a third active area at a front surface facing the fourth RDL.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Yu et al., and modify the structure of Chen et al. and Shih, by aligning the package component on the substrate, in order to minimize the voltage drop caused by the resistance of the metal lines (para [0033]).
Regarding claim 11, Chen et al. and Shih and Yu et al. teach all of the limitations of claim 9 from which this claim depends.
The combination of Chen et al. and Yu et al. teaches, further comprising:
a through molding via (TMV) (TIV, see Fig. 4, Chen et al.) penetrating the molding material (E1), wherein the TMV (TIV) electrically connects the third RDL (RDL1) to the fourth RDL (see figure in claim 7, Yu et al.) for providing a power supply from the third RDL to the semiconductor substrate.
Allowable Subject Matter
11. Claims 14-20 are allowed.
12. The following is an examiner’s statement of reasons for allowance:
Claim 14: the prior art of record alone or in combination neither teaches nor makes obvious a method for manufacturing a semiconductor structure, comprising:
….
reducing a thickness of the first substrate from a back surface of the first substrate until an exposure of the etch stop layer occurs;
Claims 5, 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 5 recites ….the second die is one of a plurality of processor dies configured to transmit or process a die-to-die signal between the processor dies through the second BSTV, wherein the second BSTV is in a peripheral region of the second die.
Claim 12 recites….the first die further comprises a first power rail disposed in the first substrate, and the first BSTV contacts a bottom of the first power rail; and the second die further comprises a second power rail disposed in the second substrate, and the second BSTV contacts a bottom of the second power rail.
13. Prior arts made of record in PTO-892 and not relied upon are considered pertinent to applicant’s disclosure: the prior arts, Chen et al. (US 2019/0131273 A1) and Yu et al. (US 2017/0263518 A1) hereby are cited as close prior arts, disclose the semiconductor structure comprising the multiple dies including substrates wherein the through-via penetrating from the bottom surface of the substrates, and redistribution layers deposited on the bottom and top surfaces of the multiple dies, but fail to disclose the claim languages stated in the section 12, therefore, by itself or in combination or with other prior arts does not disclose the limitations as stated in the section 12.
Response to Arguments
14. It has been acknowledged that the applicant amended claims 1-3, 6-11, 16-20, per the response dated on 03/06/2026.
Applicant’s arguments in page 2 of the remark section, w.r.t. the amended claim 1 have been reviewed carefully, however, the amended limitation of the claim 1 has been rejected by citing a new reference, Shih (US 2020/0251454 A1) as explained above.
Conclusion
15. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
16. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
17. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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