Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/466,744 filed on September 13, 2023.
Information Disclosure Statement
3. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Specification
4. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Semiconductor Structure and Method for Manufacturing the Semiconductor Structure Comprising Etch Stop Layer”.
Claim Objections
5. Claims 1-3, 6-11, 16-20 are objected to because of the following informalities: In the following, the claims should be recited to avoid indefiniteness due to lack of antecedent basis, and/or perform proper alignment along with the prior claim languages/phrases:
1. (Currently Amended) A semiconductor structure comprising:
a first die, comprising:
a first substrate
a first redistribution layer (RDL)
a first back-side through via (BSTV)
a second die
a second substrate
a second RDL
a second BSTV
a third RDL
2. (Currently Amended) The semiconductor structure of claim 1, further comprising:
a plurality of connectorsplurality of connectors are electrically connected to the first die through the first BSTV and to the second die through the second BSTV for power supply to the first die and the second die.
3. (Currently Amended) The semiconductor structure of claim 2, wherein the first die includes a plurality of first BSTVs, and each of the plurality of first BSTVs in a central region of the first die are electrically coupled to the plurality of connectors through the third RDL.
6. (Currently Amended) The semiconductor structure of claim 1, wherein the third RDL comprises:
a plurality of dielectric layers, each of the dielectric layers being a continuous layer extending over the back surfaces of the first substrate and the second substrate and over the molding material filling a space between the first die and the second die; and
a plurality of metal layers
7. (Currently Amended) The semiconductor structure of claim 1, further comprising:
a support substrate
8. (Currently Amended) The semiconductor structure of claim 1, further comprising:
a fourth RDL
9. (Currently Amended) The semiconductor structure of claim 7, further comprising:
the support substrate
10. (Currently Amended) The semiconductor structure of claim 7, further comprising:
a semiconductor substrate
11. (Currently Amended) The semiconductor structure of claim 9, further comprising:
a through molding via (TMV)
16. (Currently Amended) The method of claim 14, wherein a depth of the BSTV is
17. (Currently Amended) The method of claim 14, wherein
flipping over the first substrate, wherein the front surface of the first substrate faces downward; and
attaching the first substrate to the second substrate prior to the reduction of the thickness of the first substrate.
18. (Currently Amended) The method of claim 17, wherein
performing a fusion bonding operation to fuse a first dielectric layer over the first RDL to a second dielectric layer over the second substrate.
19. (Currently Amended) The method of claim 17, wherein
performing a hybrid bonding operation to bond the first substrate to the second substrate through a first hybrid layer of the first RDL and a second hybrid layer over the second substrate.
20. (Currently Amended) The method of claim 14, wherein reducing the thickness of the first substrate comprises:
performing a grinding operation on the back surface of the first substrate, wherein a thickness of the first substrate after the grinding operation is in a range of 10 to 50 microns; and
performing a first polishing operation on the back surface of the first substrate to expose the etch stop layer; and
performing a second polishing operation to remove the etch stop layer prior to forming the BSTV.
Appropriate corrections are needed.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claims 1-4, 6 are rejected under 35 U.S.C. 102(a)(1)/ (a)(2) as being anticipated by Chen et al. (US 2019/0131273 A1).
Regarding independent claim 1, Chen et al. teaches a semiconductor structure comprising (4, Fig. 4):
a first die (101, para [0039]), comprising:
a first substrate (100a, para [0018]) having a first active area at a front surface (upper surface) of the first substrate (100a);
a first redistribution layer (RDL) (RDL2, para [0022]: left segment) disposed over the front surface of the first substrate (100a); and
a first back-side (bottom surface) through via (BSTV) (TSV1, para [0039]) extending from a back surface of the first substrate (100a) toward the front surface of the first substrate (100a);
a second die (201, para [0038]) disposed adjacent to the first die (101), and separated from the first die (101) by a molding material (E1, para [0021]), wherein the second die (201) comprises:
a second substrate (200a, para [0019]) having a second active area at a front surface of the second substrate (200a);
a second RDL (RDL2: right segment) disposed over the front surface of the second substrate (200a); and
a second BSTV (TSV2) extending from a back surface of the second substrate (200a) toward the front surface of the second substrate (200a); and
a third RDL (RDL1) continuously disposed over the back surfaces of the first substrate (100a) and the second substrate (200a), and electrically connected to the first RDL (RDL2 left segment) through the first BSTV (TSV1) and to the second RDL (RDL2 right segment) through the second BSTV (TVS2).
Regarding claim 2, Chen et al. teaches wherein (Fig. 4), further comprising:
a plurality of connectors (100e, 200e), disposed on the third RDL (RDL1) opposite to the first die (101) and the second die (201), wherein the plurality of connectors (100e, 200e) are electrically connected to the first die (101) through the first BSTV (TSV1) and to the second die (201) through the second BSTV (TVS2) for power supply to the first die and the second die (this is a functional limitation/ an intended use).
Regarding claim 3, Chen et al. teaches wherein (Fig. 4), the first die (101) includes a plurality of first BSTVs (TSV1 left/right), and each of the plurality of first BSTVs in a central region of the first die (101) are electrically coupled to the plurality of connectors (100e) through the third RDL (RDL1).
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Regarding claim 4, Chen et al. teaches wherein (Fig. 4), the first die (101) is one of a plurality of input/output (I/O) dies (input/output signals, para [0034]) configured to receive an I/O signal from the third RDL through the first BSTV (this is a functional limitation/ an intended use), or to transmit an I/O signal to the third RDL through the first BSTV, wherein the first BSTV is in a peripheral region of the first die.
Regarding claim 6, Chen et al. teaches wherein (Fig. 4), the third RDL (RDL1) comprises:
a plurality of dielectric layers (102 polymer layers, para [0015]), each of the dielectric layers being a continuous layer extending over the back surfaces of the first substrate (100a) and the second substrate (200a) and over the molding material (E1) filling a space between the first die (101) and the second die (201); and
a plurality of metal layers (104 made of copper, para [0015]) surrounded by the plurality of dielectric layers (102).
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
10. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. This application currently names joint inventors. In considering patentability of the claims under pre-AIA 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of pre-AIA 35 U.S.C. 103(c) and potential pre-AIA 35 U.S.C. 102(e), (f) or (g) prior art under pre-AIA 35 U.S.C. 103(a).
12. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or non-obviousness.
13. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2019/0131273 A1) as applied to claim 1 above.
Regarding claim 13, Chen et al. teaches all of the limitations of claim 1 from which this claim depends.
Chen et al. teaches wherein (Fig. 4), a thickness of the first substrate (100a) is substantially equal (100a and 200a are in equal height, see Fig. 4) to a thickness of the second substrate (200a), and the thickness of the first substrate or the second substrate discloses a certain defined thickness according the figure 4.
Even Chen et al. is explicitly silent of disclosing wherein the thickness of the first substrate or the second substrate is less than or equal to 1 micron. It would have been obvious to select intended ‘thickness of the first substrate or the second substrate’ so that the thickness to be within the quoted range of 1 micron or less, to optimize the size of the device or miniature of a packaged device. In addition, to an ordinary artisan practicing the invention, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen thickness or upon another variable recited in a claim, the Applicant must show that the chosen thickness is critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed. Cir. 1990).
14. Claims 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2019/0131273 A1) as applied to claim 1 above, and further in view of Yu et al. (US 2017/0263518 A1).
Regarding claim 7, Chen et al. teaches all of the limitations of claim 1 from which this claim depends.
Chen et al. is explicitly silent of disclosing wherein, further comprising:
a support substrate disposed over the first RDL and the second RDL, wherein the support substrate is connected to the first die and the second die by a fusion bonding layer.
Yu et al. teaches wherein (Fig. 16), further comprising:
a support substrate (66B package component, para [0032]) disposed over the first RDL (see the annotated figure below) and the second RDL (see the annotated figure below), wherein the support substrate (66B) is connected to the first die (100B) and the second die (100C) by a fusion bonding layer (para [0032]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Yu et al., and modify the structure of Chen et al., by aligning the package component on both of the substrates, in order to minimize the voltage drop caused by the resistance of the metal lines (para [0033]).
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Regarding claim 8, Chen et al. teaches all of the limitations of claim 1 from which this claim depends.
Chen et al. is explicitly silent of disclosing wherein, further comprising:
a fourth RDL disposed over the first RDL and the second RDL, wherein the fourth RDL is connected to the first die and the second die by a hybrid bonding layer.
Yu et al. teaches wherein (Fig. 16), further comprising:
a fourth RDL (see the annotated figure in claim 7) disposed over the first RDL (see the annotated figure in claim 7) and the second RDL (see the annotated figure in claim 7), wherein the fourth RDL is connected to the first die (100B) and the second die (100C) by a hybrid bonding layer (para [0032]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Yu et al., and modify the structure of Chen et al., by aligning the package component along with the redistribution layer on the substrates, in order to minimize the voltage drop caused by the resistance of the metal lines (para [0033]), and regulate the voltage supplies for package components.
Regarding claim 9, Chen et al. and Yu et al. teach all of the limitations of claim 7 from which this claim depends.
Chen et al. is explicitly silent of disclosing wherein, further comprising:
the support substrate disposed over the fourth RDL opposite to the third RDL, wherein the fourth RDL is connected to the support substrate by a fusion bonding layer.
Yu et al. teaches wherein (Fig. 16), further comprising:
the support substrate (66B) disposed over the fourth RDL (see the annotated figure in claim 7) opposite to the third RDL (see the annotated figure in claim 7), wherein the fourth RDL is connected to the support substrate (66B) by a fusion bonding layer (para [0032]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Yu et al., and modify the structure of Chen et al., by aligning the package component on both of the substrates, in order to minimize the voltage drop caused by the resistance of the metal lines (para [0033]), and regulate the voltage supplies for package components.
Regarding claim 10, Chen et al. and Yu et al. teach all of the limitations of claim 7 from which this claim depends.
Chen et al. is explicitly silent of disclosing wherein, further comprising:
a semiconductor substrate disposed over the fourth RDL opposite to the third RDL, wherein the semiconductor substrate includes a third active area at a front surface facing the fourth RDL.
Yu et al. teaches wherein (Fig. 16), further comprising:
a semiconductor substrate (66A) disposed over the fourth RDL (see figure in claim 7) opposite to the third RDL, wherein the semiconductor substrate (66A) includes a third active area at a front surface facing the fourth RDL.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Yu et al., and modify the structure of Chen et al., by aligning the package component on the substrate, in order to minimize the voltage drop caused by the resistance of the metal lines (para [0033]).
Regarding claim 11, Chen et al. and Yu et al. teach all of the limitations of claim 9 from which this claim depends.
The combination of Chen et al. and Yu et al. teaches, further comprising:
a through molding via (TMV) (TIV, see Fig. 4, Chen et al.) penetrating the molding material (E1), wherein the TMV (TIV) electrically connects the third RDL (RDL1) to the fourth RDL (see figure in claim 7, Yu et al.) for providing a power supply from the third RDL to the semiconductor substrate.
Allowable Subject Matter
15. Claims 14-20 are allowed.
16. The following is an examiner’s statement of reasons for allowance:
Claim 14: the prior art of record alone or in combination neither teaches nor makes obvious a method for manufacturing a semiconductor structure, comprising:
….
reducing a thickness of the first substrate from a back surface of the first substrate until an exposure of the etch stop layer occurs;
Claims 5, 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 5 recites ….the second die is one of a plurality of processor dies configured to transmit or process a die-to-die signal between the processor dies through the second BSTV, wherein the second BSTV is in a peripheral region of the second die.
Claim 12 recites….the first die further comprises a first power rail disposed in the first substrate, and the first BSTV contacts a bottom of the first power rail; and the second die further comprises a second power rail disposed in the second substrate, and the second BSTV contacts a bottom of the second power rail.
17. Prior arts made of record in PTO-892 and not relied upon are considered pertinent to applicant’s disclosure: the prior arts, Chen et al. (US 2019/0131273 A1) and Yu et al. (US 2017/0263518 A1) hereby are cited as close prior arts, disclose the semiconductor structure comprising the multiple dies including substrates wherein the through-via penetrating from the bottom surface of the substrates, and redistribution layers deposited on the bottom and top surfaces of the multiple dies, but fail to disclose the claim languages stated in the section 16, therefore, by itself or in combination or with other prior arts does not disclose the limitations as stated in the section 16.
Examiner’s Note
18. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
19. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
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20. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812