Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to Applicant’s Amendment and Request for Reconsideration filed May 29, 2026. Claim 1 has been amended. Claim 7 and 8 have been canceled.
Claims 1-6 and 9-20 are pending with claims 10-20 currently withdrawn from consideration.
Response to Amendment
The amendments to the Claims filed May 29, 2026 have been entered. Applicant’s amendments to the claims have failed to overcome each and every rejection set forth in the Non-Final Office Action filed March 25, 2026.
Response to Arguments
Applicant's arguments filed May 29, 2026 have been fully considered but they are not persuasive.
Applicant argues on pages 9-10 that “Tsutsumi fails to disclose or teach the feature ‘the first isolation structures are respectively aligned with the second isolation structures and separated from the second isolation structures by at least one conductive layer’ in the amended claim 1.”
This argument is not persuasive because, as explained in the previous Office Action, Tsutsumi discloses the first isolation structures are respectively aligned with the second isolation structures (Tsutsumi, FIG. 14A, 14B, upper portion of backside trench fill structure 76 [the second isolation structures] shown disposed over and aligned with lower portion of backside trench fill structure 76 [the first isolation structures]).
As Applicant notes on page 9, Tsutsumi is silent regarding at least one conductive layer separating the first isolation structure from the second isolation structures. However, as explained in the previous Office Action, because Applicant’s specification provides no evidence of unexpected results, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Tsutsumi and Ku to the knowledge generally available to one of ordinary skill in the art in order to arrive at Applicant’s claimed structural arrangement, wherein the first isolation structures are separated from the second isolation structures by at least one conductive layer because a person having ordinary skill would have recognized the finite number of predictable solutions, i.e. no separation between the first and second isolation structures; separation by means of an insulating layer; or separation by means of a conductive layer, and would have pursued the known options with a reasonable expectation of success. The motivation for doing so would be to simplify manufacturing, thereby reducing costs while improving device performance and reliability.
On page 10, Applicant contends that “the above-mentioned feature has unexpected effects,” and refers to paragraph [0040] of the present application for support. However, Applicant has not provided any evidence indicating that this feature is critical or produces any unexpected results; the referenced text of the application states only “By such configuration, the operations of different blocks BKJ and BK2 (as shown in FIG. 7B) are not interfered with each other, so as to effectively improve the performance of the memory device”. Applicant’s specification does not indicate that either the reduced interference or the improved performance are unexpected and unobvious. The evidence relied upon by Applicant in rebutting a prima facie case of obviousness should establish "that the differences in results are in fact unexpected and unobvious and of both statistical and practical significance." Ex parte Gelles, 22 USPQ2d 1318, 1319 (Bd. Pat. App. & Inter. 1992). See MPEP 716.02.
In response to Applicant’s argument on pages 10-11 that the dependent claims are patentably distinct over the prior art, and are also allowable based at least on their dependency from independent claim 1, as amended, see the rejections of the claims below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Tsutsumi et al., US 2022/0157842 A1 (hereinafter Tsutsumi) in view of Ku et al., US 2018/0358375 A1 (hereinafter Ku).
Regarding claim 1, as amended, Tsutsumi discloses: A memory device, comprising: a laminated layer (Tsutsumi, FIG. 10A, first tier structure (132, 142, 170, 165), [0082-0089]), disposed on a substrate (Tsutsumi, FIG. 10A, substrate 8, [0080]); a stacked structure, disposed on the laminated layer (Tsutsumi, FIG. 10A, second tier structure (232, 242, 270, 265), [0102-0115]); a plurality of vertical channel pillars (Tsutsumi, FIGs. 10A, 10B, vertical semiconductor channels 60, [0142]), penetrating through the stacked structure and the laminated layer (Tsutsumi, FIG. 10A shows vertical semiconductor channels 60 [the plurality of vertical channel pillars] penetrating through the second tier structure (232, 242, 270, 265) [the stacked structure] and the first tier structure (132, 142, 170, 165) [the laminated layer]); a plurality of first isolation structures, disposed aside the plurality of vertical channel pillars and penetrating through a lower part of the stacked structure (Tsutsumi, FIG. 14A, 14B, lower portion of backside trench fill structure 76 shown disposed aside vertical semiconductor channels 60 [the plurality of vertical channel pillars] and penetrating through first tier structure (132, 142, 170, 165) [the laminated layer] and through lower part of second tier structure (232, 242, 270, 265) [the lower part of the stacked structure], [0161]); a plurality of second isolation structures, respectively disposed over the plurality of first isolation structures and penetrating through an upper part of the stacked structure (Tsutsumi, FIG. 14A, 14B, upper portion of backside trench fill structure 76 shown disposed over lower portion of backside trench fill structure 76 [the plurality of first isolation structures] and penetrating through upper part of second tier structure (232, 242, 270, 265) [the upper part of the stacked structure], [0161]); and a plurality of common source lines (Tsutsumi, continuous metallic material layer (not shown), formed on sidewalls of backside trenches 79, [0156]), disposed aside the plurality of vertical channel pillars and penetrating through the stacked structure and a part of the laminated layer (Tsutsumi, FIGs. 14A, 14B, backside trenches 79 [including continuous metallic material layer, i.e., the common source line] shown disposed aside the plurality of vertical semiconductor channels 60 [the plurality of vertical channel pillars] and penetrating through the second tier structure (232, 242, 270, 265) [the stacked structure] and the first tier structure (132, 142, 170, 165) [the laminated layer]), wherein from a top view, the plurality of common source lines extend in a first direction (Tsutsumi, FIG. 14B is a top view showing backside trenches 79 [including continuous metallic material layer, i.e., the common source line] extending along the hd1 axis [the first direction]), and (Tsutsumi, FIG. 10A, second tier structure (232, 242, 270, 265), [0102-0115]) comprises a plurality of insulating layers (Tsutsumi, FIG. 10A, insulating layers 232, insulating material, [0104]) and a plurality of conductive layers (Tsutsumi, FIG. 10A, material layers 242, a conductive material, [0104]) stacked alternately (Tsutsumi, see FIG. 10A, [0102]), wherein in a third direction (Tsutsumi, FIG. 14A shows the third direction as the z-axis, extending upwards from the bottom of the page), the first isolation structures are respectively aligned with the second isolation structures (Tsutsumi, FIG. 14A, 14B, upper portion of backside trench fill structure 76 [the second isolation structures] shown disposed over and aligned with lower portion of backside trench fill structure 76 [the first isolation structures]) (Tsutsumi, FIGs. 14A, 14B, show the third direction as the z-axis, perpendicular to the hd1 direction [the first direction]).
Tsutsumi is silent regarding: each of the first isolation structures and the second isolation structures has, in the first direction, two wide end portions respectively adjacent to two of the common source lines.
However, Ku, in the same field of endeavor, teaches that an insulating spacer having two wide end portions is advantageous in order to avoid defects that may occur between the source patterns during processing (Ku, see FIG. 8B, insulating spacer 164, analogous to the first and second isolation structures, having two wide end portions, [0134]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ku with the teachings of Tsutsumi, arriving at Applicant’s claimed each of the first isolation structures and the second isolation structures has, in the first direction, two wide end portions respectively adjacent to two of the common source lines with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Ku, to avoid defects that may occur between the source patterns, thereby increasing manufacturing yield while improving device performance and reliability.
Tsutsumi is silent regarding: the first isolation structures are separated from the second isolation structures by at least one conductive layer. However, because Applicant’s specification provides no evidence of unexpected results, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Tsutsumi and Ku to the knowledge generally available to one of ordinary skill in the art in order to arrive at Applicant’s claimed structural arrangement because a person having ordinary skill would have recognized the finite number of predictable solutions, i.e. no separation between the first and second isolation structures, separation by means of an insulating layer, or separation by means of a conductive layer, and would have pursued the known options with a reasonable expectation of success. The motivation for doing so would be to simplify manufacturing, thereby reducing costs while improving device performance and reliability.
Regarding claim 2, Tsutsumi in view of Ku teaches: The memory device of claim 1, wherein from the top view, the second isolation structures (Tsutsumi, FIG. 14A, 14B, upper portion of backside trench fill structure 76) are respectively overlapped with the first isolation structures (Tsutsumi, FIG. 14A, 14B, lower portion of backside trench fill structure 76), and the second isolation structures are respectively located within boundaries of the first isolation structures (Tsutsumi, FIG. 14B shows a top view of upper and lower portions of backside trench fill structures 76 overlap, i.e., the second isolation structures are respectively located within boundaries of the first isolation structures).
Regarding claim 3, Tsutsumi in view of Ku teaches: The memory device of claim 1, wherein from the top view, each of the first isolation structures and the second isolation structures (Ku, FIG. 8B, insulating spacers 164) further has, in the first direction (Ku, FIG. 8B, the first direction is shown as the x direction), a narrow center portion between the two wide end portions (Ku, FIG. 8B shows insulating spacer 164 having a narrow center portion between the two wide end portions, size indicated by Wa1), and wherein a size of the wide end portions in a second direction (Ku, FIG. 8B, the second direction is shown as the y direction) is greater than a size of the narrow center portion in the second direction (Ku, FIG. 8B shows increased width Wa2 and Wa3 [the size of the wide end portions in the second direction] is greater than Wa1 [the size of the narrow center portion in the second direction, [0109]), and the second direction is perpendicular to the first direction (Ku, FIG. 8B shows the y direction [the second direction] is perpendicular to the x direction [the first direction]).
Regarding claim 4, Tsutsumi in view of Ku teaches nearly every element of claim 4 but does not explicitly teach: wherein the size of the wide end portions of the first isolation structures in the second direction is greater than the size of the wide end portions of the second isolation structures in the second direction. However, because Ku, FIG. 8B and associated text teaches that the dimensions of the wide end portions of isolation structures can be optimized to minimize processing defects, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Ku to the teachings of Tsutsumi with predictable results and without undue experimentation. The motivation for doing so would be, as expressly stated by Ku, to increase yield and productivity of semiconductor devices.
Regarding claim 5, Tsutsumi in view of Ku teaches nearly every element of claim 5 but is silent regarding: wherein the size of the narrow center portions of the first isolation structures in the second direction is greater than the size of the narrow center portions of the second isolation structures in the second direction (Ku, FIG. 8B shows width Wb1 [the size of the narrow center portions of the first isolation structures in the second direction] is greater than Wa1 [the size of the narrow center portions of the second isolation structures in the second direction], “the width Wb1 may be greater than the width Wa1,” [0101]).
Regarding claim 6, Tsutsumi in view of Ku teaches: The memory device of claim 3, wherein from the top view (Ku, FIG. 8B shows a top view), each of the narrow center portions has a substantially fixed width (Ku, FIG. 8B shows the width of each of the narrow center portions as Wa1, Wb1, a substantially fixed width), and each of the wide end portions has a varied width (Ku, FIG. 8B shows width of wide end portions varies with position along the x-axis, i.e., each of the wide end portions has a varied width, “the width of the flared region [the wide end portion] may increase [i.e., vary] toward the point of the maximum width Wb2/Wa2,” [0095]).
Regarding claim 9, Tsutsumi in view of Ku teaches nearly every element of claim 9 but is silent regarding: wherein the wide end portions of the first isolation structures and the second isolation structures have enclosed voids therein. However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Tsutsumi and Ku to the knowledge generally available to one of ordinary skill in the art in order to arrive at Applicant’s claimed structural arrangement because a person having ordinary skill would have recognized the finite number of predictable solutions, i.e. voids or no voids, and would have pursued the known options with a reasonable expectation of success. The motivation for doing so would be to simplify manufacturing, thereby reducing costs while improving device performance and reliability.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEREK NIELSEN whose telephone number is (703)756-1266. The examiner can normally be reached Monday - Friday, 8:30 A.M. - 5:30 P.M..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRENT A FAIRBANKS can be reached at (408)918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.L.N./Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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