DETAILED ACTION
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 18 and 20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Liu et al. (US 2020/0411611 A1; hereinafter “Liu”).
In regard to claim 1, Liu teaches a display panel (a display panel comprises any one of the array substrates) (paragraph 16), comprising:
a substrate (an array substrate 100) (Fig. 1A and paragraph 47);
an active layer, disposed on one side of the substrate (an active layer 9 is disposed on the topside of the array substrate 100 as shown in Fig. 4) (Fig. 4 and paragraph 58); and
a plurality of sub-pixels (the array substrate comprises a plurality of pixel units) (paragraph 4), a plurality of first scanning lines (a gate line connected to the gate electrodes 7 of the first and third transistors T1 and T3) and a plurality of first signal lines (a plurality of first wires 1 and data lines 6) (Fig. 1D, Fig. 1F, Fig. 2 and paragraphs 46, 58 and 65), each of the plurality of first scanning lines extending along a first direction (a gate line connected to the gate electrodes 7 are shown extending in the lateral direction in Fig. 1D), each of the plurality of first signal lines extending along a second direction (the plurality of first wires 1 extends along a vertical direction as shown in Fig. 2), and the first direction and the second direction intersecting with each other (the lateral and vertical directions are known to intersect one another);
wherein each of the plurality of sub-pixels comprises a pixel circuit (a pixel circuit of the sub-pixel unit as shown in Fig. 5) and a light emitting element (a light emitting element is in each of the plurality of sub-pixel units) (paragraph 20), the pixel circuit comprises a first transistor (a second transistor T2) and a second transistor (a first transistor T1) (Fig. 1C and paragraph 59), a gate of the first transistor is electrically connected to a corresponding first scanning line (the whole of the gate line and the gate electrode that are integral with each other) (paragraph 58), a first electrode of the first transistor (a first electrode of a second transistor T2) is electrically connected to a corresponding first signal line (the first electrode of the second transistor T2 is connected to the data line (a data signal terminal Vdata)) (paragraphs 77), a second electrode of the first transistor is electrically connected to a first electrode of the second transistor through a first connecting portion (a second electrode of the second transistor T2 and the first electrode of the first transistor T1 is connected to the second node N2 through the data connection line 30) (Fig. 5 and paragraphs 66 and 76-77), and a second electrode of the second transistor is electrically connected to the light emitting element (the first transistor T1 is connected to the light emitting element L1 as shown in Fig. 5); and
wherein the first connecting portion is disposed on one side of the active layer away from the substrate (the data connection line 30 is shown above the active layer 9 on the first metal layer) (Fig. 8D and paragraph 129).
In regard to claim 2, Liu teaches a plurality of light-emitting control lines (a plurality of auxiliary wires 4) extending along the first direction (the plurality of auxiliary wires 4 are shown extending in the lateral direction in Fig. 1E) (Fig. 1E and paragraph 51);
a plurality of first supply voltage lines (a plurality of first sub-wires 11) extending along the second direction (the plurality of first sub-wires 11 are shown in the vertical direction in Fig. 2);
wherein the pixel circuit further comprises a third transistor (a fourth transistor T4) and a fourth transistor (a fifth transistor T5) (a fourth and fifth transistor T4 and T5 are shown in Fig. 5) (Fig. 5 and paragraph 59), a first electrode of the third transistor is electrically connected to a corresponding first supply voltage line (the first wires 1 are configured to supply a power signal to the light emitting element such as a high voltage power signal (VDD signal) which is connected to the first electrode of the fourth transistor T4) (Fig. 5 and paragraphs 46 and 79), a second electrode of the third transistor is electrically connected to the first electrode of the second transistor (the second electrode of the fourth transistor is connected to the first electrode of the second transistor T2 through the second node N2 as shown in Fig. 5), a first electrode of the fourth transistor is electrically connected to the second electrode of the second transistor (the first electrode of the fifth transistor T5 is connected to the second electrode of the first transistor T1 through the third node N3) (Fig. 5 and paragraphs 76 and 81) , a second electrode of the fourth transistor is electrically connected to the light emitting element (a second electrode of the fifth transistor T5 is connected to the first terminal (the fourth node N4) of the light emitting element L1) (Fig. 5 and paragraph 81), and a gate of the third transistor and a gate of the fourth transistor each is electrically connected to a corresponding light emitting control line (the gate of the fourth and fifth transistor T4 and T5 are shown connected to the first and second light emission control terminals EM1 and EM2) (Fig. 5 and paragraphs 110); and
wherein the first connecting portion is at least partially overlapped with the plurality of light-emitting control lines in a direction perpendicular to a plane in which the substrate is located (the data connection line 30 is shown overlapping the auxiliary wires 4 in Fig. 1B).
In regard to claim 3, Liu teaches wherein the plurality of light-emitting control lines are disposed in a first metal layer (a first metal layer is formed, and then a patterning process is performed on the first metal layer to form the plurality of auxiliary wires 4 ) Fig. 8C and paragraph 128), the first connecting portion is disposed in a second metal layer (the data connection line 30 is shown in a second metal layer in Fig. 4) (Fig. 4, Fig. 8D and paragraph 129), and the second metal layer is disposed on one side of the first metal layer away from the substrate (the metal layer of the data connection line 30 is shown above the metal layer of the auxiliary wires 4 in Fig. 4).
In regard to claim 4, Liu teaches further comprising: a plurality of second scanning lines (the gate lines connected to the gate electrodes 7 of the fifth transistor T5) and a plurality of reference voltage lines (lines that function as reset voltage lines) (Fig. 5 and paragraph 74), wherein each of the plurality of second scanning lines extends along the first direction (the plurality of first wires 1 are configured to supply power signals are shown only extending in the vertical direction) (Fig. 2), and each of the plurality of reference voltage lines extends along the first direction (the gate line connected to the gate electrodes 7 are shown only extending in the lateral direction) (Fig. 1D);
wherein the pixel circuit further comprises a fifth transistor (a seventh transistor T7), a gate of the fifth transistor (a gate of the seventh transistor T7) is electrically connected to a corresponding second scanning line (A gate electrode of the seventh transistor T7 is also connected to the second scan line (the reset control terminal Rst) (Fig. 5 and paragraph 82), a first electrode of the fifth transistor is electrically connected to a corresponding reference voltage line (a first electrode of the seventh transistor T7 is connected to the reset voltage terminal Vinit) (paragraph 82), and a second electrode of the fifth transistor is electrically connected to a gate of the second transistor (a second electrode of the seventh transistor T7 is connected to the gate electrode of the first transistor T1) (Fig. 5 and paragraph 82); and
wherein the pixel circuit further comprises a sixth transistor (a third transistor T3) (Fig. 5 and paragraph 59), a gate of the sixth transistor is electrically connected to a corresponding first scanning line (as shown in Fig. 1B the gate line 7 of the first transistor is shown to be the same for the third transistor T3), a first electrode of the sixth transistor is electrically connected to a corresponding reference voltage line (the first electrode of the third transistor T3 is shown to be electrically connected to the reset voltage terminal Vinit in Fig. 5), and a second electrode of the sixth transistor is electrically connected to the light emitting element (the second electrode of the third transistor T3 is shown to be electrically connected to the light emitting element L1 in Fig. 5).
In regard to claim 18, Liu teaches a plurality of third scanning lines extending along the first direction (the gate lines connected to the gate electrodes 7 of the seventh transistor T7) (Fig. 5 and paragraphs 58-59);
wherein the pixel circuit further comprises a seventh transistor (the seventh thin-film transistor T7) (paragraph 59), a gate of the seventh transistor is electrically connected to a corresponding third scanning line (the gate lines connected to the gate electrodes 7 of the seventh transistor T7 functions as the third scanning line) (Fig. 1B and Fig. 5), a first electrode of the seventh transistor is electrically connected to the second electrode of the second transistor, and a second electrode of the seventh transistor is electrically connected to a gate of the second transistor (as shown in Fig. 5 both the first and second electrodes of the seventh transistor T7 are electrically connected to the second electrode and gate of the first transistor T1).
In regard to claim 20, Liu teaches a display device (a fingerprint recognition device) (paragraph 17), comprising (a display panel comprises any one of the array substrates) (paragraph 16), wherein the display panel comprises:
a substrate (an array substrate 100) (Fig. 1A and paragraph 47);
an active layer, disposed on one side of the substrate (an active layer 9 is disposed on the topside of the array substrate 100 as shown in Fig. 4) (Fig. 4 and paragraph 58); and
a plurality of sub-pixels (the array substrate comprises a plurality of pixel units) (paragraph 4), a plurality of first scanning lines (a gate line connected to the gate electrodes 7 of the first and third transistors T1 and T3) and a plurality of first signal lines (a plurality of first wires 1 and data lines 6) (Fig. 1D, Fig. 1F, Fig. 2 and paragraphs 46, 58 and 65), each of the plurality of first scanning lines extending along a first direction (a gate line connected to the gate electrodes 7 are shown extending in the lateral direction in Fig. 1D), each of the plurality of first signal lines extending along a second direction (the plurality of first wires 1 extends along a vertical direction as shown in Fig. 2), and the first direction and the second direction intersecting with each other (the lateral and vertical directions are known to intersect one another);
wherein each of the plurality of sub-pixels comprises a pixel circuit (a pixel circuit of the sub-pixel unit as shown in Fig. 5) and a light emitting element (a light emitting element is in each of the plurality of sub-pixel units) (paragraph 20), the pixel circuit comprises a first transistor (a second transistor T2) and a second transistor (a first transistor T1) (Fig. 1C and paragraph 59), a gate of the first transistor is electrically connected to a corresponding first scanning line (the whole of the gate line and the gate electrode that are integral with each other) (paragraph 58), a first electrode of the first transistor (a first electrode of a second transistor T2) is electrically connected to a corresponding first signal line (the first electrode of the second transistor T2 is connected to the data line (a data signal terminal Vdata)) (paragraphs 77), a second electrode of the first transistor is electrically connected to a first electrode of the second transistor through a first connecting portion (a second electrode of the second transistor T2 and the first electrode of the first transistor T1 is connected to the second node N2 through the data connection line 30) (Fig. 5 and paragraphs 66 and 76-77), and a second electrode of the second transistor is electrically connected to the light emitting element (the first transistor T1 is connected to the light emitting element L1 as shown in Fig. 5); and
wherein the first connecting portion is disposed on one side of the active layer away from the substrate (the data connection line 30 is shown above the active layer 9 on the first metal layer) (Fig. 8D and paragraph 129).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claim 4 or 18 above, in view of Choi et al. (US 2020/0176545 A1; hereinafter “Choi”).
In regard to claim 5, Liu doesn’t explicitly teach wherein the fifth transistor comprises a first sub-transistor and a second sub-transistor; wherein a first electrode of the first sub-transistor is the first electrode of the fifth transistor, a second electrode of the first sub-transistor is electrically connected to a first electrode of the second sub-transistor, and a second electrode of the second sub-transistor is the second electrode of the fifth transistor; wherein the active layer comprises a first sub-channel region, a second sub-channel region and a first sub-connecting region, and the first sub-channel region and the second sub-channel region are connected by the first sub-connecting region; and wherein in a direction perpendicular to a plane in which the substrate is located, the first sub-channel region is at least partially overlapped with a gate of the first sub-transistor, the second sub-channel region is at least partially overlapped with a gate of the second sub-transistor, and the first sub-connecting region is at least partially overlapped with the plurality of reference voltage lines.
Choi teaches a display panel (an organic light emitting display) (paragraph 4), wherein a fifth transistor (a third transistor T3) comprises a first sub-transistor and a second sub-transistor (the third transistor T3 may include a 3ath transistor T3a and a 3bth transistor T3b) (Fig. 10 and paragraph 140); wherein a first electrode of the first sub-transistor is a first electrode of the fifth transistor (the 3ath source electrode SE3a and the 3bth source electrode SE3b are referred to as the third source electrode SE3) (paragraph 140), a second electrode of the first sub-transistor (a 3ath drain electrode DE3a) is electrically connected to a first electrode (a 3bth source electrode SE3b) of the second sub-transistor (drain electrode DE3a is shown connected to the 3bth source electrode SE3b in Fig. 10), and a second electrode of the second sub-transistor (a 3bth drain electrode DE3b) is the second electrode of the fifth transistor (the 3ath drain electrode DE3a and the 3bth drain electrode DE3b are referred to as the third drain electrode DE3) (Fig. 10 and paragraph 140); wherein the active layer comprises a first sub-channel region (a region containing 3ath active pattern ACT3a) (Fig. 10), a second sub-channel region (3bth active pattern ACT3b) and a first sub-connecting region (a region between the 3ath active pattern ACT3a and the 3bth active pattern ACT3b as shown in Fig. 10), and the first sub-channel region and the second sub-channel region are connected by the first sub-connecting region (the region between the 3ath active pattern ACT3a and the 3bth active pattern ACT3b is shown connecting them in Fig. 10); and wherein in a direction perpendicular to a plane in which the substrate is located, the first sub-channel region is at least partially overlapped with a gate of the first sub-transistor (the 3ath active pattern ACT3a is shown overlapping a 3ath gate electrode GE3a in Fig. 8) (Fig. 8 and paragraph 140), the second sub-channel region is at least partially overlapped with a gate of the second sub-transistor (the 3bth active pattern ACT3b is shown overlapping a 3bth gate electrode GE3b in Fig. 9) (Fig. 9 and paragraph 140), and the first sub-connecting region is at least partially overlapped with a plurality of reference voltage lines (an initialization power line IPL is shown overlapping the region connecting the 3ath active pattern ACT3a and the 3bth active pattern ACT3b) (Fig. 8, Fig. 9 and Fig. 10).
It would be obvious to one skilled in the art to combine the teachings of Liu with the teachings of Choi to have the fifth transistor comprises a first sub-transistor and a second sub-transistor; wherein a first electrode of the first sub-transistor is the first electrode of the fifth transistor, a second electrode of the first sub-transistor is electrically connected to a first electrode of the second sub-transistor, and a second electrode of the second sub-transistor is the second electrode of the fifth transistor; wherein the active layer comprises a first sub-channel region, a second sub-channel region and a first sub-connecting region, and the first sub-channel region and the second sub-channel region are connected by the first sub-connecting region; and wherein in a direction perpendicular to a plane in which the substrate is located, the first sub-channel region is at least partially overlapped with a gate of the first sub-transistor, the second sub-channel region is at least partially overlapped with a gate of the second sub-transistor, and the first sub-connecting region is at least partially overlapped with the plurality of reference voltage lines since this allows for a double gate structure to prevent or substantially prevent a leakage current as taught by Choi (paragraph 140).
In regard to claim 19, Liu doesn’t explicitly teach wherein the seventh transistor comprises a third sub-transistor and a fourth sub-transistor; wherein a first electrode of the third sub-transistor is the first electrode of the seventh transistor, a second electrode of the third sub-transistor is electrically connected to a first electrode of the fourth sub-transistor, and a second electrode of the fourth sub-transistor is the second electrode of the seventh transistor; wherein the active layer comprises a third sub-channel region, a fourth sub-channel region and a second sub-connecting region, and the third sub-channel region and the fourth sub-channel region are connected through the second sub-connecting region; wherein the pixel circuit further comprising a second shielding layer; wherein in a direction perpendicular to a plane in which the substrate is located, the third sub-channel region is at least partially overlapped with a gate of the third sub-transistor, the fourth sub-channel region is at least partially overlapped with a gate of the fourth sub-transistor, and the second sub-connecting region is at least partially overlapped with the second shielding layer.
Choi teaches a display panel (an organic light emitting display) (paragraph 4), wherein a seventh transistor (a third transistor T3) comprises a third sub-transistor and a fourth sub-transistor (the third transistor T3 may include a 3ath transistor T3a and a 3bth transistor T3b) (Fig. 10 and paragraph 140); wherein a first electrode of the third sub-transistor is the first electrode of the seventh transistor (the 3ath source electrode SE3a and the 3bth source electrode SE3b are referred to as the third source electrode SE3) (paragraph 140), a second electrode of the third sub-transistor (a 3ath drain electrode DE3a) is electrically connected to a first electrode (a 3bth source electrode SE3b) of the fourth sub-transistor (drain electrode DE3a is shown connected to the 3bth source electrode SE3b in Fig. 10), and a second electrode of the fourth sub-transistor (a 3bth drain electrode DE3b) is the second electrode of the seventh transistor (the 3ath drain electrode DE3a and the 3bth drain electrode DE3b are referred to as the third drain electrode DE3) (Fig. 10 and paragraph 140); wherein the active layer comprises a third sub-channel region (a region containing 3ath active pattern ACT3a) (Fig. 10), a fourth sub-channel region (3bth active pattern ACT3b) and a second sub-connecting region (a region between the 3ath active pattern ACT3a and the 3bth active pattern ACT3b as shown in Fig. 10), and the third sub-channel region and the fourth sub-channel region are connected through the second sub-connecting region (the region between the 3ath active pattern ACT3a and the 3bth active pattern ACT3b is shown connecting them in Fig. 10); wherein the pixel circuit further comprising a second shielding layer (a second power supply line PL2 can function as a shielding layer) (Fig. 9 and paragraph 182); wherein in a direction perpendicular to a plane in which the substrate is located, the third sub-channel region is at least partially overlapped with a gate of the third sub-transistor (the 3ath active pattern ACT3a is shown overlapping a 3ath gate electrode GE3a in Fig. 8) (Fig. 8 and paragraph 140), the fourth sub-channel region is at least partially overlapped with a gate of the fourth sub-transistor (the 3bth active pattern ACT3b is shown overlapping a 3bth gate electrode GE3b in Fig. 9) (Fig. 9 and paragraph 140), and the second sub-connecting region is at least partially overlapped with the second shielding layer (the power supply line PL2 is shown overlapping the region between the 3ath active pattern ACT3a and the 3bth active pattern ACT3b) (Fig. 8, Fig. 9).
It would be obvious to one skilled in the art to combine the teachings of Liu with the teachings of Choi to have the seventh transistor comprises a third sub-transistor and a fourth sub-transistor; wherein a first electrode of the third sub-transistor is the first electrode of the seventh transistor, a second electrode of the third sub-transistor is electrically connected to a first electrode of the fourth sub-transistor, and a second electrode of the fourth sub-transistor is the second electrode of the seventh transistor; wherein the active layer comprises a third sub-channel region, a fourth sub-channel region and a second sub-connecting region, and the third sub-channel region and the fourth sub-channel region are connected through the second sub-connecting region; wherein the pixel circuit further comprising a second shielding layer; wherein in a direction perpendicular to a plane in which the substrate is located, the third sub-channel region is at least partially overlapped with a gate of the third sub-transistor, the fourth sub-channel region is at least partially overlapped with a gate of the fourth sub-transistor, and the second sub-connecting region is at least partially overlapped with the second shielding layer since this allows for a double gate structure to prevent or substantially prevent a leakage current as taught by Choi (paragraph 140).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claim 4 above, in view of Guo (US 2025/0316225 A1).
In regard to claim 6, Liu teaches a plurality of second scanning lines (a gate line connected to the gate electrodes 7 of the fifth transistor T5), a plurality of first reference voltage lines (a gate line connected to the gate electrodes 7 that functions as the reset voltage terminal Vinit) (Fig. 4 and paragraph 74).
However, Liu fails to teach a plurality of second reference voltage lines; wherein the plurality of second scanning lines, the plurality of first reference voltage lines, and the plurality of second reference voltage lines each extends along the first direction; wherein the pixel circuit further comprises a fifth transistor, a gate of the fifth transistor is electrically connected to a corresponding second scanning line, a first electrode of the fifth transistor is electrically connected to a corresponding first reference voltage line, and a second electrode of the fifth transistor is electrically connected to a gate of the second transistor; and wherein the pixel circuit further comprises a sixth transistor, a gate of the sixth transistor is electrically connected to a corresponding first scanning line, a first electrode of the sixth transistor is electrically connected to a corresponding second reference voltage line, and a second electrode of the sixth transistor is electrically connected to the light emitting element.
Guo teaches a display panel (an array substrate) (paragraph 13), comprising:
a plurality of second reference voltage lines (a respective reset signal line Vint (N+1) (Fig. 3A and paragraph 102); wherein a plurality of second scanning lines (a plurality of gate lines GL connected to the third transistor T3) (Fig. 3A and paragraph 109), a plurality of first reference voltage lines (a reset signal line VintN) (Fig. 3A and 109), and the plurality of second reference voltage lines each extends along the first direction (the reset signal line Vint (N+1), plurality of gate lines GL, and reset signal line VintN are shown extending in the lateral direction in Fig. 3A); wherein a pixel circuit further comprises a fifth transistor (a pixel circuit as shown in Fig. 2E contains a third transistor T3) (Fig. 2E and paragraph 93), a gate of the fifth transistor is electrically connected to a corresponding second scanning line (the gate of the third transistor T3 is shown electrically connected to gate line GL) (Fig. 2F and paragraph 110), a first electrode of the fifth transistor is electrically connected to a corresponding first reference voltage line (a first electrode of the third transistor T3 is shown electrically connected to reset signal line VintN in Fig. 2F), and a second electrode of the fifth transistor is electrically connected to a gate of a second transistor (the second electrode of the third transistor T3 is shown electrically connected to the gate of the seventh transistor T7 in Fig. 5); and wherein the pixel circuit further comprises a sixth transistor, a gate of the sixth transistor (a sixth transistor T6) is electrically connected to a corresponding first scanning line (the gate of the sixth transistor T6 is shown connected to reset control signal line rst(N+1)) (Fig. 3A and paragraph 159), a first electrode of the sixth transistor is electrically connected to a corresponding second reference voltage line (the sixth electrode is shown connected to the reset signal line Vint (N+1) in Fig. 2F), and a second electrode of the sixth transistor is electrically connected to the light emitting element (the second electrode of the sixth transistor T6, and the anode of the light emitting element LE) (Fig. 2F and paragraph 103).
It would’ve been obvious to one skilled in the art to combine the teachings of Liu with the teachings of Guo to have a plurality of second reference voltage lines; wherein the plurality of second scanning lines, the plurality of first reference voltage lines, and the plurality of second reference voltage lines each extends along the first direction; wherein the pixel circuit further comprises a fifth transistor, a gate of the fifth transistor is electrically connected to a corresponding second scanning line, a first electrode of the fifth transistor is electrically connected to a corresponding first reference voltage line, and a second electrode of the fifth transistor is electrically connected to a gate of the second transistor; and wherein the pixel circuit further comprises a sixth transistor, a gate of the sixth transistor is electrically connected to a corresponding first scanning line, a first electrode of the sixth transistor is electrically connected to a corresponding second reference voltage line, and a second electrode of the sixth transistor is electrically connected to the light emitting element since this allows for greater functionality of the device by allowing more connections to the transistors while applying appropriate voltages during operation as taught by Guo (paragraph 105).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Guo as applied to claim 6 above, in view of Choi.
In regard to claim 8, Liu in view of Guo don’t explicitly teach The display panel according to claim 46, wherein the fifth transistor comprises a first sub-transistor and a second sub-transistor; wherein a first electrode of the first sub-transistor is the first electrode of the fifth transistor, a second electrode of the first sub-transistor is electrically connected to a first electrode of the second sub-transistor, and a second electrode of the second sub-transistor is the second electrode of the fifth transistor; wherein the active layer comprises a first sub-channel region, a second sub-channel region and a first sub-connecting region, and the first sub-channel region and the second sub-channel region are connected through the first sub-connecting region; and wherein in a direction perpendicular to a plane in which the substrate is located, the first sub-channel region is at least partially overlapped with a gate of the first sub-transistor, the second sub-channel region is at least partially overlapped with a gate of the second sub-transistor, and the first sub-connecting region is at least partially overlapped with the plurality of second reference voltage lines.
Choi teaches a display panel (an organic light emitting display) (paragraph 4), wherein a fifth transistor (a third transistor T3) comprises a first sub-transistor and a second sub-transistor (the third transistor T3 may include a 3ath transistor T3a and a 3bth transistor T3b) (Fig. 10 and paragraph 140); wherein a first electrode of the first sub-transistor is a first electrode of the fifth transistor (the 3ath source electrode SE3a and the 3bth source electrode SE3b are referred to as the third source electrode SE3) (paragraph 140), a second electrode of the first sub-transistor (a 3ath drain electrode DE3a) is electrically connected to a first electrode (a 3bth source electrode SE3b) of the second sub-transistor (drain electrode DE3a is shown connected to the 3bth source electrode SE3b in Fig. 10), and a second electrode of the second sub-transistor (a 3bth drain electrode DE3b) is the second electrode of the fifth transistor (the 3ath drain electrode DE3a and the 3bth drain electrode DE3b are referred to as the third drain electrode DE3) (Fig. 10 and paragraph 140); wherein the active layer comprises a first sub-channel region (a region containing 3ath active pattern ACT3a) (Fig. 10), a second sub-channel region (3bth active pattern ACT3b) and a first sub-connecting region (a region between the 3ath active pattern ACT3a and the 3bth active pattern ACT3b as shown in Fig. 10), and the first sub-channel region and the second sub-channel region are connected through the first sub-connecting region (the region between the 3ath active pattern ACT3a and the 3bth active pattern ACT3b is shown connecting them in Fig. 10); and wherein in a direction perpendicular to a plane in which the substrate is located, the first sub-channel region is at least partially overlapped with a gate of the first sub-transistor (the 3ath active pattern ACT3a is shown overlapping a 3ath gate electrode GE3a in Fig. 8) (Fig. 8 and paragraph 140), the second sub-channel region is at least partially overlapped with a gate of the second sub-transistor (the 3bth active pattern ACT3b is shown overlapping a 3bth gate electrode GE3b in Fig. 9) (Fig. 9 and paragraph 140), and the first sub-connecting region is at least partially overlapped with a plurality of second reference voltage lines (an initialization power line IPL is shown overlapping the region connecting the 3ath active pattern ACT3a and the 3bth active pattern ACT3b) (Fig. 8, Fig. 9 and Fig. 10).
It would be obvious to one skilled in the art to combine the teachings of Liu with the teachings of Choi to have the fifth transistor comprises a first sub-transistor and a second sub-transistor; wherein a first electrode of the first sub-transistor is the first electrode of the fifth transistor, a second electrode of the first sub-transistor is electrically connected to a first electrode of the second sub-transistor, and a second electrode of the second sub-transistor is the second electrode of the fifth transistor; wherein the active layer comprises a first sub-channel region, a second sub-channel region and a first sub-connecting region, and the first sub-channel region and the second sub-channel region are connected through the first sub-connecting region; and wherein in a direction perpendicular to a plane in which the substrate is located, the first sub-channel region is at least partially overlapped with a gate of the first sub-transistor, the second sub-channel region is at least partially overlapped with a gate of the second sub-transistor, and the first sub-connecting region is at least partially overlapped with the plurality of second reference voltage lines since this allows for a double gate structure to prevent or substantially prevent a leakage current as taught by Choi (paragraph 140).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claim 1 above, in view of Wang (US 2022/0278183 A1).
In regard to claim 9, Liu teaches further comprising: a plurality of second scanning lines (a gate line connected to the gate electrodes 7 of the fifth transistor T5) and a plurality of reference voltage lines (lines that function as reset voltage lines) (Fig. 5 and paragraph 74), and each of the plurality of reference voltage lines extends along the first direction; wherein the pixel circuit further comprises a fifth transistor (the gate line connected to the gate electrodes 7 are shown only extending in the lateral direction) (Fig. 1D), a gate of the fifth transistor (a gate of the seventh transistor T7) is electrically connected to a corresponding second scanning line (A gate electrode of the seventh transistor T7 is also connected to the second scan line (the reset control terminal Rst) (Fig. 5 and paragraph 82), a first electrode of the fifth transistor is electrically connected to a corresponding reference voltage line (a first electrode of the seventh transistor T7 is connected to the reset voltage terminal Vinit) (paragraph 82), and a second electrode of the fifth transistor is electrically connected to a gate of the second transistor (a second electrode of the seventh transistor T7 is connected to the gate electrode of the first transistor T1) (Fig. 5 and paragraph 82); and wherein the pixel circuit further comprises a sixth transistor (a third transistor T3) (Fig. 5 and paragraph 59), a gate of the sixth transistor is electrically connected to a corresponding first scanning line (as shown in Fig. 1B the gate line 7 of the first transistor is shown to be the same for the third transistor T3), a first electrode of the sixth transistor is electrically connected to a corresponding reference voltage line (the first electrode of the third transistor T3 is shown to be electrically connected to the reset voltage terminal Vinit in Fig. 5), and a second electrode of the sixth transistor is electrically connected to the light emitting element (the second electrode of the third transistor T3 is shown to be electrically connected to the light emitting element L1 in Fig. 5).
However, Liu fail to teach wherein each of the plurality of second scanning lines extends along the first direction.
Wang teaches a display panel (paragraph 66), wherein each of a plurality of second scanning lines (a reset signal Vinit) extends along the first direction (the a reset signal Vinit is shown extending in the vertical direction in Fig. 6) (Fig. 6 and paragraph 93).
It would be obvious to one skilled in the art to combine the teachings of Liu with the teachings of Wang to have each of the plurality of second scanning lines extends along the first direction since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Wang as applied to claim 9 above, and further in view of Choi.
In regard to claim 10, Choi teaches a display panel (an organic light emitting display) (paragraph 4), wherein a fifth transistor (a third transistor T3) comprises a first sub-transistor and a second sub-transistor (the third transistor T3 may include a 3ath transistor T3a and a 3bth transistor T3b) (Fig. 10 and paragraph 140); wherein a first electrode of the first sub-transistor is a first electrode of the fifth transistor (the 3ath source electrode SE3a and the 3bth source electrode SE3b are referred to as the third source electrode SE3) (paragraph 140), a second electrode of the first sub-transistor (a 3ath drain electrode DE3a) is electrically connected to a first electrode (a 3bth source electrode SE3b) of the second sub-transistor (drain electrode DE3a is shown connected to the 3bth source electrode SE3b in Fig. 10), and a second electrode of the second sub-transistor (a 3bth drain electrode DE3b) is the second electrode of the fifth transistor (the 3ath drain electrode DE3a and the 3bth drain electrode DE3b are referred to as the third drain electrode DE3) (Fig. 10 and paragraph 140); wherein the active layer comprises a first sub-channel region (a region containing 3ath active pattern ACT3a) (Fig. 10), a second sub-channel region (3bth active pattern ACT3b) and a first sub-connecting region (a region between the 3ath active pattern ACT3a and the 3bth active pattern ACT3b as shown in Fig. 10), and the first sub-channel region and the second sub-channel region are connected by the first sub-connecting region (the region between the 3ath active pattern ACT3a and the 3bth active pattern ACT3b is shown connecting them in Fig. 10); wherein the pixel circuit further comprises a first shielding layer (a second power supply line PL2 can function as a shielding layer) (Fig. 9 and paragraph 182); and wherein in a direction perpendicular to a plane in which the substrate is located, the first sub-channel region is at least partially overlapped with a gate of the first sub-transistor (the 3ath active pattern ACT3a is shown overlapping a 3ath gate electrode GE3a in Fig. 8) (Fig. 8 and paragraph 140), the second sub-channel region is at least partially overlapped with a gate of the second sub-transistor (the 3bth active pattern ACT3b is shown overlapping a 3bth gate electrode GE3b in Fig. 9) (Fig. 9 and paragraph 140), and the first sub-connecting region is at least partially overlapped with the first shielding layer plurality of reference voltage lines (the power supply line PL2 is shown overlapping the region between the 3ath active pattern ACT3a and the 3bth active pattern ACT3b) (Fig. 8, Fig. 9).
It would be obvious to one skilled in the art to combine the teachings of Liu with the teachings of Choi to have the fifth transistor comprises a first sub-transistor and a second sub-transistor; wherein a first electrode of the first sub-transistor is the first electrode of the fifth transistor, a second electrode of the first sub-transistor is electrically connected to a first electrode of the second sub-transistor, and a second electrode of the second sub-transistor is the second electrode of the fifth transistor; wherein the active layer comprises a first sub-channel region, a second sub-channel region and a first sub-connecting region, and the first sub-channel region and the second sub-channel region are connected by the first sub-connecting region; wherein the pixel circuit further comprises a first shielding layer; and wherein in a direction perpendicular to a plane in which the substrate is located, the first sub-channel region is at least partially overlapped with a gate of the first sub-transistor, the second sub-channel region is at least partially overlapped with a gate of the second sub-transistor, and the first sub-connecting region is at least partially overlapped with the first shielding layer since this allows for a double gate structure to prevent or substantially prevent a leakage current as taught by Choi (paragraph 140).
In regard to claim 11, Liu in view of Wang and Choi teaches wherein the first shielding layer is electrically connected to a corresponding reference voltage line (the second power supply line PL2 is connected to the IPL through the first power supply line PL1) (Choi paragraphs 171 179 and 182); or a plurality of first supply voltage lines extends along the second direction, and the first shielding layer is electrically connected to a corresponding first supply voltage line.
Claims 12 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claim 1 above, and further in view of Cho et al. (US 2021/0257438 A1; hereinafter “Cho”).
In regard to claim 12, Liu doesn’t explicitly teach wherein a plurality of pixel circuits are arranged in an array along the first direction and the second direction, and a column of pixel circuits is electrically connected to at least one of the plurality of first signal lines; wherein the display panel further comprises a display region and a non-display region at least partially surrounding the display region; wherein the non-display region comprises a first fan-out region disposed on one side of the display region in the second direction, and the first fan-out region comprises a plurality of fan-out wirings; wherein the display region comprises a first display region and a second display region, the second display region is disposed on at least one side of the first display region in the first direction, the first display region and the second display region each comprises a plurality of first signal lines, the plurality of first signal lines are electrically connected to the plurality of fan-out wirings, and the plurality of first signal lines in the second display region are electrically connected to the plurality of fan-out wirings through connecting wirings; wherein the connecting wirings are disposed in the display region and each comprises a first connecting line segment extending along the first direction and a second connecting line segment extending along the second direction, the second connecting line segment is electrically connected to a signal corresponding fan-out wiring, and the first connecting line segment is electrically connected to a corresponding first signal line in the second display region.
Cho teaches a display panel (a display panel 10) (Fig. 1 and paragraph 72), wherein a plurality of pixel circuits are arranged in an array along the first direction and the second direction (each pixel PX may be driven by a pixel circuit and are shown arranged in an array in Fig. 3) (Fig. 3 and paragraph 93), and a column of pixel circuits (pixel columns PXC) is electrically connected to at least one of a plurality of first signal lines (signal wirings SW (SW1 and SW2)) (Fig. 7 and paragraph 132); wherein the display panel further comprises a display region and a non-display region at least partially surrounding the display region (an active region in which an image is displayed, and a non-active region disposed around the active region in which an image is not displayed) (Fig. 1 and paragraph 4); wherein the non-display region comprises a first fan-out region disposed on one side of the display region in the second direction, and the first fan-out region comprises a plurality of fan-out wirings (the display device includes a plurality of non-active fan-out wirings NFW_1 and NFW_2 disposed in the non-active region and connected to the pad portion 20) (Fig. 1 and paragraphs 8, 83 and 130); wherein the display region comprises a first display region and a second display region (the active region AAR may be divided into an inner active region AAR_I and an outer active region AAR_L (AAR_L1 and AAR_L2)) (Fig. 6 and paragraph 125), the second display region is disposed on at least one side of the first display region in the first direction (the outer active region AAR_L (AAR_L1 and AAR_L2) is shown on the sides of the active region AAR) (Fig. 6), the first display region and the second display region each comprises a plurality of first signal lines (the signal wirings SW (SW1 and SW2) are shown in the AAR_I and an outer active region AAR_L (AAR_L1 and AAR_L2)) (Fig. 7), the plurality of first signal lines are electrically connected to the plurality of fan-out wirings, and the plurality of first signal lines in the second display region are electrically connected to the plurality of fan-out wirings through connecting wirings (the signal wirings SW (SW1 and SW2) are shown connected to the non-active fan-out wirings NFW_1 and NFW_2 via connection wirings CW and contact electrodes CNE) (Fig. 7 and paragraph 138); wherein the connecting wirings are disposed in the display region and each comprises a first connecting line segment (a first extension portion CWV_1 of each of the connection wirings CW) extending along the first direction and a second connecting line segment (a third extension portion CWH) extending along the second direction (a first extension portion CWV_1 and a third extension portion CWH are shown extending in the first and second direction) (Fig. 7 and paragraph 130), the second connecting line segment is electrically connected to a corresponding fan-out wiring (the third extension portion CWH are electrically connected to the non-active fan-out wirings NFW_1 and NFW_2 through first contact hole CT1) (Fig. 7 and paragraph 144), and the first connecting line segment is electrically connected to a corresponding first signal line in the second display region (the first extension portion CWV_1 is shown connected to the signal wirings SW1 and SW2 in Fig. 7).
It would be obvious to one skilled in the art to combine the teachings of Liu with the teachings of Cho to have a plurality of pixel circuits are arranged in an array along the first direction and the second direction, and a column of pixel circuits is electrically connected to at least one of the plurality of first signal lines; wherein the display panel further comprises a display region and a non-display region at least partially surrounding the display region; wherein the non-display region comprises a first fan-out region disposed on one side of the display region in the second direction, and the first fan-out region comprises a plurality of fan-out wirings; wherein the display region comprises a first display region and a second display region, the second display region is disposed on at least one side of the first display region in the first direction, the first display region and the second display region each comprises a plurality of first signal lines, the plurality of first signal lines are electrically connected to the plurality of fan-out wirings, and the plurality of first signal lines in the second display region are electrically connected to the plurality of fan-out wirings through connecting wirings; wherein the connecting wirings are disposed in the display region and each comprises a first connecting line segment extending along the first direction and a second connecting line segment extending along the second direction, the second connecting line segment is electrically connected to a signal corresponding fan-out wiring, and the first connecting line segment is electrically connected to a corresponding first signal line in the second display region since this layout allows display device which includes connection wirings passing through an active region but can employ a general-purpose driver chip and reduce a difference in luminance between regions due to process dispersion of a conductive layer as taught by Cho (paragraph 7).
In regard to claim 16, Liu teaches a plurality of first supply voltage lines, each of the plurality of first supply voltage lines (a plurality of first sub-wires 11) being disposed in the display region and extending along the second direction (the plurality of first sub-wires 11 are shown extending in the vertical directions in the regions containing the plurality of pixel units in Fig. 1A) (Fig. 1A and paragraph 69), and the plurality of first supply voltage lines being electrically connected to the light emitting element (the plurality of first wires are configured to provide a power signal to the light emitting element) (paragraph 130); and a plurality of supply voltage auxiliary lines (a plurality of auxiliary wires 4) extending along the first direction (the plurality of auxiliary wires 4 are shown extending in the lateral direction in Fig. 1A) (Fig. 1A and paragraph 130); wherein the plurality of supply voltage auxiliary lines are disposed in a same layer as a first connecting line segment (a data connection line 30) and in a different layer from the plurality of first supply voltage lines (the auxiliary wires 4 are shown in the same layer as the data connection line 30 and in a different layer as the plurality of first sub-wires 11 in Fig. 4) (Fig. 4 and 58); and wherein the plurality of supply voltage auxiliary lines are electrically connected to the plurality of first supply voltage lines (the auxiliary wires 4 are electrically connected to the first sub-wires 11) paragraph 56).
In regard to claim 17, Liu teaches wherein each of the supply voltage auxiliary lines comprises a protrusion portion extending along the second direction (the portion of the plurality of auxiliary wires 4 that functions as a second electrode plate 82 in the protrusion portion) (Fig. 1B, Fig. 1E and paragraph 58); a second electrode of a fifth transistor (a seventh transistor T7) is electrically connected to a gate of the second transistor through a second connecting portion (the seventh transistor is electrically connected to the gate of the first transistor T1 through a data connection line 30 that corresponds to the first node N1 as shown in Fig. 1B and Fig. 5); the second connecting portion is disposed on one side of the active layer away from the substrate (the data connection line 30 is shown on the topside of the active layer 9 in Fig. 4), and the protrusion portion is disposed on one side of the second connecting portion away from the substrate (the protruding portion of the auxiliary wires 4 would be on the lateral side surface of the data connection line 30 away from the substrate as shown in Fig. 4); and the protrusion portion is at least partially overlapped with the second connecting portion in a direction perpendicular to a plane in which the substrate is located (as shown in Fig. 1B the protruding portion of the auxiliary wires 4 is shown overlapping the data connection line 30 that corresponds to the first node N1 in Fig. 1B).
Allowable Subject Matter
Claims 7, and 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In regard to claim 7, Liu is considered a close prior art of record. However. Liu fails to teach “wherein each of the plurality of third reference voltage lines is electrically connected to a corresponding first reference voltage line, and each of the plurality of fourth reference voltage lines is electrically connected to a corresponding second reference voltage line”. Liu does not teach any elements that could be mapped as third or fourth reference voltage lines that can be connected to the first and second reference voltage lines.
In regard to claims 13, Liu is considered a close prior art of record. However. Liu fails to teach “the plurality of second auxiliary line segments are disposed in a same layer as the second connecting line segment and are insulated from the second connecting line segment and the first connecting line segment”. Liu is silent to the regard of any element that could be mapped as the plurality of second auxiliary line segments are disposed in a same layer as the second connecting line segment and are insulated from the second connecting line segment and the first connecting line segment.
Claims 14-15 are objected to due to their dependency on claim 13.
Moreover, none of the prior arts of record, taken either alone or in combination, anticipate nor render obvious the claimed inventions.
Conclusion
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/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893