DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Domestic Benefit
No claim to an application for domestic benefit.
Foreign Priority
No claim to an application for foreign priority.
Information Disclosure Statement
The information disclosure statement submitted on 09/14/2023 was filed before first Office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
-- METAL INSULATOR METAL CAPACITOR (MIM CAPACITOR) BETWEEN TWO NANOSHEET STACKS SEPARATED BY INSULATOR--
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1, given the broadest reasonable interpretation, includes a situation wherein first stacked nanosheet and a second stacked nanosheet may be stacked vertically that is separated by a MIM capacitor. Even though Applicant in some embodiments teaches of different stacks of nanosheets in a vertical direction ONLY stacks of nanosheets in a horizontal direction are separated by a MIM capacitor. As such, Applicant does not have possession of nanosheets stacked in a vertical direction separated by a MIM capacitor. Applicant does NOT have possession of a genus claim that includes both a horizontal interpretation of separation by MIM capacitor AND also a vertical interpretation of separation by MIM capacitor.
Dependent claims 2-7 do not remedy this interpretation and are rejected for incorporating the subject matter of independent claim 1.
Independent claim 8 and dependent claims 9-13 are rejected for same reasons as claims 1-7 supra.
Independent claim 14 and dependent claims 15-20 are rejected for same reasons as claims 1-7 supra.
Claims 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
There are two claims labeled 16 that run-together without indentation. The second claim 16 appears to depend on a different claim tree than independent claim 14 thereby making both claims indefinite. For purpose of examination on the merits both claims are examined on their merits however the second 16 is interpreted as depending on independent claim 14.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-4, 6-8, 10-14, (two claims 16) and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2024/0113101 A1 to Dutta et al. (“Dutta”).
PNG
media_image1.png
443
667
media_image1.png
Greyscale
Regarding independent claim 1, Dutta teaches of a semiconductor device (abstract; first sentence) comprising:
a first stacked nanosheet Field Effect Transistor (FET) 102 (“MOS transistor”; Figure 1A; paragraph 0023. See paragraph 0026, reference number 108 that makes part of 102 are nanoribbons. See paragraph 0048, in the method of formation the nanoribbons may be considered nanosheets);
a second stacked nanosheet (as illustrated in the method of formation there is the left stack when facing Figure 2F. As illustrated in Figure 1A, part of the left stack when facing Figure 1A is intact);
a metal insulator metal (MIM) capacitor 118 (“capacitor”; Figure 1A and Figure 2N; paragraph 0023. See paragraph 0030, there are metal electrodes 120/122 separated by a dielectric layer 124 such as HfO) between the first stacked nanosheet 102 and the second stacked nanosheet (i.e., left stack when facing Figure 1A); and
an insulator 126/130 (“dielectric layer”/“isolation structure”; Figure 1A; paragraphs 0031,0033; 130+126 separates the capacitor 118 from the entirety of the left stack when facing Figure 1A; 126 separates the capacitor 118 from a lower stack of 108 in 102 –particularly the bottom 108s) separating the MIM capacitor 118 from each of the first stacked nanosheet 102 and the second stacked nanosheet (i.e., left stack when facing Figure 1A).
Regarding claim 3, Dutta teaches wherein the first stacked FET 102 comprises a replacement gate (i.e., see Figures 2: specifically removal of sacrificial layers 208 in paragraph 0048 and then the deposited gate structure in paragraph 0049. This appears to be a type of product-by-process claim that implies a structure of alternating gates and nanosheet channel regions that is already present in Figure 1A).
Regarding claim 4, Dutta teaches of a second electrode 128 (“conductive contact”; Figure 1A; paragraph 0032) of the MIM capacitor 118 connected to an inner plate 122 of the MIM capacitor 118.
Regarding claim 6, Dutta teaches in Figure 1A wherein the MIM capacitor 118 comprises an outer plate 120, a MIM insulator 124 and an inner plate 122.
Regarding claim 7, Dutta teaches in Figure 1A wherein a height of the MIM capacitor 118 (i.e., 120+124+122+128) is greater (i.e., the vertical height of adding 120+124+122+128) than a height of the first stacked nanosheet 102 (i.e., total of 102 OR the bottom two 108s separated by one gate layer and a bottom gate layer).
Regarding independent claim 8, refer to claim 1 rejection supra along with the explanation of replacement gate process of claim 3 rejection supra. Further, there may be a lower and upper stack of the first stacked nanosheet and second stacked nanosheet by grouping different 108s of Figure 1A together, accordingly. Last, in the method of formation Figure 2C there are nanosheets 210 and sacrificial layer 208, alternating.
It is noted that the first stacked nanosheet of claim 8 is not required to be an FET.
Regarding first claim 10, refer to claim 3 rejection supra.
Regarding first claim 11, refer to claim 4 rejection supra.
Regarding first claim 12, refer to claim 6 rejection supra.
Regarding first claim 13, refer to claim 7 rejection supra.
Regarding independent claim 14, refer to claim 1 rejection supra because claim 14 is the “forming” of the device of claim 1. It is noted that the first stacked nanosheet of claim 14 is not required to be an FET.
Regarding first claim 16, refer to claim 3 rejection supra.
Regarding second claim 16, refer to claim 4 rejection supra.
Regarding claim 18, refer to claim 6 rejection supra.
Regarding claim 19, refer to claim 7 rejection supra.
Regarding claim 20, refer to the process of the replacement gate of claim 3 rejection supra. Further, there may be a lower and upper stack of the first stacked nanosheet and second stacked nanosheet by grouping different 108s of Figure 1A together, accordingly.
Allowable Subject Matter
Claim 2, 5, 9, 15 and 17 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), 1st paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 2 contains allowable subject matter, because the closest prior art of record, singularly or in combination fails to disclose or suggest, in combination with the other elements of claim 2, a backside contact below the second stacked nanosheet connecting a first electrode of the MIM capacitor and a lower source drain of the second stacked nanosheet.
Claim 5 contains allowable subject matter, because the closest prior art of record, singularly or in combination fails to disclose or suggest, in combination with the other elements of claim 5, wherein the first stacked nanosheet and the second stacked nanosheet each comprise: an upper stacked nanosheet and a lower stacked nanosheet, wherein the upper stacked nanosheet and the lower stacked nanosheet each comprise: alternating layers of a work function metal and a semiconductor channel material vertically aligned and stacked one on top of another.
The prior art of Dutta does not appear to teach of a metal gate in the claimed second nanosheet stack.
Claim 9 contains allowable subject matter, because the closest prior art of record, singularly or in combination fails to disclose or suggest, in combination with the other elements of claim 9, a backside contact below the second stacked nanosheet electrically connecting a first electrode of the MIM capacitor and a lower source drain of the second stacked nanosheet.
Claim 15 contains allowable subject matter, because the closest prior art of record, singularly or in combination fails to disclose or suggest, in combination with the other elements of claim 15, forming a backside contact below the second stacked nanosheet electrically connecting a first electrode of the MIM capacitor and a lower source drain of the second stacked nanosheet.
Claim 17 contains allowable subject matter, because the closest prior art of record, singularly or in combination fails to disclose or suggest, in combination with the other elements of claim 17, wherein the first stacked nanosheet and the second stacked nanosheet each comprise: an upper stacked nanosheet and a lower stacked nanosheet, wherein the upper stacked nanosheet and the lower stacked nanosheet each comprise: alternating layers of a work function metal and a semiconductor channel material vertically aligned and stacked one on top of another.
The prior art of Dutta does not appear to teach of a metal gate in the claimed second nanosheet stack.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P DULKA whose telephone number is (571)270-7398. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ELISEO RAMOS-FELICIANO can be reached at (571)272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
27 December 2025
/John P. Dulka/Primary Examiner, Art Unit 2817