DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Foreign priority is not claimed for this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/14/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Claims 17-48 and 50 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species II and III, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 04/06/2026.
Specification
The disclosure is objected to because of the following informalities:
Par. 113: main input match network 306 should be 304 (Fig. 3).
Par. 116: “transmission line 318” should probably be “transmission line 324” since 318 is the first peak transistor.
Par. 131: last sentence “a third shunt inductor in parallel with a third capacitor” should probably read “in series” according to how it’s arranged in Fig. 3.
Appropriate correction is required.
Claim Objections
Claim 7 is objected to because of the following informalities:
Line 7: “a third shunt inductor in parallel with a third capacitor” should probably read “in series” according to how it’s arranged in figure 3. For examining purposes, examiner interprets this to mean in series.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "the average power" and “the peak power” in line 2. There is insufficient antecedent basis for this limitation in the claim. In claim 1, these are written as “average power saturation” and “peak power saturation.” Appropriate correction is required.
Claim 3 recites the limitation “a substantially constant load’ in line 4. This limitation was already claimed in claim 1. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-16 and 49 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210203279 by Pham et al.
Regarding claim 1, Pham teaches a three-way Doherty amplifier (Fig. 5), comprising:
a three-way power splitter (#510 and #511 split the signal three ways) configured to receive an input signal (RFin)and to output a main signal without a phase shift provided at a main splitter output (#132 has no phase shift), a first peak signal with a 90 degree phase shift provided at a first peak signal output (#538 has a 90 degree phase shift), and a second peak signal with a 180 degree phase shift provided at a second peak signal output (#539 has a 180 degree phase shift);
a main path comprising a main amplifier (#132), a first input network coupled between the main splitter output and the main amplifier (Par. 60), and a main impedance load on the main amplifier configured to impose a main phase offset of 90 degrees (#551);
a first peak path comprising a first peak amplifier (#538), a second input network coupled between the first peak signal output and the first peak amplifier (Par. 60), and a first peak impedance load on the first peak amplifier configured to impose a first peak phase offset of 90* (#552);
a second peak path comprising a second peak amplifier (#539), a third input network coupled between the second peak signal output and the second peak amplifier (Par. 60), and a second peak impedance load on the second peak amplifier (#553); and
a combining node configured to provide an output load impedance to output the main signal during an average power saturation and a combination of the main signal, the first peak signal, and the second peak signal during a peak power saturation (#565);
wherein a first ratio of a gate width of the main amplifier to a first gate width of the first peak amplifier and a second ratio of the gate width of the main amplifier to a second gate width of the second peak amplifier, respectively, are configured to provide a substantially constant load on the main amplifier (Par. 74; the output impedance is what sees the load impedance so the output impedance is proportional to the gate width of the transistor. It’s common knowledge in the art and also device physics for FETs).
Regarding claim 2, Pham teaches the three-way Doherty amplifier of claim 1, wherein, for the main amplifier, a power at the average power is about the same as the power at the peak power (peak power of main amp is the average power of the whole amplifier. Well known in the art of Dohertys. Main amp reaches peak power (saturation) at back off while the auxiliary amps are off because of the higher impedance offered to the main amplifier at such back off. As shown in “3-Way Doherty Power Amplifiers: Design Guidelines and MMIC Implementation at 28 GHz” by Piacibello et al. fig. 1a and 1b reaches its peak at x1 and peak power is 1. Both peaking amplifiers are off from 0 to x1 and the impedance the main amplifier is seeing is much higher than it would be seeing when all amplifiers are on. Because of high impedance, the output power of the main amp will reduce significantly. At peak power, efficiency peaks.).
Regarding claim 3, Pham teaches the three-way Doherty amplifier of claim 1, with the main impedance, first impedance load, and second impedance load consisting of a capacitor and inductor, but doesn’t specify that the inductor shunts out the output capacitance. However, this configuration and the need to shunt out output capacitance is common knowledge in the art , as shown in fig. 10 of US 10903182 by Wang et al.
Regarding claim 4, Pham teaches the three-way Doherty amplifier of claim 1, but doesn’t explicitly state that the Doherty combining node comprises a resistive load impedance for 1/(1+P1+P2), where P1 represents a number of pairs of fingers of the first peak amplifier normalized to a number of pairs of fingers of the main amplifier and P2 represents a number of pairs of fingers of the second peak amplifier normalized to the number of pairs of fingers of the main amplifier. However, it’s known in the art that this is how a basic Doherty amplifier functions. The Analysis paragraph of technical article “Anaren Doherty Combiners Simplify Amplifier Development (Tuning Doherty Combiners)” talks about the impedance at the combining node and how the 35 Ohm quarter wavelength transmission lines transforms 25 ohms to 50 ohms which makes sense for a two way Doherty if 1/(1+P1) = ½. The same concept applies to a three-way Doherty where 1/(1+P1+P2) would equal 1/3.
Regarding claim 5, Pham (with the teaching reference by Piacibello) teaches the three-way Doherty amplifier of claim 4, and while it doesn’t specify gate widths, this is simply a design choice. Asymmetry is a common design choice in Doherty amplifiers as shown in “3-Way Doherty Power Amplifiers: Design Guidelines and MMIC Implementation at 28 GHz” by Piacibello et al.
Regarding claim 6, Pham teaches the three-way Doherty amplifier of claim 1, wherein the first ratio of the gate width of the main amplifier to the first gate width of the first peak amplifier and the second ratio of the gate width of the main amplifier to the second gate width of the second peak amplifier, respectively, are configured to provide a substantially constant load on the main amplifier based on having a same impedance loading on the main amplifier, the first peak amplifier, and the second peak amplifier to cancel load modulation (Par. 75; Abstract: invention focuses on Doherty system with low load modulation; Par. 74; the output impedance is what sees the load impedance so the output impedance is proportional to the gate width of the transistor. It’s common knowledge in the art and also device physics for FETs).
Regarding claim 7, Pham teaches the three-way Doherty amplifier of claim 1, but fails to teach wherein the main impedance load comprises a first shunt inductor in series with a first capacitor and a first transmission line or a first lumped equivalent of the first transmission line, the first peak impedance load comprises a second shunt inductor in series with a second capacitor and a second transmission line or a second lumped equivalent of the second transmission line, and the second peak impedance load comprises a third shunt inductor in parallel (examiner interprets this to mean in series) with a third capacitor.
However, different types of configurations of shunt inductors, capacitors, and lumped elements/transmission lines are well known in the art, as shown in fig. 12, 13, and par. 74 of US 20120105147 by Harris et al., which teaches a three way Doherty system’s lumped element network at the output.
Regarding claim 8, Pham teaches the three-way Doherty amplifier of claim 1, but doesn’t specify the gate widths and ratios of the amplifiers. However, this is simply a design choice. Asymmetry is a common design choice in Doherty amplifiers as shown in “3-Way Doherty Power Amplifiers: Design Guidelines and MMIC Implementation at 28 GHz” by Piacibello et al.
Regarding claim 9, Pham teaches the three-way Doherty amplifier of Claim 8, wherein a ratio of peak power to average power output from the combining node is about -6 dB (Par. 78; well known that -6 dB is reached when the main and peaking amplifiers are the same size).
Regarding claim 10, Pham teaches the three-way Doherty amplifier of claim 1, but doesn’t specify the gate widths and ratios of the amplifiers. However, this is simply a design choice. Asymmetry is a common design choice in Doherty amplifiers as shown in “3-Way Doherty Power Amplifiers: Design Guidelines and MMIC Implementation at 28 GHz” by Piacibello et al.
Regarding claim 11, Pham teaches the three-way Doherty amplifier of Claim 10, wherein a ratio of peak power to average power output from the combining node is about -9.5 dB (Par. 78).
Regarding claim 12, Pham teaches the three-way Doherty amplifier of claim 1, but doesn’t specify the gate widths and ratios of the amplifiers. However, this is simply a design choice. Asymmetry is a common design choice in Doherty amplifiers as shown in “3-Way Doherty Power Amplifiers: Design Guidelines and MMIC Implementation at 28 GHz” by Piacibello et al.
Regarding claim 13, Pham teaches the three-way Doherty amplifier of Claim 12, wherein a ratio of peak power to average power output from the combining node is about -12 dB (Par. 78).
Regarding claim 14, Pham teaches the three-way Doherty amplifier of claim 1, but doesn’t specify the gate widths and ratios of the amplifiers. However, this is simply a design choice. Asymmetry is a common design choice in Doherty amplifiers as shown in “3-Way Doherty Power Amplifiers: Design Guidelines and MMIC Implementation at 28 GHz” by Piacibello et al.
Regarding claim 15, Pham teaches the three-way Doherty amplifier of Claim 14, wherein a ratio of peak power to average power output from the combining node is about -14 dB (Par. 78).
Regarding claim 16, Pham teaches the three-way Doherty amplifier of Claim 1, wherein the main amplifier is a class AB transistor and the first peak amplifier and the second peak amplifier, respectively, are class C transistors (Par. 61).
Regarding claim 49, Pham teaches a three-way Doherty amplifier, comprising:
a main path comprising a main amplifier (Fig. 5 #132), a main input network (Par. 60) coupled between a main splitter output (Fig. 5 #510 and #511 split the signal three ways) and the main amplifier, and a main output network (Fig. 5 #551) coupled between the main amplifier and a combining node (Fig. 5 #565);
a first peak path comprising a first peak amplifier (#538), a second input network coupled between a first peak signal output and the first peak amplifier (Par. 60) , and a first peak output network (#552)coupled between the first peak amplifier and the combining node (#565); and
a second peak path comprising a second peak amplifier (#539), a third input network coupled between a second peak signal output and the second peak amplifier (Par. 60), and a second peak output network (#553) coupled between the second peak amplifier and the combining node (#565),
wherein a first ratio of a gate width of the main amplifier to a first gate width of the first peak amplifier and a second ratio of the gate width of the main amplifier to a second gate width of the second peak amplifier, respectively, are configured to provide a substantially constant load on the main amplifier (Par. 74; the output impedance is what sees the load impedance so the output impedance is proportional to the gate width of the transistor. It’s common knowledge in the art and also device physics for FETs).
Conclusion
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/NAREH SHAMIRYAN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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