DETAILED ACTION
This office action is in response to the election of claims filed on April 2, 2026. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgements
Applicant's election without traverse of Invention I (Claims 1-16) in the reply filed on April 2, 2026, is acknowledged. The present office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-20 are currently pending in this application. Claims 17-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 14, 2023 is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9, 11-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zeng (US 2021/0193646).
With respect to Claim 1, Zeng discloses (Fig. 4-5) all aspects of the current invention including a power semiconductor device (1), comprising:
a semiconductor body (10) having a front side coupled to a frontside metallization (11,13) and a backside coupled to a backside metallization (12), wherein:
the frontside metallization comprises a first load terminal structure (11; including portion 115) and a control terminal structure (13; including portion 135), the backside metallization comprises a second load terminal structure (12) coupled to the backside; and
the power semiconductor device is configured to conduct a load current between the first load terminal structure and the second load terminal structure;
an active region with a plurality of transistor cells (141), the plurality of transistor cells comprising:
gate structures (electrodes 141) configured to control the load current and in electrical connection to the control terminal structure;
a plurality of source regions (101) coupled to the first load terminal structure; and a body region (102) coupled to the first load terminal structure,
wherein the frontside metallization comprises a first layer (layers 137 and 117) and a second layer (layers 1352 and 115) above the first layer,
wherein at least one of the first layer and the second layer (layers 1352 and 115) is laterally segmented, with a first segment being part of the first load terminal structure and a second segment being part of the control terminal structure
With respect to Claim 2, Zeng discloses (Fig. 4-5) wherein both the first layer (layers 137 and 117) and the second layer (layers 1352 and 115) are laterally segmented, wherein the first layer comprises a first segment that is part of the first load terminal structure and a second segment that is part of the control terminal structure, and wherein the second layer comprises a first segment that is part of the first load terminal structure and a second segment that is part of the control terminal structure.
With respect to Claim 3, Zeng discloses (Fig. 4-5) wherein in an overlap area (1311), the second segment of the second layer laterally overlaps the first segment of the first layer.
With respect to Claim 4, Zeng discloses (Fig. 4-5) wherein the second segment of the second layer is laterally surrounded by the first segment of the second layer on at least two opposing faces.
With respect to Claim 5, Zeng discloses (Fig. 4-5) wherein the second segment of the first layer is laterally surrounded by the first segment of the first layer on at least two opposing faces.
With respect to Claim 6, Zeng discloses (Fig. 4-5) all aspects of the current invention including a power semiconductor device (1), comprising:
a semiconductor body (10) having a front side coupled to a frontside metallization (11,13) and a backside coupled to a backside metallization (12), wherein:
the frontside metallization comprises a first load terminal structure (11; including portion 115) and a control terminal structure (13; including portion 135), the backside metallization comprises a second load terminal structure (12) coupled to the backside; and
the power semiconductor device is configured to conduct a load current between the first load terminal structure and the second load terminal structure;
an active region with a plurality of transistor cells (141), the plurality of transistor cells comprising:
gate structures (electrodes 141) configured to control the load current and in electrical connection to the control terminal structure;
a plurality of source regions (101) coupled to the first load terminal structure; and a body region (102) coupled to the first load terminal structure,
wherein the frontside metallization comprises a first layer (layers 137 and 117) and a second layer (layers 1352 and 115) above the first layer, both the first layer and the second layer being laterally segmented, respective segments being either connected to the first load terminal or the control terminal structure
wherein the frontside metallization comprises:
a gate runner area (1351) where both the first layer and the second layer are electrically connected to the control terminal structure
an overlap area (1311) where the first layer is electrically connected to the first load terminal and the second layer is electrically connected to the control terminal structure
a load terminal area (1151,1152) where both the first layer and the second layer are electrically connected to the first load terminal
With respect to Claim 7, Zeng discloses (Fig. 4-5) wherein in a lateral cross-section, a second segment of the first layer has a smaller lateral extension than a second segment of the second layer.
With respect to Claim 8, Zeng discloses (Fig. 4-5) wherein the frontside metallization comprises a dielectric structure (18) between the first layer and the second layer at least in the overlap area, and wherein the first layer and the second layer are electrically insulated by the dielectric structure in the overlap area
With respect to Claim 9, Zeng discloses (Fig. 4-5) wherein the dielectric structure (18) extends between a first segment of the first layer and a first segment of the second layer, and wherein first segment of the first layer and the first segment of the second layer are electrically connected through openings of the dielectric structure
With respect to Claim 11, Zeng discloses (Fig. 4-5) wherein the first layer and the second layer comprise a different metal.
With respect to Claim 12, Zeng discloses (Fig. 4-5) wherein the first layer and the second layer comprise a same metal.
With respect to Claim 13, Zeng discloses (Fig. 4-5) wherein a second segment of the second layer is arranged closer to a chip edge of the semiconductor body than every first segment of the second layer
With respect to Claim 14, Zeng discloses (Fig. 4-5) wherein the second layer in the overlap area forms a bond pad (1153) of the control terminal structure
With respect to Claim 15, Zeng discloses (Fig. 4-5) wherein some of the plurality of transistor cells (141) are arranged below a second segment of the second layer or, respectively, in the overlap area.
With respect to Claim 16, Zeng discloses (Fig. 4-5) wherein the power semiconductor device is configured as a RC-IGBT, and wherein a diode anode structure is arranged below a second segment of the second layer or, respectively, in the overlap area.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Zeng (US 2021/0193646) in view of Yagi (US 2014/0001539).
With respect to Claim 10, Zeng discloses (Fig. 4-5) most aspects of the current invention. However, Zeng does not show wherein the dielectric structure is a least partly grid-shaped between the first segment of the first layer and the first segment of the second layer.
On the other hand, and in the same field of endeavor, Yagi teaches (Fig 4) a power semiconductor device (100), comprising a semiconductor body (10) having a front side coupled to a frontside metallization (GM,SM) and a backside coupled to a backside metallization (19), wherein the frontside metallization comprises a first load terminal structure (SM) and a control terminal structure (GM), the backside metallization comprises a second load terminal structure (19) coupled to the backside, wherein the frontside metallization comprises a first layer (16/17) and a second layer (27/28) above the first layer, both the first layer and the second layer being laterally segmented and further wherein the frontside metallization comprises a dielectric structure (23) between the first layer and the second layer at least in an overlap area, and wherein the first layer and the second layer are electrically insulated by the dielectric structure in the overlap area, and further show wherein the dielectric structure is a least partly grid-shaped between the first segment of the first layer and the first segment of the second layer.
Yagi teaches the dielectric structure is provided in a desired pattern to electrically insulate the first segment (16) of the first layer from the second segment (17) of the first layer and to electrically insulate the first segment (27) of the second layer from the second segment (28) of second first layer.
However, it is noted that the specification fails to provide teachings about the criticality of having the dielectric structure is a least partly grid-shaped between the first segment of the first layer and the first segment of the second layer, as claimed in the instant application
Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the dielectric structure disclosed by Yagi as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, as the particular dielectric structure claimed by applicant is nothing more than one of numerous dielectric structure shapes that a person having ordinary skill in the art will find obvious to provide using routine experimentation based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of wherein the dielectric structure is a least partly grid-shaped between the first segment of the first layer and the first segment of the second layer in the device of Zeng, as taught by Yagi to electrically insulate the first segment (16) of the first layer from the second segment (17) of the first layer and to electrically insulate the first segment (27) of the second layer from the second segment (28) of second first layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUINTON A BRASFIELD whose telephone number is (571)272-0804. The examiner can normally be reached M-F 9AM-4PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format.
For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Q.A.B/ Examiner, Art Unit 2814
/WAEL M FAHMY/ Supervisory Patent Examiner, Art Unit 2814
Prosecution Insights