DETAILED ACTION
This non-final action is responsive to the following communications: 02/09/2026.
Applicant amended claims 2, and 16. Claims 1, 19 are in cancelled status; no new claims added. Claims 2-18, 20-21 are pending. Claims 2, 8, and 16 are independent.
Continued Examination under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/09/2026 has been entered.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Domestic Priority
4. See ADS for domestic CON priority details.
Information Disclosure Statement
5. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on: 02/09/2026. All IDS’s have been considered.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7. Claims 8-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. Such omission is tantamount to omitting essential structural cooperative relationships of elements also. See MPEP § 2172.01. A claim which omits subject matter disclosed to be essential to the invention as described in the specification or in other statements of record may be rejected as failing to claim the subject matter that the inventor or a joint inventor regards as the invention. See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976); In re Venezia, 530 F.2d 956, 189 USPQ 149 (CCPA 1976); and In re Collier, 397 F.2d 1003, 158 USPQ 266 (CCPA 1968). Such essential matter may include missing elements (circuitry components, functional descriptions/ bridging keys essential for function), steps or necessary structural cooperative relationships of elements described by the applicant(s) as necessary to practice the invention. For example, for In re Mayhew, the Court of Customs and Patent Appeals (CCPA) held that claims were not enabled under 35 U.S.C. § 112 because they omitted a cooling bath and its specific location, which were deemed essential elements based on the specification. The court found that the specification indicated these elements were critical for the invention to function as described, and their omission from the claims rendered them not supported by an enabling disclosure. In the instant case, specification disclosure para [0014], Fig. 5, para [0035], para [0041], para [006] teaches the invention but the claims lack most of the essential elements (see bold descriptions) as described in details in the following. Because of the lack of elements, claims can be interpreted in unlimited number of ways and thus they are indefinite.
Regarding independent claim 8, a method, comprising: receiving a refresh command;
refreshing a first of victim row at a first rate; refreshing a second of victim row at a second rate; (limitations fail to encompass associated victim row decoder circuit configured to determine a plurality of victim row addresses based, at least in part, on a row address, wherein the plurality of victim row addresses correspond to a plurality of victim word lines physically adjacent to an aggressor word line associated with the row address, content addressable memory configured to store the plurality of victim row addresses in a plurality of registers wherein each register of the plurality of registers includes: a first field configured to store a victim row address of a respective one of the plurality of victim row addresses; and a second field configured to store a count value associated with the respective victim row address, wherein the count value is adjusted each time the respective victim row address is determined by the victim row decoder.
Also, fails to described associated refresh address generator circuit configured to provide one of the plurality of victim row addresses for performing a refresh operation on a victim word line associated with the one of the plurality of victim row addresses during a targeted refresh operation interval when the count value associated with the one of the plurality of victim row addresses reaches a threshold value, wherein the count value is reset after the targeted refresh operation, wherein the refresh address generator circuit is configured to provide an auto-refresh address for the refresh operation on a word line corresponding to the auto-refresh address if the count value has not reached the threshold value. See Fig. 5, para [0035], para [0041], para [006]).
auto-refreshing rows at a third rate (limitation fails to encompass essential circuitry, functions, timing sequence/ relationship to victim refresh, target region/ row of auto-refresh. It is not clear if the auto-refresh is applied on the rows mentioned, victim rows or all rows of array and in which case third rate is applicable. Also see above and See Fig. 5, para [0035], para [0041], para [006]).
All dependent claims inclusive of Claims 8-15 are rejected under this category.
Double Patenting
8. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
9. Claims 2, 8, 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US 11,069,393 B2.
Although the claims at issue are not identical to US 11,069,393 B2, they are not patentably distinct from each other and obvious over apparatus configuration suggested by the sets of claims in combination. See analysis in the following:
Regarding independent claim 2, US 11,069,393 B2 teaches a memory device (US 11,069,393 B2: claims 1-16), comprising:
a memory array comprising a plurality of word lines (US 11,069,393 B2: array requiring refresh. See also claims 14, line 2: “memory array”), wherein at least one word line of the plurality of word lines is an aggressor row (claim 3, lines 1-3: “aggressor word line”);
a refresh control circuit comprising:
a first victim address generator configured to generate a first type of row address corresponding to +/-1 physically adjacent neighboring rows of the aggressor row in the memory array (US 11,069,393 B2: see claim 3, “…first victim word line is physically closer to an aggressor word line than the second victim word line…”. See also claim 16); and
a second victim address generator configured to generate a second type of row address corresponding to +/-2 physically adjacent neighboring rows of the aggressor row in the array (US 11,069,393 B2: claim 3, claim 16),
wherein the refresh control circuit is configured to provide the first type of row address at a first rate and the second type of row address at a second rate (US 11,069,393 B2: claim 6: refresh address and control signal),
wherein the first rate is greater than the second rate (US 11,069,393 B2: claim 2: “…first frequency is greater than the second frequency…”); and
at least one component configured to set the first rate and second rate (US 11,069,393 B2: claim 1: “timing circuit”).
Regarding independent claim 8, US 11,069,393 B2 teaches a method (US 11,069,393 B2: claims 17-20. See also claims 1-16), comprising:
receiving a refresh command (required refresh command, see also claim 12, 18: “command control circuit” providing refresh signal and command);
refreshing a first of victim row at a first rate; refreshing a second of victim row at a second rate; and (claims 17-18, claim 1-2)
auto-refreshing rows at a third rate (US 11,069,393 B2: claim 10: “auto-refresh” performed on address is a different operation and thus the rate and frequency is different).
Regarding independent claim 16, US 11,069,393 B2 teaches an apparatus (US 11,069,393 B2: claims 1-16) comprising:
a memory array comprising a plurality of word lines (US 11,069,393 B2: array requiring refresh. See also claims 14, line 2: “memory array”), wherein at least one word line of the plurality of word lines is an aggressor row (claim 3, lines 1-3: “aggressor word line”);
a refresh control circuit (US 11,069,393 B2, claim 1, lines 1-3): comprising
at least one victim address generator configured to generate a plurality of types of row addresses corresponding to the plurality of word lines (US 11,069,393 B2: see claim 3, “…first victim word line is physically closer to an aggressor word line than the second victim word line…”. See also claim 16),
wherein the refresh control circuit is configured to provide the plurality of types of row addresses for refresh operations performed at corresponding ones of a plurality of rates on the plurality of word lines of the memory array (US 11,069,393 B2: claim 6: “refresh address” and associated control signal); and
a row decoder configured to perform the refresh operations based on row addresses provided from the refresh control circuit (claim 7, claim 8, claims14-15),
wherein word lines corresponding to a first type of row addresses of the plurality of types of row addresses are refreshed at a first rate of the plurality of rates and word lines corresponding to a second type of row addresses of the plurality of types of row addresses are refreshed at a second rate of the plurality of rates (US 11,069,393 B2: claim 2: “…first frequency is greater than the second frequency…”. See also US 11,069,393 B2: claim 1: “timing circuit”),
wherein word lines associated with the first type of row addresses have a first physical relationship with the aggressor row and word lines associated with the second type of row addresses have a second physical relationship with the aggressor row (see claim 16, lines 1-6); and
at least one component configured to set the plurality of rates. (rate (US 11,069,393 B2: claim 1: “timing circuit”)
10. Claims 3-7, 9-15, 17-18, 20-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 11,069,393 B2, in view of claims 1-20 of US 11798610 B2.
Analysis is not shown and analysis not performed here.
Although the claims at issue are not identical to US 11798610 B2 or, US 11,069,393 B2, they are not patentably distinct from each other and obvious over the sets of claims.
(TD should be submitted for both US 11798610 B2 and US 11,069,393 B2).
Allowable Subject Matter
Claims 2-7, 16-18, 20-21 are objected to because of the NSDP double patenting rejection (see rejection above). But would be allowable if the rejection is over-come.
Regarding claims listed above, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims.
Response to Arguments
Based on claim amendments dated 02/09/2026, previously set 112b rejections of claims 2-7, 16-18, 20-21 are being withdrawn.
Based on persuasive arguments dated 02/09/2026, previous prior art rejections are being withdrawn.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: Mandava et al. (US 2014/0281207 A1): Fig. 1-Fig. 8 disclosure applicable for all claims. Morohashi et al. (US. 2019/0385667) are applicable for all claims, see specially Figure 6 disclosure of both.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached on (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825