DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on February 19, 2026 is acknowledged.
Claims 21-25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on February 19, 2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu et. al. (US 20230062775 A1), hereinafter Hsu.
Regarding claim 1, Hsu teaches a substrate (Fig 1N substrate 112, [0014]) comprising: a core layer (Fig 1D cavity substrate 120, [0018]) comprising a cavity (Fig 1D cavity hole 118, [0018]); a region (Fig 1D region R1, [0018]) comprising a passive component block (Fig 1E semiconductor device 600, [0021]) located at least partially in the cavity (Fig 1D cavity hole 118, [0018]) of the core layer (Fig 1D cavity substrate 120, [0018]), wherein the passive component block (Fig 1E semiconductor device 600, [0021]) comprises a first passive device (Fig 1E device component 200, [0023]) and a second passive device (Fig 1E device component 300, [0023]); at least one dielectric layer (Fig 1F dielectric layer 122, [0041]) coupled to the core layer (Fig 1D cavity substrate 120, [0018]); and a plurality of interconnects (Fig 1J metallization patterns M11 and M21, [0048]) located at least partially in the at least one dielectric layer (Fig 1F dielectric layer 122, [0041]).
Regarding claim 2, Hsu teaches the first passive device (Fig 1E device component 200, [0023]) comprises a first front side (Fig 3A side opposite backside 200-BS, [0035]) and a first back side (Fig 3A backside 200-BS, [0035]), and wherein the second passive device (Fig 1E device component 300, [0023]) comprises a second front side (Fig 3A side opposite backside 300-BS, [0035]) and a second back side (Fig 3A backside 300-BS, [0035]).
Regarding claim 3, Hsu teaches the first back side (Fig 3A backside 200-BS, [0035]) of the first passive device (Fig 1E device component 200, [0023]) faces (Fig 3A) the second back side (Fig 3A backside 300-BS, [0035]) of the second passive device.
Regarding claim 4, Hsu teaches the first passive device (Fig 1E device component 200, [0023]) includes a first deep trench capacitor device (Fig 4A capacitor 210, [0028]), and wherein the second passive device (Fig 1E device component 300, [0023]) includes a second deep trench capacitor device (Fig 4A capacitor 310, [0034]; structure may be similar to device component 200, [0034]).
Regarding claim 5, Hsu teaches the passive component block (Fig 1E semiconductor device 600, [0021]) includes a first block core layer (Fig 5A passivation layer 260, [0027]) and a second block core layer (Fig 5A passivation layer 360, [0034]).
Regarding claim 6, Hsu teaches the passive component block (Fig 1E semiconductor device 600, [0021]) touches (Fig 1F) the at least one dielectric layer (Fig 1F dielectric layer 122, [0041]).
Regarding claim 7, Hsu teaches the at least one dielectric layer (Fig 1F dielectric layer 122, [0041]) is located in (Fig 1F) at least part of the cavity (Fig 1D cavity hole 118, [0018]) of the core layer (Fig 1D cavity substrate 120, [0018]).
Regarding claim 8, Hsu teaches the plurality of interconnects (Fig 1J metallization patterns M11 and M21, [0048]) are configured to be electrically coupled ([0053]) to the passive component block (Fig 1E semiconductor device 600, [0021]).
Regarding claim 9, Hsu teaches the at least one dielectric layer (Fig 1F dielectric layer 122, [0041]) laterally surrounds (Fig 1F, 122R and 122F) the passive component block (Fig 1E semiconductor device 600, [0021]).
Regarding claim 10, Hsu fails to teach the substrate is implemented in a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle.
The recitation calling for “the substrate is implemented in a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle” does not distinguish over the cited reference regardless of the function allegedly performed by the claimed device, because only the device per se is relevant, no matter which of the device’s functions is referred to in the claim, and if the prior art structure is capable of performing the intended function, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967). In the instant application, implementing the substrate in an electronic device does not differentiate the claimed device Hsu since it requires merely using the substrate in an electronic device.
Regarding claim 11, Hsu teaches a package (Fig 1O package substrate 190A, [0072]) comprising: an integrated device (Fig 1N component 191, [0070]); and a substrate (Fig 1N substrate 112, [0014]) coupled to the integrated device (Fig 1N component 191, [0070]) through at least a plurality of solder interconnects (Fig 1N conductive connectors 188F, [0066]), the substrate (Fig 1N substrate 112, [0014]) comprising: a core layer (Fig 1D cavity substrate 120, [0018]) comprising a cavity (Fig 1D cavity hole 118, [0018]); a region (Fig 1D region R1, [0018]) comprising a passive component block (Fig 1E semiconductor device 600, [0021]) located at least partially in the cavity (Fig 1D cavity hole 118, [0018]) of the core layer (Fig 1D cavity substrate 120, [0018]), wherein the passive component block (Fig 1E semiconductor device 600, [0021]) comprises a first passive device (Fig 1E device component 200, [0023]) and a second passive device (Fig 1E device component 300, [0023]); at least one dielectric layer (Fig 1F dielectric layer 122, [0041]) coupled to the core layer (Fig 1D cavity substrate 120, [0018]); and a plurality of interconnects (Fig 1J metallization patterns M11 and M21, [0048]) located at least partially in the at least one dielectric layer (Fig 1F dielectric layer 122, [0041]).
Regarding claim 12, Hsu teaches the first passive device (Fig 1E device component 200, [0023]) comprises a first front side (Fig 3A side opposite backside 200-BS, [0035]) and a first back side (Fig 3A backside 200-BS, [0035]), and wherein the second passive device (Fig 1E device component 300, [0023]) comprises a second front side (Fig 3A side opposite backside 300-BS, [0035]) and a second back side (Fig 3A backside 300-BS, [0035]).
Regarding claim 13, Hsu teaches the first back side (Fig 3A backside 200-BS, [0035]) of the first passive device (Fig 1E device component 200, [0023]) faces the second back side (Fig 3A backside 300-BS, [0035]) of the second passive device (Fig 1E device component 300, [0023]).
Regarding claim 14, Hsu teaches the first passive device (Fig 1E device component 200, [0023])includes a first deep trench capacitor device (Fig 4A capacitor 210, [0028]), and wherein the second passive device (Fig 1E device component 300, [0023]) includes a second deep trench capacitor device (Fig 4A capacitor 310, [0034]; structure may be similar to device component 200, [0034]).
Regarding claim 15, Hsu teaches the passive component block (Fig 1E semiconductor device 600, [0021]) includes a first block core layer (Fig 5A passivation layer 260, [0027]) and a second block core layer (Fig 5A passivation layer 360, [0034]).
Regarding claim 16, Hsu teaches the passive component block (Fig 1E semiconductor device 600, [0021]) touches (Fig 1F) the at least one dielectric layer (Fig 1F dielectric layer 122, [0041]).
Regarding claim 17, Hsu teaches the at least one dielectric layer (Fig 1F dielectric layer 122, [0041]) is located in (Fig 1F) at least part of the cavity (Fig 1D cavity hole 118, [0018]) of the core layer (Fig 1D cavity substrate 120, [0018]).
Regarding claim 18, Hsu teaches the plurality of interconnects (Fig 1J metallization patterns M11 and M21, [0048]) are configured to be electrically coupled ([0053]) to the passive component block (Fig 1E semiconductor device 600, [0021]).
Regarding claim 19, Hsu teaches the at least one dielectric layer (Fig 1F dielectric layer 122, [0041]) laterally surrounds (Fig 1F, 122R and 122F) the passive component block (Fig 1E semiconductor device 600, [0021]).
Regarding claim 20, Hsu fails to teach the substrate is implemented in a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle.
The recitation calling for “the substrate is implemented in a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle” does not distinguish over the cited reference regardless of the function allegedly performed by the claimed device, because only the device per se is relevant, no matter which of the device’s functions is referred to in the claim, and if the prior art structure is capable of performing the intended function, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967). In the instant application, implementing the substrate in an electronic device does not differentiate the claimed device Hsu since it requires merely using the substrate in an electronic device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Batri et. al. (US 20230245990 A1) teaches a substrate that has a cavity with stacked devices formed outside of the cavity and then inserted into the substrate. The stacked devices are active and passive.
Navaja et. al. (US 20200176417 A1) teaches a substrate that has a cavity with stacked devices formed outside of the cavity and then inserted into the substrate. The stacked devices can be both passive.
Saito et. al. (US 20080261336 A1) teaches a frame of material formed around a device component prior to singulation to protect the inner component during additional processing.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN GAUTHIER can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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