Prosecution Insights
Last updated: October 02, 2026
Application No. 18/467,163

PACKAGE COMPRISING A SUBSTRATE WITH A PASSIVE COMPONENT BLOCK

Final Rejection §102§103
Filed
Sep 14, 2023
Examiner
LEE, ALVIN LYNGHI
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Qualcomm Incorporated
OA Round
2 (Final)
88%
Grant Probability
Favorable
3-4
OA Rounds
2m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
73 granted / 83 resolved
+20.0% vs TC avg
Moderate +11% lift
Without
With
+11.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
43 currently pending
Career history
126
Total Applications
across all art units

Statute-Specific Performance

§103
54.9%
+14.9% vs TC avg
§102
19.9%
-20.1% vs TC avg
§112
22.2%
-17.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 83 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment The Amendment filed August 05, 2026, has been entered. Claims 1-20 and 26-30 remain pending in the application. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-20, 26-27, and 29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu et. al. (US 20230062775 A1), hereinafter Hsu. Regarding claim 1, Hsu teaches a substrate (Fig 1N substrate 112, [0014]) comprising: a core layer (Fig 1D cavity substrate 120, [0018]) comprising a cavity (Fig 1D cavity hole 118, [0018]); a region (Fig 1D region R1, [0018]) comprising a passive component block (Fig 1E semiconductor device 600, [0021]) located at least partially in the cavity (Fig 1D cavity hole 118, [0018]) of the core layer (Fig 1D cavity substrate 120, [0018]), wherein the passive component block (Fig 1E semiconductor device 600, [0021]) comprises a first passive device (Fig 1E device component 200, [0023]) and a second passive device (Fig 1E device component 300, [0023]); one or more dielectric layers (Fig 1N adhesive 400, [0035], encapsulation layer 500, [0036], and dielectric layer 122, [0042]; It is known in the art that epoxy is a dielectric material; adhesive 400 and layer 500 may both be epoxy as disclosed in the paragraphs cited) coupled to the (i) core layer (Fig 1D cavity substrate 120, [0018]; the one or more dielectric layers are coupled to the cavity substrate through dielectric layer 122), (ii) the first passive device (Fig 1E device component 200, [0023]) and (iii) the second passive device (Fig 1E device component 300, [0023]), wherein a first portion (Fig 1N adhesive 400, [0035]) of the one or more dielectric layers (Fig 1N adhesive 400, [0035] , encapsulation layer 500, [0036], and dielectric layer 122, [0042]) is located between the first passive device (Fig 1E device component 200, [0023]) and the second passive device (Fig 1E device component 300, [0023]); and a plurality of interconnects (Fig 1N conductive pads 350, [0048]) located at least partially in the one or more dielectric layers (Fig 1N adhesive 400, [0035] , encapsulation layer 500, [0036], and dielectric layer 122, [0042]). Regarding claim 2, Hsu teaches the first passive device (Fig 1E device component 200, [0023]) comprises a first front side (Fig 3A side opposite backside 200-BS, [0035]) and a first back side (Fig 3A backside 200-BS, [0035]), wherein the second passive device (Fig 1E device component 300, [0023]) comprises a second front side (Fig 3A side opposite backside 300-BS, [0035]) and a second back side (Fig 3A backside 300-BS, [0035]), and wherein the first portion (Fig 1N adhesive 400, [0035]) of the one or more dielectric layers (Fig 1N adhesive 400, [0035] , encapsulation layer 500, [0036], and dielectric layer 122, [0042]) is coupled to and touches the first passive device (Fig 3A side opposite backside 200-BS, [0035]) and the second passive device (Fig 1E device component 300, [0023]). Regarding claim 3, Hsu teaches the first back side (Fig 3A backside 200-BS, [0035]) of the first passive device (Fig 1E device component 200, [0023]) faces toward (Fig 3A) the second back side (Fig 3A backside 300-BS, [0035]) of the second passive device (Fig 1E device component 300, [0023]), and wherein the first portion (Fig 1N adhesive 400, [0035]) of the one or more dielectric layers (Fig 1N adhesive 400, [0035] , encapsulation layer 500, [0036], and dielectric layer 122, [0042]) is coupled to and touches (i) the first back side(Fig 3A backside 200-BS, [0035]) of the first passive device (Fig 1E device component 200, [0023]) and (ii) the second back side (Fig 3A backside 300-BS, [0035]) of the second passive device (Fig 1E device component 300, [0023]). Regarding claim 4, Hsu teaches the first passive device (Fig 1E device component 200, [0023]) includes a first deep trench capacitor device (Fig 4A capacitor 210, [0028]), and wherein the second passive device (Fig 1E device component 300, [0023]) includes a second deep trench capacitor device (Fig 4A capacitor 310, [0034]; structure may be similar to device component 200, [0034]). Regarding claim 5, Hsu teaches the passive component block (Fig 1E semiconductor device 600, [0021]) includes a first block core layer (Fig 5A passivation layer 260, [0027]) and a second block core layer (Fig 5A passivation layer 360, [0034]). Regarding claim 6, Hsu teaches the one or more dielectric layers (Fig 1N adhesive 400, [0035] , encapsulation layer 500, [0036], and dielectric layer 122, [0042]) include a first dielectric layer (Fig 1N adhesive 400, [0035] and encapsulation layer 500, [0036]) and a second dielectric layer (Fig 1N dielectric layer 122, [0042]), and wherein the first dielectric layer (Fig 1N adhesive 400, [0035] and encapsulation layer 500, [0036]) is located between the first passive device (Fig 1E device component 200, [0023]) and the second passive device (Fig 1E device component 300, [0023]), wherein the first dielectric layer (Fig 1N adhesive 400, [0035] and encapsulation layer 500, [0036]) is part of the first portion (Fig 1N adhesive 400, [0035]) of the one or more dielectric layers (Fig 1N adhesive 400, [0035] , encapsulation layer 500, [0036], and dielectric layer 122, [0042]), and wherein the second dielectric layers (Fig 1N dielectric layer 122, [0042]) is coupled to and touches (i) the first dielectric layer (Fig 1N adhesive 400, [0035] and encapsulation layer 500, [0036]) and (ii) the core layer (Fig 1D cavity substrate 120, [0018]). Regarding claim 7, Hsu teaches the first dielectric layer (Fig 1N adhesive 400, [0035] and encapsulation layer 500, [0036]) is different from (the first dielectric layer includes epoxy, [0035] and [0036]; the second dielectric layer includes a polymer such as polyimide, [0042]) the second dielectric layer (Fig 1N dielectric layer 122, [0042]). Regarding claim 8, Hsu teaches the plurality of interconnects (Fig 1N conductive pads 350, [0048]) are configured to be electrically coupled ([0053]) to the passive component block (Fig 1E semiconductor device 600, [0021]). Regarding claim 9, Hsu teaches the one or more dielectric layers (Fig 1N adhesive 400, [0035] , encapsulation layer 500, [0036], and dielectric layer 122, [0042]) laterally surrounds (Fig 1F, 122R and 122F) the passive component block (Fig 1E semiconductor device 600, [0021]). Regarding claim 10, Hsu fails to teach the substrate is implemented in a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle. The recitation calling for “the substrate is implemented in a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle” does not distinguish over the cited reference regardless of the function allegedly performed by the claimed device, because only the device per se is relevant, no matter which of the device’s functions is referred to in the claim, and if the prior art structure is capable of performing the intended function, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967). In the instant application, implementing the substrate in an electronic device does not differentiate the claimed device Hsu since it requires merely using the substrate in an electronic device. Regarding claim 11, Hsu teaches a package (Fig 1O package substrate 190A, [0072]) comprising: an integrated device (Fig 1N component 191, [0070]); and a substrate (Fig 1N substrate 112, [0014]) coupled to the integrated device (Fig 1N component 191, [0070]) through at least a plurality of solder interconnects (Fig 1N conductive connectors 188F, [0066]), the substrate (Fig 1N substrate 112, [0014]) comprising: a core layer (Fig 1D cavity substrate 120, [0018]) comprising a cavity (Fig 1D cavity hole 118, [0018]); a region (Fig 1D region R1, [0018]) comprising a passive component block (Fig 1E semiconductor device 600, [0021]) located at least partially in the cavity (Fig 1D cavity hole 118, [0018]) of the core layer (Fig 1D cavity substrate 120, [0018]), wherein the passive component block (Fig 1E semiconductor device 600, [0021]) comprises a first passive device (Fig 1E device component 200, [0023]) and a second passive device (Fig 1E device component 300, [0023]); one or more dielectric layers (Fig 1N adhesive 400, [0035], encapsulation layer 500, [0036], and dielectric layer 122, [0042]; It is known in the art that epoxy is a dielectric material; adhesive 400 and layer 500 may both be epoxy as disclosed in the paragraphs cited) coupled to the (i) core layer (Fig 1D cavity substrate 120, [0018]; the one or more dielectric layers are coupled to the cavity substrate through dielectric layer 122), (ii) the first passive device (Fig 1E device component 200, [0023]) and (iii) the second passive device (Fig 1E device component 300, [0023]), wherein a first portion (Fig 1N adhesive 400, [0035]) of the one or more dielectric layers (Fig 1N adhesive 400, [0035] , encapsulation layer 500, [0036], and dielectric layer 122, [0042]) is located between the first passive device (Fig 1E device component 200, [0023]) and the second passive device (Fig 1E device component 300, [0023]); and a plurality of interconnects (Fig 1N conductive pads 350, [0048]) located at least partially in the one or more dielectric layers (Fig 1N adhesive 400, [0035] , encapsulation layer 500, [0036], and dielectric layer 122, [0042]). Regarding claim 12, Hsu teaches the first passive device (Fig 1E device component 200, [0023]) comprises a first front side (Fig 3A side opposite backside 200-BS, [0035]) and a first back side (Fig 3A backside 200-BS, [0035]), wherein the second passive device (Fig 1E device component 300, [0023]) comprises a second front side (Fig 3A side opposite backside 300-BS, [0035]) and a second back side (Fig 3A backside 300-BS, [0035]), and wherein the first portion (Fig 1N adhesive 400, [0035]) of the one or more dielectric layers (Fig 1N adhesive 400, [0035] , encapsulation layer 500, [0036], and dielectric layer 122, [0042]) is coupled to and touches the first passive device (Fig 3A side opposite backside 200-BS, [0035]) and the second passive device (Fig 1E device component 300, [0023]). Regarding claim 13, Hsu teaches the first back side (Fig 3A backside 200-BS, [0035]) of the first passive device (Fig 1E device component 200, [0023]) faces toward the second back side (Fig 3A backside 300-BS, [0035]) of the second passive device (Fig 1E device component 300, [0023]), and wherein the first portion (Fig 1N adhesive 400, [0035]) of the one or more dielectric layers (Fig 1N adhesive 400, [0035] , encapsulation layer 500, [0036], and dielectric layer 122, [0042]) is coupled to and touches (i) the first back side(Fig 3A backside 200-BS, [0035]) of the first passive device (Fig 1E device component 200, [0023]) and (ii) the second back side (Fig 3A backside 300-BS, [0035]) of the second passive device (Fig 1E device component 300, [0023]). Regarding claim 14, Hsu teaches the first passive device (Fig 1E device component 200, [0023])includes a first deep trench capacitor device (Fig 4A capacitor 210, [0028]), and wherein the second passive device (Fig 1E device component 300, [0023]) includes a second deep trench capacitor device (Fig 4A capacitor 310, [0034]; structure may be similar to device component 200, [0034]). Regarding claim 15, Hsu teaches the passive component block (Fig 1E semiconductor device 600, [0021]) includes a first block core layer (Fig 5A passivation layer 260, [0027]) and a second block core layer (Fig 5A passivation layer 360, [0034]). Regarding claim 16, Hsu teaches the one or more dielectric layers (Fig 1N adhesive 400, [0035] , encapsulation layer 500, [0036], and dielectric layer 122, [0042]) include a first dielectric layer (Fig 1N adhesive 400, [0035] and encapsulation layer 500, [0036]) and a second dielectric layer (Fig 1N dielectric layer 122, [0042]), and wherein the first dielectric layer (Fig 1N adhesive 400, [0035] and encapsulation layer 500, [0036]) is located between the first passive device (Fig 1E device component 200, [0023]) and the second passive device (Fig 1E device component 300, [0023]), wherein the first dielectric layer (Fig 1N adhesive 400, [0035] and encapsulation layer 500, [0036]) is part of the first portion (Fig 1N adhesive 400, [0035]) of the one or more dielectric layers (Fig 1N adhesive 400, [0035] , encapsulation layer 500, [0036], and dielectric layer 122, [0042]), and wherein the second dielectric layers (Fig 1N dielectric layer 122, [0042]) is coupled to and touches (i) the first dielectric layer (Fig 1N adhesive 400, [0035] and encapsulation layer 500, [0036]) and (ii) the core layer (Fig 1D cavity substrate 120, [0018]). Regarding claim 17, Hsu teaches the first dielectric layer (Fig 1N adhesive 400, [0035] and encapsulation layer 500, [0036]) is different from (the first dielectric layer includes epoxy, [0035] and [0036]; the second dielectric layer includes a polymer such as polyimide, [0042]) the second dielectric layer (Fig 1N dielectric layer 122, [0042]). Regarding claim 18, Hsu teaches the plurality of interconnects (Fig 1N conductive pads 350, [0048]) are configured to be electrically coupled ([0053]) to the passive component block (Fig 1E semiconductor device 600, [0021]). Regarding claim 19, Hsu teaches the one or more dielectric layers (Fig 1N adhesive 400, [0035] , encapsulation layer 500, [0036], and dielectric layer 122, [0042]) laterally surrounds (Fig 1F, 122R and 122F) the passive component block (Fig 1E semiconductor device 600, [0021]). Regarding claim 20, Hsu fails to teach the substrate is implemented in a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle. The recitation calling for “the substrate is implemented in a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle” does not distinguish over the cited reference regardless of the function allegedly performed by the claimed device, because only the device per se is relevant, no matter which of the device’s functions is referred to in the claim, and if the prior art structure is capable of performing the intended function, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967). In the instant application, implementing the substrate in an electronic device does not differentiate the claimed device Hsu since it requires merely using the substrate in an electronic device. Regarding claim 26, Hsu teaches a boundary interface (Fig 1N) between the first dielectric layer (Fig 1N adhesive 400, [0035] and encapsulation layer 500, [0036]) and the second dielectric layer (Fig 1N dielectric layer 122, [0042]). Regarding claim 27, the first dielectric layer (Fig 1N adhesive 400, [0035] and encapsulation layer 500, [0036]) is a first type of a dielectric layer (the first dielectric layer includes epoxy, [0035] and [0036]), and wherein the second dielectric layer (Fig 1N dielectric layer 122, [0042]) is a second type of a dielectric layer (the second dielectric layer includes a polymer such as polyimide, [0042]). Regarding claim 29, Hsu teaches a boundary interface (Fig 1N) between the first dielectric layer (Fig 1N adhesive 400, [0035] and encapsulation layer 500, [0036]) and the second dielectric layer (Fig 1N dielectric layer 122, [0042]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 28 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et. al. (US 20230062775 A1), hereinafter Hsu, in view of LV (CN 116130444 A). Regarding claim 28, Hsu fails to teach the first portion of the one or more dielectric layers includes one of at least prepreg and/or Ajinomoto Build-up Film (ABF). Regarding the choice of including Ajinomoto build-up film in the first portion of the one or more dielectric layers, this particular material would have been obvious to try. Hsu teaches the adhesive 400 can be epoxy or a die attach film ([0035]). Further, Hsu teaches the encapsulation layer 500 can be a resin such epoxy or a molding underfill ([0036]) to encapsulate the passive devices ([0036]). In addition, Hsu teaches the dielectric layer 122 can be formed of Ajinomoto build-up film or a polymer such as those listed for the encapsulation layer ([0042]). Lv teaches it was known in the art before the effective filing date of the claimed invention that dielectric materials such as epoxy resin or Ajinomoto build-up film could be used as adhesive or underfill ([n0064]). In pursuing a material to cover and physically connect the passive devices, one having ordinary skill in the art before the effective filing date of the claimed invention would be able to use the list of materials provided by Hsu and Lv. One having ordinary skill in the art would recognize that the adhesive and coating properties would be achieved equally, regardless of which of these materials is chosen. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421. Regarding claim 30, Hsu fails to teach the first portion of the one or more dielectric layers includes one of at least prepreg and/or Ajinomoto Build-up Film (ABF). Regarding the choice of including Ajinomoto build-up film in the first portion of the one or more dielectric layers, this particular material would have been obvious to try. Hsu teaches the adhesive 400 can be epoxy or a die attach film ([0035]). Further, Hsu teaches the encapsulation layer 500 can be a resin such epoxy or a molding underfill ([0036]) to encapsulate the passive devices ([0036]). In addition, Hsu teaches the dielectric layer 122 can be formed of Ajinomoto build-up film or a polymer such as those listed for the encapsulation layer ([0042]). Lv teaches it was known in the art before the effective filing date of the claimed invention that dielectric materials such as epoxy resin or Ajinomoto build-up film could be used as adhesive or underfill ([n0064]). In pursuing a material to cover and physically connect the passive devices, one having ordinary skill in the art before the effective filing date of the claimed invention would be able to use the list of materials provided by Hsu and Lv. One having ordinary skill in the art would recognize that the adhesive and coating properties would be achieved equally, regardless of which of these materials is chosen. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421. Response to Arguments Applicant’s arguments, see 35 USC §102 section starting on page 8, filed August 05, 2026, with respect to the rejection(s) of claim(s) 1 and 11 under 35 USC §102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a different interpretation of Hsu. The amended limitation involving dielectric layer has been interpreted to use different dielectric layers of Hsu. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN GAUTHIER can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALVIN L LEE/Examiner, Art Unit 2813 /STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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Prosecution Timeline

Sep 14, 2023
Application Filed
May 14, 2026
Non-Final Rejection mailed — §102, §103
Aug 05, 2026
Response Filed
Sep 23, 2026
Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+11.1%)
3y 2m (~2m remaining)
Median Time to Grant
Moderate
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