Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7-8, 21 and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gao (US 20210092878 A1).
Regarding Claim 1, Gao teaches a semiconductor device (see Fig. 3A), comprising:
a substrate (110) having one or more integrated circuit die (103) disposed on a top surface;
a thermal module (cooling plates 101 and 102, connected via heat pipe 305 to inlet port and outlet ports 302 and 303) surrounding the substrate (shown Fig. 3A), wherein the thermal module includes:
an upper plate (101),
a lower plate (102), wherein the substrate is positioned between the upper plate and the lower plate (shown Fig. 3A), and
at least one heat pipe (305, shown Fig. 3B) extending from the upper plate to the lower plate.
Regarding Claim 7, Gao teaches the semiconductor device of claim 1, further comprising a spring screw (108A, 108B, 401 and 402, see also [0029]) shown fig. 4, coupling the upper plate and the lower plate.
Regarding Claim 8, Gao teaches the semiconductor device of claim 1, wherein the upper plate and the lower plate are filled with a liquid (see [0016]).
Regarding Claim 21, Gao teaches a structure including a semiconductor device package (see Figs. 3A-3B and 4),
a substrate (110) having at least one integrated circuit (IC) (103) disposed on the substrate;
an upper plate (101) above the substrate;
a lower plate (102) below the substrate; and
a plurality of attachment components (108 and 305, see also Figs. 1 and 3B) connecting the upper plate and the lower plate, wherein in a cross-sectional view the at least one IC is between a first attachment component of the plurality of attachment components and a second attachment component of the plurality of attachment components, and wherein the first attachment component and the second attachment component are each one of a thermal pipe or a spring screw (shown Fig. 3B).
Regarding Claim 23, Gao teaches the structure of claim 21, further comprising:
a thermal interface material (105, see also [0018]) extending between the at least one IC and the upper plate (shown Fig. 3A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-3, 9-10, 11-13, 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Gao (US 20210092878 A1) in further view of Nabovati (US 20250087557 A1).
Regarding Claim 2, Gao teaches the semiconductor device of claim 1, but does not explicitly teach a plurality of voltage regulator modules (VRM) disposed on a bottom surface of the substrate.
Nabovati teaches a semiconductor device (see Figs. 7A-7B) comprising an upper plate (701), a lower plate (705), a substrate (702) comprising a plurality of IC die (703) on an upper surface of the substrate and further comprising a plurality of voltage regulator modules (704, see also [0013] and [0072]) on a bottom surface of the substrate (shown Fig. 7B).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the device of Gao to further comprise a plurality of voltage regulator modules on a bottom surface of the substrate as this would optimize power consumption via voltage regulation while increasing computational density and reducing package volume (see also Nabovati: 0040]).
Regarding Claim 3, Gao as modified by Nabovati teaches the semiconductor device of claim 2, further comprising a thermal interface material (TIM) (Gao: 106) extending from each of the plurality of VRM to the lower plate (as modified by Nabovati, see also Nabovati: [0054] disclosing a thermal interface material being implemented between cooler plates and electronic layers).
Regarding Claim 9, Gao teaches the semiconductor device of claim 1, but does not explicitly teach a frontside ring extending along an upper surface of a periphery of the substrate and a backside ring extending along a lower surface of the periphery of the substrate.
Nabovati teaches a semiconductor device (see Figs. 7A-7B) comprising an upper plate (701), a lower plate (705), a substrate (702) comprising a plurality of IC die (703) on an upper surface of the substrate and further comprising a frontside ring (outer portion of 702, shown Fig. 7B) along an upper surface of the periphery of the substrate and a backside ring (713) along a lower surface of the periphery of the substrate.
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement a frontside ring as shown in Nabovati to accommodate the plurality of die disposed on the upper surface of the substrate and further implementing a backside ring to provide a communication interface to connect to additional semiconductor devices (see also [0072-0073]) as these features aid in high-density packaging (see also [0039]).
As applied to Gao, this modification would teach a frontside ring extending along an upper surface of a periphery of the substrate and a backside ring extending along a lower surface of the periphery of the substrate.
Regarding Claim 10, Gao as modified by Nabovati teaches the semiconductor device of claim 9, wherein the frontside ring and the backside ring are between the upper plate and the lower plate.
Regarding Claim 11, Gao teaches a semiconductor device (see Figs. 3A-3B and 4) comprising:
a substrate (110) having a top surface and a bottom surface;
an integrated circuit (IC) die (103) disposed on the top surface;
an upper thermally conductive plate (101) disposed over the top surface of the substrate and thermally coupled to the IC die (shown Fig. 3A);
a lower thermally conductive plate (102) disposed under the bottom surface of the substrate; and
a connection (heat pipe 305 and spring screws 108A-B, 402 and 401 shown Fig. 4) extending between the upper thermally conductive plate and the lower thermally conductive plate (shown Figs. 3B and 4).
Gao does not explicitly teach a voltage regulator module (VRM) disposed on the bottom surface and coupled to the lower thermally conductive plate.
Nabovati teaches a semiconductor device (see Figs. 7A-7B) comprising an upper plate (701), a lower plate (705), a substrate (702) comprising a plurality of IC die (703) on an upper surface of the substrate and thermally coupled to the upper plate and further comprising a plurality of voltage regulator modules (704, see also [0013] and [0072]) on a bottom surface of the substrate (shown Fig. 7B) and thermally coupled to the lower plate.
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the device of Gao to further comprise a plurality of voltage regulator modules on a bottom surface of the substrate as this would optimize power consumption via voltage regulation while increasing computational density and reducing package volume (see also Nabovati: 0040]).
As applied to Gao, this modification would teach a voltage regulator module (VRM) disposed on the bottom surface and coupled to the lower thermally conductive plate.
Regarding Claim 12, Gao as modified by Nabovati teaches the semiconductor device of claim 11, wherein the connection is a plurality of heat pipes (305, shown Fig. 3B).
Regarding Claim 13, Gao as modified by Nabovati teaches the semiconductor device of claim 11, wherein the connection is a spring screw (shown Fig. 4).
Regarding Claim 15, Gao as modified by Nabovati teaches the semiconductor device of claim 11, further comprising:
a thermal interface material (106) extending from the VRM to the lower thermally conductive plate.
Regarding Claim 17, Gao as modified by Nabovati teaches the semiconductor device of claim 11, wherein the IC die is a chip disposed on a substrate (see Gao: [0019]).
Claim(s) 4-6 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Gao (US 20210092878 A1) in further view of Austin (US 20240111344 A1).
Regarding Claim 4, Gao teaches the semiconductor device of claim 1, but does not explicitly teach a liquid cooling plate between the upper plate and the one or more integrated circuit die.
Austin teaches a semiconductor device (shown Figs. 1-2) comprising one or more die (110A) surrounded by a thermal module including an upper plate (108C-D), a lower plate (108A-B) and heat pipes (114, shown Fig. 2) connecting the upper plate and lower plate and further comprising a liquid cooling plate (112A) between the upper plate and the one or more die (shown Fig. 1).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to further implement a liquid cooling plate as suggested by Austin as this would improve cooling performance within the semiconductor device (see also Austin: [0094]).
As modified by Austin, the liquid cooling plate would be coupled to an upper surface of the one or more integrated circuit die of Gao in between an upper plate and the one or more circuit die.
Regarding Claim 5, Gao as modified by Austin teaches the semiconductor device of claim 4, wherein the liquid cooling plate includes an inlet for a coolant and an outlet for the coolant (as modified by Austin, see Fig. 1).
Regarding Claim 6, Gao as modified by Austin teaches the semiconductor device of claim 4.
Gao further teaches a thermal interface material (105) being disposed between the upper surface of the integrated circuit die and a lower surface of the upper plate (shown Fig. 3A). Gao further suggests implementing additional thermal interface material layers between the upper plate and other components (see also Gao: [0018]).
As modified by Austin, it would be obvious to one of ordinary skill in the art to further implement a thermal interface material between each electronic component and plate layer to improve thermal conductance between the cooling plates and the integrated circuit die while further preventing short circuit (see Gao: [0018]).
As applied to Gao this would teach:
a first thermal interface material (TIM) extending from the liquid cooling plate to an upper surface of the integrated circuit die and a second TIM extending from the liquid cooling plate the upper plate.
Regarding Claim 22, Gao teaches the structure of claim 21, but does not explicitly teach a liquid cooling plate over the substrate, and wherein the upper plate included is above the liquid cooling plate; and
wherein an outlet of the liquid cooling plate is coupled to another liquid cooling plate of another package.
Austin teaches a semiconductor device (shown Figs. 1-2) comprising one or more die (110A) surrounded by a thermal module including an upper plate (108C-D), a lower plate (108A-B) and heat pipes (114, shown Fig. 2) connecting the upper plate and lower plate and further comprising a liquid cooling plate (112A) between the upper plate and the one or more die (shown Fig. 1).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant to further implement a liquid cooling plate as suggested by Austin as this would improve cooling performance within the semiconductor device (see also Austin: [0094]).
As modified by Austin, the liquid cooling plate would be coupled to an upper surface of the one or more integrated circuit die of Gao in between an upper plate and the one or more circuit die.
Gao further describes each cooling plate comprising an inlet and outlet for coolant flow (see [0020] wherein a plurality of structures may be implemented in an electronic rack including a number of shelves with multiple cooling devices being implemented.
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to couple an outlet of a first structure to a liquid cooling plate of another package on a common electronic rack to provide coolant to multiple structures on a common server rack (see Gao: [0020-0021]).
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Gao (US 20210092878 A1) in view of Nabovati (US 20250087557 A1) and further in view of Austin (US 20240111344 A1).
Regarding Claim 14, Gao as modified by Nabovati teaches the semiconductor device of claim 11, but does not explicitly teach a liquid cooling plate between the top surface of the substrate and the upper thermally conductive plate.
Austin teaches a semiconductor device (shown Figs. 1-2) comprising one or more die (110A) surrounded by a thermal module including an upper plate (108C-D), a lower plate (108A-B) and heat pipes (114, shown Fig. 2) connecting the upper plate and lower plate and further comprising a liquid cooling plate (112A) between the upper plate and the one or more die (shown Fig. 1).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to further implement a liquid cooling plate as suggested by Austin as this would improve cooling performance within the semiconductor device (see also Austin: [0094]).
As modified by Austin, the liquid cooling plate would be coupled to an upper surface of the one or more integrated circuit die of Gao in between an upper plate and the upper surface of the substrate.
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Gao (US 20210092878 A1) in view of Nabovati (US 20250087557 A1) and further in view of Chuang (US 20060249280 A1).
Regarding Claim 16, Gao as modified by Nabovati teaches the semiconductor device of claim 11, but does not explicitly teach wherein the lower thermally conductive plate includes a raised portion adjacent the VRM.
Chuang teaches a semiconductor device wherein a lower thermally conductive plate (260, see Fig. 2) comprises a raised portion (264) to accommodate electronic components within the device (see also Chuang: [0020]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the lower thermally conductive plate of Gao to have a raised portion to tightly maintain contacts between components and provide a desired height between the lower thermally conductive plate and the substrate (see also Chaung: [0019-0020]).
As applied to the device of Gao and Nabovati, this modification would teach that the lower thermally conductive plate includes a raised portion adjacent the VRM.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Zhu (US 20240030096 A1) teaches a semiconductor package comprising surface-mounted discrete devices with double-sided heat sinking (shown Fig. 2).
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/C.P.B./ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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