DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 6, 7, 10, 15, 16, 19, and20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kumar et al. US 8,788,995 B1 (“Kumar”) in view of Segal et al. US 2014/0189624 A1 (“Segal”).
As to claim 1, Kumar discloses a method for whole-process placement and routing incremental optimization, comprising:
acquiring, based on a comprehensive timing analysis result after placement and routing, all violation cells that do not satisfy core constraints (Kumar Column 8 Lines 7-50 – e.g., timing analysis, including identifying timing violations, see also Segal, explained below);
determining, among all the violation cells, one or a plurality of independent target violation cells to be optimized, the plurality of independent target violation cells referring to a plurality of target violation cells that are uncorrelated both in terms of logical connections and spatial connections (Kumar Figure 1, Column 8 Lines 7-50 – e.g., timing violations, and Column 10 Line 62-Column 11 Line 59 – e.g., analysis of different paths);
adjusting a position or area of each of the target violation cells and synchronously adjusting routing of a neighboring cell connected to the target violation cell to satisfy the core constraints (Kumar Figure 1A or Column 8 Lines 15-50 – e.g., buffer insertion and gate resizing performed as part of a place and route optimization);
updating a placement and routing environment after optimization of the one or more independent target violation cells and outputting an updated comprehensive timing analysis result (Kumar Figure 1A or Column 8 Lines 15-50 – e.g., an overall place and route optimization);
judging, based on the updated comprehensive timing analysis result, whether violation cells are present; and if violation cells are present, reacquiring, in the new placement and routing environment, all violation cells that do not satisfy the core constraints, determining target violation cells to be optimized (Kumar Figure 1A or Column 11 Line 60-Column 12 Line 16 – e.g., “remedy timing defects”), and
repeatedly performing the operations of optimizing the target violation cells, updating the placement and routing environment after optimization, judging, and determining the target violation cells among all the violation cells based on the updated comprehensive timing analysis result (Kumar Figure 1A or Column 11 Line 60-Column 12 Line 16 – e.g., “repetitive iterative loop” of analysis and optimization).
Kumar discloses many of the elements of claim 1, including performing timing analysis and design optimizations. Kumar discloses identifying timing pathways to perform optimization on, rather than specific cells. However, the missing element is well known in the art because while teaching iterative optimization of a circuit, Segal discloses cell and timing analysis at the cell level in order to perform optimizations (Segal Paragraph 24). It would have been obvious to one having ordinary skill in the art at the time the invention was made to use cell level analysis and manipulation, as in Segal, in the optimization as Kumar, because doing so would allow the design to be easily optimized while replacing cells and/or updating timing information.
As to claim 6, Kumar and Segal disclose the method of claim 1. Kumar and Segal further disclose wherein after the comprehensive timing analysis result is obtained, all the violation cells are ranked based on timing margins, and a violation cell with a lowest timing margin is determined as a first target violation cell; and the rest of the independent target violation cells are determined based on a relationship between other violation cells and the determined first target violation cell in terms of logical connections and spatial connections (Kumar Figure 3 – e.g., identification and ranking of nodes with violations, including timing and propagation criteria).
As to claim 7, Kumar and Segal disclose the method of claim 1. Kumar and Segal further disclose wherein after the comprehensive timing analysis result is obtained, a critical path is determined, and a violation cell with a lowest timing margin on the critical path is determined as a first target violation cell; and the rest of the independent target violation cells are determined based on a relationship between other violation cells and the determined first target violation cell in terms of logical connections and spatial connections (Kumar Figure 3 – e.g., identification and ranking of nodes with violations , Kumar Figure 16 – e.g., “worst endpoint path”).
As to claim 19, Kumar and Segal disclose the method of claim 1. Kumar and Segal further disclose a computer device, comprising a memory, a processor, and a computer program stored on the memory and capable of running on the processor (Kumar Figure 14 or Segal Figure 5).
As to claim 20, Kumar and Segal disclose the method of claim 1. Kumar and Segal further disclose a computer-readable storage medium having a computer program stored thereon (Kumar Figure 14 or Segal Figure 5).
Claims 10, 15, and 16 recite elements similar to claims 1, 6, and 7, and are rejected for similar reasons.
Allowable Subject Matter
Claims 2-5, 8, 9, 11-14, 17, and 18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not teach or suggest a method or apparatus for whole-process placement and routing incremental optimization having the combination of steps/elements of the claims including, among other elements, the grid and division details of the claims, in combination with the analysis and manipulation elements of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYCE M AISAKA whose telephone number is (571)270-5808. The examiner can normally be reached M-F: 6:30AM-5:00PM PT.
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/BRYCE M AISAKA/ Primary Examiner, Art Unit 2851
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