DETAILED ACTION
This Office action responds to Applicant’s application filed on 09/14/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-18.
Information Disclosure Statement (IDS)
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Specification Objection
The specification has been checked to the extend necessary to determine the presence of possible minor errors. However, the Applicant’s cooperation is requested in correcting any errors of which Applicant may become aware in the specification.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Therefore, the following features must be shown or the features canceled from the claims:
Next to fig. 1 (of the instant application) of the MPS diode 100, it should be written “Prior Art”
The MPS diode 1 of claim 11 not showing the subregions of each of the plurality of wells 5 that has a higher dopant concentration than a remainder of the wells 5 for enabling Ohmic contacts with the metal layer 105a (see, e.g., fig. 1, of the instant application).
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-5, 8, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by over Rascuna (US 2022/0028979).
Regarding claim 1, Rascuna shows (see, e.g., Rascuna: figs. 2, and 3A-3C) all aspects of the instant invention including a merged PiN Schottky (MPS) diode 50/100 (see, e.g., Rascuna: par. [0002]), comprising a semiconductor body 53/52/59’/64 including an active area, wherein the active area 52/59’/64 comprises:
A drift region 52 of a first conductivity type (see, e.g., Rascuna: par. [0025])
A plurality of wells 59’/59/104 of a second conductivity type different from the first conductivity type (see, e.g., Rascuna: par. [0033]), wherein the plurality of wells 59’ are mutually spaced apart, with each well forming a respective PN-junction with the drift region 52 (see, e.g., Rascuna: par. [0021])
A metal layer assembly 58/69 arranged on a surface 52a of the semiconductor body 53/52/59’/64 and comprising at least one metal layer 58
wherein:
The metal layer assembly 58/69 forms a plurality of Schottky contacts together with the drift region 52 and a plurality of respective Ohmic contacts with the plurality of wells 59’/59/104 (see, e.g., Rascuna: par. [0014], and [0022] – [0023]) (see also MPEP 2112.01(I))
The drift region 52 comprises a doped region 64 arranged in the active area 52/59’/64 surrounding each of the plurality of wells 59’/59/104
The doped region 64 has a higher dopant concentration than a remainder of the drift region 52 (see, e.g., Rascuna: par. [0025], and [0028] – [0029])
In a first direction from a center of the doped region 64 to an edge of the doped region 64, the dopant concentration in the doped region 64 decreases (see, e.g., Rascuna: [0028] – [0029]) (the first direction is considered perpendicular to the metal layer 58, perpendicular to the upper surface 52a of the drift region 52, and parallel to the length of the wells 59’)
The doped region 64 comprises a substantially uniformly doped center region 64b and a substantially uniformly doped outer region 64a/64c arranged in between the center region and the edge of the doped region 64 (see, e.g., Rascuna: par. [0025], and [0028] – [0029])
The center region 64b has a higher dopant concentration than the outer region 64a/64c (see, e.g., Rascuna: par. [0025], and [0028] – [0029])
Regarding claim 4, Rascuna shows (see, e.g., Rascuna: figs. 2, and 3A-3C) that the center region 64b has a dopant concentration that is at least two times higher than a dopant concentration at or near the edge of the doped region 64 (see, e.g., Rascuna: par. [0025], and [0028] – [0029]).
Regarding claim 5, Rascuna shows (see, e.g., Rascuna: figs. 2, and 3A-3C) that the doped region 64 has a dopant concentration that is at least two times higher than a dopant concentration in a remainder of the drift region 52 (see, e.g., Rascuna: par. [0025], and [0028] – [0029]).
Regarding claim 8, Rascuna shows (see, e.g., Rascuna: figs. 2, and 3A-3C) that the plurality of wells 59’/59/104 has a spacing between adjacently arranged wells 59’/59/104 that is substantially identical.
Regarding claim 18, Rascuna shows (see, e.g., Rascuna: figs. 2, and 3A-3C) all aspects of the instant invention including a method for manufacturing a merged PiN Schottky (MPS) diode 50/100 (see, e.g., Rascuna: par. [0002]), comprising:
Providing a semiconductor body 53/52/59’/64 including an active area, wherein the active area 52/59’/64 comprises a drift region 52 of a first conductivity type (see, e.g., Rascuna: par. [0025])
Forming a doped region 64 in the drift region 52, wherein the doped region 64 has a higher dopant concentration than the remainder of the drift region 52 (see, e.g., Rascuna: par. [0025], and [0028] – [0029]), and wherein in a first direction from the center of the doped region 64 to an edge of the doped region 64, the dopant concentration in the doped region decreases (see, e.g., Rascuna: [0028] – [0029]) (the first direction is considered perpendicular to the metal layer 58, perpendicular to the upper surface 52a of the drift region 52, and parallel to the length of the wells 59’/59/104)
Forming a plurality of wells 59’/59/104 of a second conductivity type different from the first conductivity type in the doped region 64 (see, e.g., Rascuna: par. [0033]), wherein the plurality of wells 59’/59/104 are mutually spaced apart, with each well forming a respective PN-junction with the drift region 52 (see, e.g., Rascuna: par. [0021])
Arranging a metal layer assembly 58/69 on a surface 52a of the semiconductor body 53/52/59’/64, wherein the metal layer assembly 58/69 comprises at least one metal layer 58, and wherein the metal layer assembly 58/69 forms a plurality of Schottky contacts together with the drift region and a plurality of respective Ohmic contacts with the plurality of wells 59’/59/104’ (see, e.g., Rascuna: par. [0014], and [0022] – [0023]) (see also MPEP 2112.01(I))
The drift region 52 comprises a doped region 64 arranged in the active area 52/59’/64 surrounding each of the plurality of wells 59’/59/104, wherein the doped region 64 has a higher dopant concentration than a remainder of the drift region 52, and wherein in a first direction from a center of the doped region to an edge of the doped region, the dopant concentration in the doped region decreases
The doped region 64 comprises a substantially uniformly doped center region 64b and a substantially uniformly doped outer region 64a/64c arranged in between the center region 64b and the edge 64a/64c of the doped region 64, and wherein the center region 64b has a higher dopant concentration than the outer region 64a/64c (see, e.g., Rascuna: par. [0025], and [0028] – [0029])
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Rascuna (US 2022/0028979).
Regarding claim 3, Rascuna shows (see, e.g., Rascuna: figs. 2, and 3A-3C) most aspects of the instant invention including a merged PiN Schottky (MPS) diode 50/100 (see, e.g., Rascuna: par. [0002]), comprising the center region 64b, the outer region 64a/64c, and a number of wells 59’. Rascuna shows (see, e.g., Rascuna: figs. 2, and 3A-3C) that the center region 64b surrounds between 40-60% of the number of wells 59’, and wherein the outer region 64a/64c surrounds a remainder of the number of wells 59’.
However, the differences in the percentages of the number of wells surrounded by the center region 64b and by the outer region 64a/64c will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the mentioned percentages of the number of wells, and Rascuna has identified such percentages of the number of wells as result-effective variables subject to optimization (see, e.g., Rascuna: par. [0033] – [0034]), it would have been obvious to one of ordinary skill in the art to use these thickness values in the device of Rascuna.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed thickness values or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claims 6-7, 9-10, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Rascuna in view of Yasui (US 2018/0047855).
Regarding claim 6, Rascuna shows (see, e.g., Rascuna: figs. 2, and 3A-3C) most aspects of the instant invention including a merged PiN Schottky (MPS) diode 50/100 (see, e.g., Rascuna: par. [0002]), comprising a doped region 64 and a plurality of wells 59’/59/104 each extend from the surface 52a of the semiconductor body 53/52/59’/64.
However, Rascuna fails (see, e.g., Rascuna: figs. 2, and 3A-3C) to show that the doped region 64 extends further into the semiconductor body 53/52/59’/64 than the plurality of wells 59’/59/104. Yasui, in a similar device to Rascuna, shows (see, e.g., Yasui: fig. 8) that the doped region 11 extends further into the semiconductor body 10 than the plurality of wells 2/17. Yasui also shows (see, e.g., Yasui: fig. 8) that by such a region 11, namely a current dispersion layer, the resistance of a constricted current path 12 is reduced and the current path can be expanded up to a part right under region 2. As a result, conduction loss can be reduced to the extent nearly equal to an Schottky Barrier Diode (SBD) of a simplified structure (see, e.g., Yasui: par. [0012]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the doped region of Yasui that extends further into the semiconductor body than the plurality of wells in the device of Rascuna, in order to reduce the resistance of a constricted current path, and to reduce the conduction loss.
Regarding claim 7, Rascuna shows (see, e.g., Rascuna: figs. 2, and 3A-3C) most aspects of the instant invention including a merged PiN Schottky (MPS) diode 50/100 (see, e.g., Rascuna: par. [0002]), comprising a plurality of wells 59’/59/104.
However, Rascuna fails (see, e.g., Rascuna: figs. 2, and 3A-3C) to show that the plurality of wells 59’/59/104 are arranged as parallel strips or as concentric shapes. Yasui, in a similar device to Rascuna, shows (see, e.g., Yasui: fig. 12) that the plurality of wells 2 are arranged as parallel strips or as concentric shapes. Yasui also shows (see, e.g., Yasui: fig. 8) that, with the plurality of wells 2 arranged as parallel strips or as concentric shapes, not only surge current ruggedness improves, but also the changes of a chip size, the shape and dimension of a pattern, and the like from the conventional ones corresponding to desired characteristics can be minimized. Consequently, the increase of difficulty in design and the increase of cost of a power semiconductor element can be avoided even when an annular pattern is added (see, e.g., Yasui: par. [0077]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the plurality of wells of Yasui arranged as parallel strips or as concentric shapes in the device of Rascuna, in order to improve the surge current ruggedness, the changes of a chip size, the shape and dimension of a pattern, and the like from the conventional ones.
Regarding claim 9, Rascuna shows (see, e.g., Rascuna: figs. 2, and 3A-3C) most aspects of the instant invention including a merged PiN Schottky (MPS) diode 50/100 (see, e.g., Rascuna: par. [0002]), comprising the plurality of wells 59’/59/104 relatively spaced apart.
However, Rascuna fails (see, e.g., Rascuna: figs. 2, and 3A-3C) to show that the doped region 64 between the wells 59’/59/104 becomes depleted at substantially a same voltage applied to the MPS diode 50/100. Yasui, in a similar device to Rascuna, shows (see, e.g., Yasui: fig. 8) that the doped region 11/16 between the wells 2/17 becomes depleted at substantially a same voltage applied to the MPS diode 50/100. Yashui also shows (see, e.g., Yasui: fig. 8) that when a reverse voltage is applied between the anode electrode 6 and the cathode electrode 3 in contrast, the Schottky junction is biased reversely and the SiC-SBD comes to be in a blocking state (see, e.g., Yasui: par. [0056]). On this occasion, a depletion layer extending from the p-n junction between the p-type impurity regions 2 and 17 and the n-type impurity region 11 covers the Schottky junction and hence the electric field at the Schottky junction is relaxed. As a result, leak current reduces and a high voltage is blocked (see, e.g., Yasui: par. [0056]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the doped region of Yasui between wells that becomes depleted at a same voltage in the device of Rascuna, in order to reduce the leak current and block the high voltage.
Regarding claim 10, Rascuna shows (see, e.g., Rascuna: figs. 2, and 3A-3C) most aspects of the instant invention including a merged PiN Schottky (MPS) diode 50/100 (see, e.g., Rascuna: par. [0002]), comprising the semiconductor body 53/52/59’/64 and wherein the active area 52/59’/64. Rascuna shows (see, e.g., Rascuna: figs. 2, and 3A-3C) only shows a guard ring 105 (see, e.g., Rascuna: par. [0034]).
However, Rascuna fails (see, e.g., Rascuna: figs. 2, and 3A-3C) to show that the semiconductor body 53/52/59’/64 comprises a termination area adjacent to the active area 52/59’/64. Yasui, in a similar device to Rascuna, shows (see, e.g., Yasui: fig. 8) that the semiconductor body 10 comprises a termination area 31/32/33 arranged adjacent to the active area 16/17. Yasui also shows (see, e.g., Yasui: fig. 8) that by such a termination area 31/32/33, which is a JTE structure, provided around the active region 16/17, the electric field at the chip terminal end of a SiC-SBD is relaxed and hence a desired high withstand voltage can be secure (see, e.g., Yasui: par. [0057]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the termination area of Yasui in the device of Rascuna, in order to relax the electric field at the chip terminal end and to secure a desired high withstand voltage.
Regarding claim 17, Rascuna in view of Yasui shows (see, e.g., Rascuna: figs. 2, and 3A-3C) shows that the metal layer assembly 58/69 forms a first terminal of the MPS diode 50/100, wherein the MPS diode 50/100 further comprises a contact 56/57 arranged on the substrate 53, and wherein the contact 56/57 forms a second terminal of the MPS diode 50/100.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Rascuna in view of Miyake (US 2016/0300960).
Regarding claim 11, Rascuna shows (see, e.g., Rascuna: figs. 2, and 3A-3C) most aspects of the instant invention including a merged PiN Schottky (MPS) diode 50/100 (see, e.g., Rascuna: par. [0002]), comprising a plurality of wells 59’/59/104.
Hopwever, Rascuna fails (see, e.g., Rascuna: figs. 2, and 3A-3C) to show that each of the plurality of wells 59’/59/104 comprise a subregion having a higher dopant concentration than a remainder of the well 59’/59/104 for enabling an Ohmic contact with the metal layer assembly 58/69. Miyake, in a similar device to Rascuna, shows (see, e.g., Miyake: fig. 3) each of the plurality of wells 20 comprise a subregion 21 having a higher dopant concentration than a remainder of the well 20 for enabling an Ohmic contact with the metal layer 14 (see, e.g., Miyake: par. [0034]). Miyake also shows (see, e.g., Miyake: fig. 3) that since the p-type impurity density of the first region 21 is high, the barrier between the first region 21 and the anode electrode 14 is small (see, e.g., Miyake: par. [0034]). Due to this, when the diode turns on, the holes flow in easily from the anode electrode 14 to the p-type contact regions 20. Also, due to this, when the diode turns on, the depletion layer vanishes at a fast speed from within the n-type contact regions 25 and the p-type contact regions 20 (see, e.g., Miyake: par. [0034]). Thus, the diode has a fast response speed. Further, in the diode 10, no current flows in the p-type contact regions 20 when the diode is on (see, e.g., Miyake: par. [0034]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the plurality of wells of Miyake with a subregion having a higher dopant concentration than a remainder of the well in the device of Rascuna, in order to reduce the barrier between the sub-region and the metal electrode, and to make the diode faster.
Claim 16 are rejected under 35 U.S.C. 103 as being unpatentable over Rascuna in view of Yasui in further view of Masaki (JP 20100038414 A).
Regarding claim 16, Rascuna in view of Yasui shows (see, e.g., Rascuna: figs. 2, and 3A-3C) most aspects of the instant invention including a merged PiN Schottky (MPS) diode 50/100 (see, e.g., Rascuna: par. [0002]), comprising a doped region 64 and a plurality of wells 59’/59/104 each extend from the surface 52a of the semiconductor body 53/52/59’/64 and a doped region 64.
However, Rascuna in view of Yasui fails (see, e.g., Rascuna: figs. 2, and 3A-3C) to show that the wells 59’/59/104 of each pair of adjacently arranged wells 59’/59/104 have a spacing that increases from the center of the doped region 64 to the edge of the doped region 64. Masaki, in a similar device to Rascuna in view of Yasui, shows (see, e.g., Masaki: figs. 1 and 2) that the wells 59’/59/104 of each pair of adjacently arranged wells 40 have a spacing that increases from the center of the doped region 30 to the edge of the doped region 30. Masaki also shows (see, e.g., Masaki: figs. 1 and 2) that by arranging each pair of adjacent wells such as the spacing between adjacent wells increases from the center 80 of the doped region 30 to the edge 82 of the doped region 30, it makes the average resistance in the central section 80 high such that the amount of heat generated per unit volume per unit time in the central section 80 is reduced (see, e.g., Masaki: par. [0022] – [0030]; see especially par. [0030]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the plurality of wells of Masaki of each pair of adjacently arranged wells that have a spacing that increases from the center of the doped region to the edge of the doped region in the device of Rascuna in view of Yasui, in order to increase the average resistance in the central section high such that the amount of generated heat in the central section is reduced.
Allowable Subject Matter
Claims 2, and 12-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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