DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Figure 5 Group III in the reply filed on 02-23-2026 is acknowledged. The traversal is on the ground(s) that the limitation “fan out” of independent claims 1 and 18 do not read on Figure 3 Group I or Figure 4 Group II. This argument is found persuasive in light of the specification and thusly means the examiner will not interpret the increasing distances d1, d2 , and d3 of Figures 3 and 4 to be fanning out.
The election requirement is withdrawn.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-15, 17 are provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claims 1, 4, 15, and 17 of co-pending U.S. Patent application No. (18/467278). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are substantially similar in scope as demonstrated in the table below.
This is a provisional non-statutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim 1 – 18/467,258
Claim 1 – 18/467,278
A merged PIN Schottky (MPS) diode, comprising:
a semiconductor body including an active area, wherein the active area comprises:
a drift region of a first conductivity type; and
a plurality of wells of a second conductivity type different from the first conductivity type, wherein the plurality of wells are mutually spaced apart, each well forming a respective PN-junction with the drift region;
a metal layer assembly arranged on a surface of the semiconductor body and comprising at least one metal layer, wherein the metal layer assembly forms a plurality of Schottky contacts together with the drift region and a plurality of respective Ohmic contacts with the plurality of wells;
A merged PiN Schottky (MPS) diode, comprising:
a semiconductor body including an active area, wherein the active area comprises:
a drift region of a first conductivity type; and
a plurality of wells of a second conductivity type different from the first conductivity type, wherein the plurality of wells are mutually spaced apart, each well forming a respective PN-junction with the drift region; and
a metal layer assembly arranged on a surface of the semiconductor body and comprising at least one metal layer, wherein the metal layer assembly forms a plurality of Schottky contacts together with the drift region and a plurality of respective Ohmic contacts with the plurality of wells,
wherein, in an outward direction from a center of the active area, a spacing between adjacently arranged wells increases; and
and a spacing between adjacently arranged wells increases in an outward direction from a center of the active area; and
wherein the drift region comprises a doped region surrounding the plurality of wells and has a dopant concentration greater than that in a remainder of the drift region, and a dopant profile of the doped region is configured so that, for wells of each pair of adjacently arranged wells, the doped region between the wells becomes depleted at substantially a same voltage applied to the MPS diode.
Claim 4
wherein the plurality of wells are formed as strips extending parallel to the surface of the semiconductor body, and wherein the strips fan out in at least part of the active area.
The MPS diode according to claim 1, wherein the plurality of wells are formed as strips extending parallel to the surface of the semiconductor body, and wherein the strips fan out in at least part of the active area.
Claim 2
Claim 15
The MPS diode according to claim 1, wherein the active area comprises an inner region in which a spacing between adjacently arranged strips is substantially constant, and a fanout region surrounding the inner region in which a spacing between adjacently arranged strips increases in the outward direction.
The MPS diode according to claim 4, wherein the active area comprises an inner region in which a spacing between adjacently arranged strips is substantially constant, and a fanout region surrounding the inner region in which a spacing between adjacently arranged strips increases in the outward direction.
Claim 8
Claim 17
The MPS diode according to claim 2, wherein the active area further comprises an outer region surrounding the fanout region in which a spacing between adjacently arranged strips is substantially constant, and wherein the spacing between adjacently arranged strips in the outer region is greater than the spacing between adjacently arranged strips in the inner region.
The MPS diode according to claim 15, wherein the active area further comprises an outer region surrounding the fanout region in which a spacing between adjacently arranged strips is substantially constant, and wherein the spacing between adjacently arranged strips in the outer region is greater than the spacing between adjacently arranged strips in the inner region.
Claim 5
Claim 4
The MPS diode according to claim 1,
Claim 1 and Claim 4
wherein the drift region comprises a doped region surrounding the plurality of wells and having a dopant concentration that is greater than that in a remainder of the drift region, and wherein the doped region has a dopant profile that, for wells of each pair of adjacently arranged wells, the doped region between the wells becomes depleted at substantially a same voltage applied to the MPS diode.
Claim 1
Due to the provisional status of the double patenting rejection Claims 3, 4, 6, 7, 9-15, 17 are rejected to since they could be equated to claims in a manner presented below.
Claim 3 – 18/467,258
Claim 5 – 18/467,278
Claim 4
Claim 6
Claim 6
Claim 10
Claim 7
Claim 11
Claim 9
Claim 5
Claim 10
Claim 6
Claim 11
Claim 1
Claim 12
Claim 7
Claim 13
Claim 8
Claim 14
Claim 9
Claim 15
Claim 16
Claim 17
Claim 16
Allowable Subject Matter
Claim 18 is allowed.
The following is a statement of reasons for the indication of allowable subject matter: Examiner was unable to find prior art that read on the fan out structure and thusly believes that, after a few concerns listed above, this application contains allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. YASUI; Kan et al. (US-20180047855-A1), Sundaresan; Siddarth et al. (US-10840385-B1), RASCUNA; Simone et al. (US-20220028979-A1), Yu; Xiaotian et al. (US-20210328076-A1), Dun; Haiping et al. (US-20180138322-A1), MIYAKE; Hiroki et al. (US-20160300960-A1), Mieczkowski; Van et al. (US-20160093748-A1), Chen; Weize et al. (US-20140001594-A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAIME LYNN SPRENGER whose telephone number is (571)272-8444. The examiner can normally be reached Monday - Thursday, 7:30a.m. - 5:00p.m. ET..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAIME LYNN SPRENGER/Examiner, Art Unit 2893 /J.L.S./Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights