DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 09/14/2023, is/are in compliance with the provisions 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 6, 7, 9, 13-15 and 17 is/are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Kim, Yongho (PG Pub US 20210066251) herein referred to as Kim
As to claim 1, a semiconductor chip (first semiconductor chip C1/C2/C3 [0031, Kim] Fig. 1A and 1B) comprising:
a semiconductor substrate (substrate 100, [0038] Fig. 1B) having an active surface and a non-active surface (active and non-active surface, [0007], Fig. 1B) opposite to each other;
a plurality of through electrodes (1st through electrodes 125, [0007], Fig. 1B) passing through the semiconductor substrate (substrate 100, [0038] Fig. 1B);
a plurality of wiring structures (wiring structure formed in the first semiconductor device layer 110 against external shock or moisture [0039], Fig. 1B) on the active surface and electrically connected to the plurality of through electrodes (plurality of first through electrodes configured to pass through the first semiconductor substrate and the first semiconductor device layer and to be electrically connected, [0007], Fig. 1B);
an inter-wire insulating layer (insulating layer 240 , [0057] Fig. 1B) surrounding the plurality of wiring structures (wiring structures, on device layer 110 [0039];
a plurality of front chip connection pads (first front surface pads 124, [0038] Fig. 1B) electrically connected to the plurality of wiring structures;
a front insulating layer (first front surface insulating layer 123, [0038] Fig. 1B) surrounding the plurality of front chip connection pads, (124) on the inter-wire insulating layer (240);
a plurality of rear chip connection pads (first rear surface pads 122, [0029], Fig. 1B) on the non-active surface and electrically connected to the plurality of through electrodes; and
a rear insulating layer (first rear surface insulating layer 121, [0007], Fig. 1B) surrounding the plurality of rear chip connection pads, (122) on the non-active surface, wherein
the front insulating layer (123) includes a cover insulating portion (“the molding layer 160 may contact an edge of the upper surface of the first semiconductor chip C1” [0057]) covering a side surface of the inter-wire insulating layer (240) and
extending into the semiconductor substrate through the active surface. (“the molding layer 160 may contact an edge of the upper surface of the first semiconductor chip C1”. [0057])
As to claim 2, Kim teaches the elements of claim 1 as discussed above and further discloses the semiconductor chip of claim 1, wherein
only the cover insulating portion (160), the semiconductor substrate (100), and the rear insulating layer (121) are exposed at a side surface of the semiconductor chip (C1). (Fig. 1B Kim)
As to claim 6, Kim teaches a semiconductor package as discussed above, and further discloses:
a first semiconductor chip (C1/C2/C3 Kim [0031, Kim]) including a first semiconductor substrate (100 Kim) having a first active surface and a first non-active surface opposite to each other (active and non-active surface, [0007], Fig. 1B Kim),
a plurality of first through electrodes (125, Kim) passing through the first semiconductor substrate (100, Kim), a first front insulating layer (123, Kim) on the first active surface, and a first rear insulating layer (121, Kim) on the first non-active surface;
a second semiconductor chip (C2, [0007, Kim], “a second semiconductor chip including a second semiconductor substrate having an active surface and a non-active surface opposite to the active surface” Kim) including a second semiconductor substrate having a second active surface and a second non-active surface opposite to each other, and
a second front insulating layer (223, Kim) on the second active surface, the second active surface facing the first non-active surface and the second semiconductor chip (C2, Fig. 1B) being stacked on the first semiconductor chip; a second semiconductor device layer formed on the active surface of the second semiconductor substrate and including a circuit pattern; (“a second front surface insulating layer formed on the second semiconductor device layer and spaced apart from the second semiconductor substrate with the second semiconductor device layer interposed therebetween” [0007] Fig. 1B) and
a plurality of first bonding pads (122, Kim) between the first semiconductor chip (C1, Kim) and the second semiconductor chip (C2, Kim), surrounded by the first rear insulating layer (222, Kim) and the second front insulating layer (223, Kim), and
electrically connected to the plurality of first through electrodes, (125/225, Kim) wherein the second front insulating layer (223, Kim) includes a cover insulating portion (160, Kim) extending into the second semiconductor substrate (200, Kim) through the second active surface and covering a side surface of the second semiconductor chip (C2, Fig. 1B).
As to claim 7, Kim teaches the semiconductor package of claim 6, as discussed above, and further discloses wherein,
on the side surface of the second semiconductor chip (C2), the cover insulating portion (160, Kim) includes a single material (“The molding layer 160 may include, for example, an EMC” [0057]), and only the cover insulating portion is between the second active surface of the second semiconductor chip (C2) and the second semiconductor substrate (200, Kim)
As to claim 9, the semiconductor package of claim 6, wherein
the first semiconductor chip (C1) has a vertical cross-section having a rectangular shape, (See Fig. 1B, Kim) and the second semiconductor chip (C2) has a vertical cross-section having a trapezoidal shape (Trapezoid as defined by Webster “a four-sided geometric shape (quadrilateral) characterized by having at least one pair of parallel sides, known as bases.” See Fig. 1B, Kim ).
As to claim 13, Kim teaches the semiconductor package of claim 6, wherein
the second semiconductor chip (C2) further includes:
a plurality of wiring structures (224) plurality of wiring structures on device layer 110 that connect the plurality of individual devices to other wiring lines formed on the first semiconductor substrate, Kim) between the second active surface and the second front insulating layer (223, Kim) and electrically connected to the plurality of first bonding pads (122, Kim); and
an inter-wire insulating layer (240, Kim) surrounding the plurality of wiring structures, (224) wherein the cover insulating portion (160 Kim) covers a side surface of the inter-wire insulation layer (240, Kim).
As to claim 14, Kim teaches the semiconductor package of claim 13, as discussed above, and further discloses wherein
the second semiconductor chip (C2, Kim) further includes: a plurality of second through electrodes (225 Kim) passing through the second semiconductor substrate (200, Kim) and electrically connected to the plurality of wiring structures (224, Kim); and
a second rear insulating layer (221, Kim) on the second non-active surface, wherein only the cover insulating portion (160, Kim), the second semiconductor substrate (C2), and
the second rear insulating layer (221, Kim) are exposed at the side surface of the second semiconductor chip (C2, Kim).
As to claim 15, Kim teaches the semiconductor package of claim 14, as discussed above, and further discloses wherein
the first rear insulating layer (121, Kim) and the second front insulating layer (223, Kim) surround the plurality of first bonding pads (122, Kim) and are coupled to each other, and
the second semiconductor chip (C2, Kim) includes a first-second semiconductor chip (C3, Kim) and a second-second semiconductor chip (C4, Kim) stacked on the first-second semiconductor chip (C3, Kim)
the second rear insulating layer (221, Kim) of the first-second semiconductor chip (C3, Kim) and the second front insulating layer (223, Kim) of the second-second semiconductor chip (C4, Kim) are coupled to each other and surround a plurality of second bonding pads (222, Kim) between the first-second semiconductor chip (C3, Kim) and the second-second semiconductor chip (C4, Kim).
As to claim 17, Kim teaches a semiconductor package as discussed above, and further discloses comprising:
a high bandwidth memory (HBM) control die including a first semiconductor substrate having a first active surface and a first non-active surface opposite to each other ([0131] “The first to fourth semiconductor chips C1, C2, C3, and C4 may be memory devices or DRAM devices for implementing the HBM.”, Fig. 1B Kim ),
a plurality of first through electrodes (1st through electrodes 125, [0007], Fig. 1B Fig. 1B Kim) passing through the first semiconductor substrate, (substrate 100 ,[0007] Fig. 1B) a first front insulating layer (first front surface insulating layer 123, Fig. 1B) on the first active surface, and a first rear insulating layer (first rear surface insulating layer 121, [0007], Fig. 1B) on the first non-active surface;
a plurality of dynamic random access memory (DRAM) (“memory semiconductor chip such as dynamic random access memory (DRAM)” [0035] Fig. 1B Kim) dies
including a second semiconductor substrate (200, Fig. 1B Kim) having a second active surface and a second non-active surface opposite to each other, a plurality of second through electrodes passing through the second semiconductor substrate, a second front insulating layer (223, Fig. 1B Kim) on the second active surface, and a second rear insulating layer on the second non-active surface, the second active surface facing the first non-active surface, and
the plurality of DRAM dies being sequentially stacked on the HBM control die (“In FIGS. 1A and 1B, the semiconductor chip stack structure 10 in which the first to fourth semiconductor chips C1, C2, C3, and C4 are stacked is exemplarily illustrated”, [0036] Fig. 1B Kim) and having horizontal widths less than a horizontal width of the HBM control die (obvious);
a plurality of first bonding pads (first rear surface pads 122, Fig. 1B) between a lowermost DRAM die of the plurality of DRAM dies and the HBM control die and surrounded by the second front insulating layer (223, Kim) of the lowermost DRAM die of the plurality of DRAM dies and the first rear insulating layer ( “The first to fourth semiconductor chips C1, C2, C3, and C4 may be memory devices or DRAM devices for implementing the HBM.” [0131]) ; and
a plurality of second bonding pads between two adjacent DRAM dies among the plurality of DRAM dies, and surrounded by the second front insulating layer and the second rear insulating layer between the two adjacent DRAM dies among the plurality of DRAM dies, wherein the second front insulating layer includes a cover insulating portion extending into the second semiconductor substrate through the second active surface and covering a side surface of each of the DRAM dies, and only the cover insulating portion, the second semiconductor substrate, and the second rear insulating layer are exposed at the side surface of each of the DRAM dies. (Fig. 1B Kim)
the plurality of DRAM (C2-C4, used for processing, See [0133] Fig. 12) dies being sequentially stacked on the HBM control (C5 used for control, See [0131] Fig. 12) die and having horizontal widths less than a horizontal width of the HBM control die; "
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable by Kim, Yongho (PG Pub US 20210066251) herein referred to as Kim
As to claim 8, Kim teaches the semiconductor package of claim 6, as discussed above, and further discloses wherein
“the cover insulating portion (160) at a corner portion thereof and the corner portion being in contact with the second semiconductor substrate” (C2, Fig. 1B Kim).
Kim does not appear to expressly disclose " the cover insulating portion has a round shape at a corner portion "
Koroku teaches: “the cover insulating portion has a round shape (obvious) at a corner portion thereof and the corner portion being in contact with the second semiconductor substrate.”
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the cover insulating portion a round shape design choice at a corner portion of the Kim device, such as is designed in the Koroku device. In semiconductor encapsulation, rounding the edge of the encapsulation material (e.g., epoxy) instead of leaving it flat, creates a smoother interface, prevents stress points, reduces crack initiation (especially from thermal expansion), improves adhesion, and enhances long-term reliability so as to use an industrially tested and accepted device.
Claim(s) 3-4, 10, 11, 12, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, Yongho (PG Pub US 20210066251) herein referred to as Kim in view of Roesner et al. herein referred to as Roesner (US 9496193).
As to claim 3, Kim discloses the semiconductor chip of claim 2,
the side surface of the semiconductor chip (C1, Fig. 1B Kim)
Kim does not appear to expressly disclose “a side surface of the semiconductor substrate is a surface having a scallop”
Roesner teaches a scalloped edge on the side surface of a semiconductor chip. (scallop features 40 of surface structure 20 are formed using a Bosch deep reactive-ion etching (DRIE) process, col 3 lines 66-67, Fig. 1 Roesner).
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to employ the method of creating the semiconductor substrate scalloped edge from the Roesner device, in the Kim device so as to make a scalloped edge on the side of the semiconductor chip making an industrially tested and accepted device/process/material. Fabricating a rounded edge inhibits vertical travel of liquid bonding material along the sidewalls of the substrate, if necessary [col 3 lines 33-35, Roesner] The Kim/ Roesner combination discloses the elements of claim 3 as discussed above and further discloses a scalloped edge on the side of the semiconductor chip.
As to claim 4, Kim as combined with Roesner teaches the semiconductor chip of claim 3 as discussed above, and further discloses wherein,
the side surface of the semiconductor chip (C1), a side surface of the cover insulating portion and a side surface of the rear insulating layer are flat surfaces (Fig. 1B Kim)
As to claim 10, Kim as combined with Roesner teaches the semiconductor package of claim 6, as discussed above, and further discloses wherein,
the side surface of the second semiconductor chip (C2), a first portion of the side surface of the second semiconductor substrate has a surface having scallops (22 and 24 scallops of Fig 1. Roesner ) of , and
a second portion of the side surface of the second semiconductor substrate (C2) has a flat surface (Fig. 1B Kim).
As to claim 11, Kim as combined with Roesner teaches the semiconductor package of claim 10, as discussed above, and further discloses wherein
a side surface of the first semiconductor chip (C1 horizontal layer sides , Fig. 1B Kim) is a flat surface in its entirety.
As to claim 12, Kim as combined with Roesner teaches the semiconductor package of claim 10, wherein
a lower surface of the second semiconductor chip (C2, Fig. 1B Kim) facing the first semiconductor chip (C1, Fig. 1B Kim)
Kim as combined with Roesner does not appear to expressly disclose “a smaller horizontal width” (obvious) than an upper surface of the second semiconductor chip”.
However, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the horizontal widths of a lower surface of the second semiconductor chip, a smaller horizontal width than an upper surface of the second semiconductor chip” since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. Optimizing chip widths in semiconductor manufacturing is crucial for maximizing the number of functional chips (yield) per wafer, reducing manufacturing cost per chip and improving power efficiency.
As to claim 18, Kim as combined with Roesner teaches the semiconductor package of claim 17, wherein, of
the side surface of each of the DRAM dies, a side surface of the second semiconductor substrate (C2) is a surface having scallops, and
a side surface of the cover insulating portion (160, Kim) and a side surface of the second rear insulating layer are flat surfaces. (Fig. 1B Kim)
Claim(s) 5 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable by Kim, Yongho (PG Pub US 20210066251) herein referred to as Kim and further in view of Huang et al. (US 20230170258) herein referred to as Huang.
As to claim 5, Kim teaches the semiconductor chip of claim 1, wherein
“the side surface of the semiconductor chip (C2-C4), Kim has a first angle with respect to an upper surface of the front insulating layer” and
Kim does not appear to expressly disclose:
“a second angle with respect to a lower surface of the rear insulating layer, the second angle being less than the first angle”.
Huang does disclose a device layer (129) disposed on substrate (104), such that a second angle with respect to the lower surface, the second angle is less than the first angle (See Fig. 1A).
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make a second angle with respect to a lower surface of the rear insulating layer, the second angle being less than the first angle in the Km device as in the Huang device. The scalloped edge of (104 Huang) creates a first angle with respect to an upper surface of the device layer of (129 Huang). See Fig. 1A of Huang. Fabricating a rounded edge inhibits vertical travel of liquid bonding material along the sidewalls of the substrate, if necessary. The Kim/ Huang combination discloses the elements of claim 5 as discussed above and further discloses a scalloped edge on the side of the semiconductor chip.
As to claim 20, the Kim/Huang combination teaches the semiconductor package of claim 17, as discussed above and further teaches wherein
each of the plurality of DRAM dies facing the HBM control (C5 used for control, See [0131] Fig. 12) C2-C4, used for processing, See [0133] Fig. 12, Kim) die has a lower surface having a first horizontal width and an upper surface having a second horizontal width, and
the side surface of each of the plurality of DRAM dies has a first angle with respect to a lower surface of the second front insulating layer (223, Kim) and
a second angle with respect to an upper surface of the second rear insulating layer (221, Kim), the second angle being less than the first angle.
Kim does not appear to expressly disclose:” the first horizontal width being smaller (obvious) than the second horizontal width”
However, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the horizontal widths of the DRAM die less than a horizontal width of the HBM control die since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. Optimizing die widths in semiconductor manufacturing is crucial for maximizing the number of functional chips (yield) per wafer, reducing manufacturing cost per chip and improving power efficiency.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, Yongho (PG Pub US 20210066251) herein referred to as Kim, and further in view of Oh et al. (US 2023011200) herein referred to as Oh.
As to claim 16, Kim teaches the semiconductor package of claim 14, as discussed above,
However, Kim does not teach:
“each of the plurality of first bonding pads is a single body including a lower portion and an upper portion that are diffusion-bonded to each other”.
Oh does teach the plurality of bonding pads is a single body including a lower portion and an upper portion that are diffusion-bonded to each other”. Diffusion bonding is a solid-state joining process that uses heat and pressure to fuse two solid materials, typically metals,
without melting them.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to bond the plurality of pads of the Kim device in a single body using a diffusion bonded method to bond the lower portion, upper portion and bonding pads as is used in the Oh device, so as to use an industrially tested and accepted device/process/material.)
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, Yongho (PG Pub US 20210066251) herein referred to as Kim in view of Hong et al (US 10790264) herein referred to as Hong and further in view of Jang, Aenee (US 20220130799) herein referred to as Jang..
As to claim 19, Kim discloses the elements of claim the semiconductor package of claim 17 as discussed above.
Kim teaches “each of the plurality of first bonding pads and each of the plurality of second bonding pads” and “each of the first rear insulating layer, the second front insulating layer, and the second rear insulating layer”
However, Kim does not appear to expressly disclose
each of the plurality of first bonding pads and each of the plurality of second bonding pads include Cu, and
Nonetheless, Hong does teach a plurality of internal connection pads formed of copper (col 5 lines 18-20).
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make each of the plurality of first bonding pads and each of the plurality of second bonding pads include Cu. Copper is well known to be used in bonding pads and connectors for its excellent electrical/thermal conductivity, cost-effectiveness (vs. gold), high strength, and superior performance in high-current applications so as to use an industrially tested and accepted material.
Also, Kim does not appear to expressly disclose
“the first rear insulating layer, the second front insulating layer, and the second rear insulating layer includes silicon oxide. “
Nonetheless, Jang does teach an insulating layers made of silicon oxide ([0048, Jang]).
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the first rear insulating layer, the second front insulating layer, and the second rear insulating layer include silicon oxide. Silicon oxide layers are crucial in semiconductor manufacturing for providing excellent electrical insulation, preventing current leakage, and enabling precise transistor function so as to use an industrially tested and accepted material.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN SHAW MUSLIM whose telephone number is (571)270-0071. The examiner can normally be reached Mon-Fri 7 am - 4 pm.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897