DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 3 in the reply filed on 4/14/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-4, 6, 9, 12, 14, 16-17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US patent publication US 20190164899 A1 (Hu et al hereinafter Hu).
Regarding claim 1, Hu discloses a method, comprising: forming a photoresist layer (FIG. 17, photoresist 1700 is formed ¶ [0045]) over a wafer (semiconductor die 100 may be a device wafer or interposer wafer ¶ [0013]); aligning a first photomask (FIG. 17, mask 1710 is aligned ¶ [0045]) with a first area (FIG. 17, first active signal region 110A ¶ [0012]) of the wafer; performing a first exposure process (FIG. 17, an exposure process is performed with exposure 1720 ¶ [0045]) to a first portion of the photoresist layer (FIG. 17, photoresist 1700X portion overlapping stitching zone 110AB, which is inside first active signal region 110A ¶ [0045]) within the first area of the wafer; aligning a second photomask (FIG. 18, mask 1810 is aligned ¶ [0046]) with a second area of the wafer (FIG. 18, second active signal region 110B ¶ [0012]), wherein aligning the first photomask and aligning the second photomask are performed using an alignment mark (FIG. 12, alignment marks 300AB/500AB may be used to align masks 1710/1810 ¶ [0045-0046]) within a stitching zone (FIG. 12, alignment marks 300AB/500AB are in stitching zone 110AB ¶ [0045]) of the wafer, the stitching zone being an overlapping region of the first area and the second area (stitching zone 110AB is the overlap of regions 110A and 110B); performing a second exposure process (FIG. 18, exposure 1820 is performed ¶ [0046]) to a second portion of the photoresist layer within the second area of the wafer (FIG. 18, photoresist 1700M portion overlapping stitching zone 110AB, which is inside second active signal region 110B ¶ [0046]); and performing a development process (FIG. 19, developed photoresist 1700’ is formed from a development process the removes portions 1700X and 1700M ¶ [0048]) to remove the first and second portions of the photoresist layer.
Regarding claim 3, Hu discloses the limitations of claim 1 and further discloses performing a die singulation process (FIG. 33, a singulation process on a plurality of the disclosed dies is provided for ¶ [0055]) by sawing the wafer through scribe lines (FIG. 28, scribe lines 2830 ¶ [0055]) of the wafer to form a semiconductor die, wherein the alignment mark remain in the semiconductor die after the die singulation process is finished (FIG. 28, the singulation process leaves stitching region 110AB intact, which indicates that the alignment marks 300AB/500AB in region 110AB remain after the singulation ¶ [0055]).
Regarding claim 4, Hu discloses the limitations of claim 1 as detailed above and further discloses that the alignment mark extends into the first area of the wafer (FIG. 12, alignment marks 300AB/500AB extend into first active signal region 110A, defined as the first area of the wafer in the foregoing discussion of claim 1; the present claim does not require that the alignment mark extend into a sub-area of the first area which is exclusive of the stitching area).
Regarding claim 6, Hu discloses the limitations of claim 1 as detailed above and further discloses forming semiconductor devices (FIG. 2, semiconductor integrated circuit devices 210 are formed ¶ [0013]) over the first area and the second area of the wafer, and wherein the stitching zone of the wafer is free of semiconductor devices (FIG. 2, integrated circuit devices 210 are provided in regions 110A and 110B, but are not provided in stitching region 110AB).
Regarding claim 9, Hu discloses a method, comprising: forming a photoresist layer (FIGS. 5, 8, and 12, photoresist 300 is formed ¶ [0026-0035]) over a wafer (semiconductor die 100 may be a device wafer or interposer wafer ¶ [0013]); performing a first exposure process (FIGS. 3-4, an exposure process is performed with exposure 320 ¶ [0026-0027]), through a first photomask (FIGS. 3-4, exposure 320 is performed through mask 310 ¶ [0026-0027]), to a first portion (FIGS. 3-4, 300A and 303A portions of photoresist 300 ¶ [0026-0027]) and a second portion (FIGS. 3-4, 315A, 315AB, and 300AB portions of photoresist 300 ¶ [0026-0027]) of the photoresist layer within a first area (FIGS. 3-4, first active signal region 110A, which includes portions 300A, 303A, 315A, 315AB, and 300AB ¶ [0012]) of the wafer, wherein the first photomask has an alignment mark pattern (FIGS. 3 and 5, alignment marks 300AB/500AB are in stitching zone 110AB, formed from patterns in mask 310 which correspond to second portion regions 300AB and 500AB ¶ [0026-0028]) correspond to the second portion of the photoresist layer; performing a second exposure process (FIGS. 6-8, exposure 620 is performed ¶ [0029-0031]), through a second photomask (FIGS. 6-7, exposure 620 is performed through mask 610 ¶ [0029-0030]), to a third portion (FIGS. 6-7, portions 300B, 318B, and 315B ¶ [0029-0030]) of the photoresist layer within a second area (FIGS. 6-7, second active signal region 110B ¶ [0012]) of the wafer, wherein the second portion of the photoresist layer is within a stitching zone of the wafer (FIGS. 6-7, 315A, 315AB, and 300AB portions of photoresist 300 include portions 315AB and 300AB in stitching zone 110AB, where regions 110A and 110B overlap), the stitching zone being an overlapping region of the first area and the second area; and performing a development process to remove the first, second, and third portions of the photoresist layer to form a patterned photoresist layer (FIG. 13, developed photoresist 300’ is formed from a development process the removes portions of photoresist 300 treated by the exposure processes ¶ [0038]).
Regarding claim 12, Hu discloses the limitations of claim 9 as detailed above, and further discloses that the second portion of the photoresist layer extends into the first area of the wafer (FIGS. 3-4, the claimed ‘second portion’, understood to include 315A portion of photoresist 300, extends into the first active signal region 110A of the wafer).
Regarding claim 14, Hu discloses the limitations of claim 9 as detailed above, and further discloses forming semiconductor devices (FIG. 2, semiconductor integrated circuit devices 210 are formed ¶ [0013]) over the first area and the second area of the wafer, and wherein the stitching zone of the wafer is free of semiconductor devices (FIG. 2, integrated circuit devices 210 are provided in regions 110A and 110B, but are not provided in stitching region 110AB).
Regarding claim 16, Hu discloses a method, comprising: forming semiconductor devices (FIG. 2, semiconductor integrated circuit devices 210 are formed ¶ [0013]) within a first device region (annotated FIG. 12 below, first active signal region 110A excluding strip labeled “Non-device region portion of substrate” ¶ [0012]) and a second device region (annotated FIG. 12, second active signal region 110B excluding the straight-line strip labeled “Non-device region portion of substrate” ¶ [0012]) of a substrate (FIG. 2, substrate 200 includes the aforementioned regions ¶ [0013]), and absent within a non-device region (FIG. 2 and annotated FIG. 12, devices 210 are absent from strip labeled “Non-device region portion of substrate” in stitching region 110AB) of the substrate, wherein the non-device region separates the first device region from the second device region (annotated FIG. 12, strip labeled “Non-device region portion of substrate” separates the main bodies of device regions 110A and 110B from each other); forming an alignment mark (FIGS. 12 and 17, alignment marks 300AB/500AB are formed over “Non-device region portion of substrate” ¶ [0028, 0045]) over the non-device region of the substrate, wherein a portion of the alignment mark extends into the first device region of the substrate (annotated FIG. 12, an upper portion of alignment marks 300AB/500AB extend into region 110A); and forming features over the first and second device regions using the alignment mark (FIGS. 17-18, masks 1710 and 1810 are formed using the alignment mark, among other features ¶ [0045-0046]).
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Regarding claim 17, Hu discloses the limitations of claim 16 as detailed above and further discloses that the non-device region is a strip region extending continuously from one side of substrate to another side of the substrate (annotated FIG. 12 above, the designated “Non-device region portion of substrate” is a strip region extending continuously from the left to right sides of the substrate).
Regarding claim 21, Hu discloses the limitations of claim 16 as detailed above and further discloses that another portion of the alignment mark extends into the second device region of the substrate (annotated FIG. 12, a lower portion of alignment marks 300AB/500AB extend into region 110B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over US patent publication US 20190164899 A1 (Hu et al hereinafter Hu) as applied to claim 6 above, and further in view of US 20210313292 A1 (Wang et al hereinafter Wang).
Hu discloses the limitations of claim 6 as detailed above, but did not explicitly disclose that the alignment mark overlaps at least one of the semiconductor devices.
However, Wang discloses methods for forming devices on wafers (the methods used to form the embodiments discussed in ¶ [0039]) which comprise an alignment mark (FIG. 4B, alignment pattern AP ¶ [0039]) which overlaps at least one semiconductor device (FIG. 4B, semiconductor devices 120a and 120b; while not shown in FIG. 4B, a non-shown embodiment wherein alignment pattern AP overlaps both semiconductor devices 120a and 120b is explicitly contemplated). Having taught a number of different embodiments for the overlapping property of the alignment mark, Wang demonstrates that the selection of the alignment mark’s size and positional overlap relative to other device features is a result-effective variable which may be adjusted based on various practical concerns (e.g. increasing size to improve the detection capability, or decreasing size to reduce the amount of etching or fill material required).
Hu and Wang both pertain to the field of methods for forming devices on wafers, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the method of Hu in view of Wang such that the alignment mark overlaps at least one of the semiconductor devices, in order to form an alignment mark with increased size to improve its detection capability.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Hu as applied to claim 9 above, and further in view of an obvious modification to the disclosure of Hu.
Regarding claim 10, Hu discloses the limitations of claim 9 as detailed above, and further forming a dielectric layer (FIG. 2, dielectric IMD layer 250 is formed over substrate 200 of wafer 100 before photoresist 300 is formed ¶ [0024]) over the wafer prior to forming the photoresist layer; performing an etching process to the dielectric layer through the patterned photoresist layer (FIG. 13, an etching process is performed on patterned IMD layer 250’ through patterned photoresist 300’ ¶ [0039]) to form openings in the dielectric layer, wherein a pattern of the openings within the stitching zone of the wafer corresponds to the alignment mark pattern of the first photomask (FIGS. 12-13, the opening trenches 1300 include portions where alignment marks 300AB/500AB are present ¶ [0039]); and filling the openings of the dielectric layer with a material (FIG. 14, conductive lines 1400 are formed in the trenches 1300 of patterned IMD 250’ ¶ [0040]). Hu did not explicitly describe a step wherein the material filled in the openings within the stitching zone of the wafer forms an alignment mark, such a detail not being a point of particular emphasis for the disclosure of their invention. Hu did show FIG. 12 being the last “schematic top view” (¶ [0035]) of photoresist 300, and FIG. 6 was the last cross-sectional view which overlapped with an exposed portion/alignment mark (portion/mark 305AB ¶ [0029]), and Hu also teaches that cross-sectional views subsequent to FIG. 13 correspond to line B-B of FIG. 8 (¶ [0038]), which does not illustrate a cross-sectional view of the alignment marks, and also notes that a person skilled in the art may “readily extrapolate the indicated processing to structures that may be produced in other active signal regions” (¶ [0038]).
Further, since FIG. 12 illustrated the opening in photoresist 300 (¶ [0035]) which included the openings which Hu characterizes as being used to form alignment marks after further processing (FIG. 12, 300AB, 500AB, 305AB ¶ [0028]), a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to form the alignment marks in the openings designated as alignment mark openings concurrently with the “filling the openings of the dielectric layer with a material” step described in Hu (¶ [0040]), in order to prepare the alignment marks for the further processing steps in the device’s processing (e.g. aligning masks 1710/1810 ¶ [0045-0046]), since the alignment mark openings are exposed at the same time as the metal line openings which were illustrated as filled in FIG. 14 and Hu taught that a person skilled in the art may “readily extrapolate the indicated processing to structures that may be produced in other active signal regions”.
Regarding claim 11, Hu discloses the limitations of claim 10 as detailed above and further discloses performing a die singulation process (FIG. 33, a singulation process on a plurality of the disclosed dies is provided for ¶ [0055]) by sawing the wafer through scribe lines (FIG. 28, scribe lines 2830 ¶ [0055]) of the wafer to form a semiconductor die, wherein the alignment mark remain in the semiconductor die after the die singulation process is finished (FIG. 28, the singulation process leaves stitching region 110AB intact, which indicates that the alignment marks 300AB/500AB in region 110AB remain after the singulation ¶ [0055]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Hu as applied to claim 16 above, and further in view of an obvious modification to the disclosure of Hu.
Hu discloses the limitations of claim 16 as detailed above and further discloses forming a back-end-of-line (BEOL) structure (FIG. 28, layers 1400, 2200, 2210, 2300, 2320, and 2340 among others form a BEOL structure above devices 210 ¶ [0049-0055]) over the semiconductor devices, the BEOL structure comprises a dielectric layer (patterned IMD layer 250’ is a dielectric layer in the BEOL structure ¶ [0039]) and metal features in the dielectric layer (FIG. 14, metal features 1400 are formed in trenches of patterned IMD 250’ ¶ [0040]). Hu did not explicitly state that the alignment mark is formed within the dielectric layer. such a detail not being a point of particular emphasis for the disclosure of their invention. Hu did show FIG. 12 being the last “schematic top view” (¶ [0035]) of photoresist 300, and FIG. 6 was the last cross-sectional view which overlapped with an exposed portion/alignment mark (portion/mark 305AB ¶ [0029]), and Hu also teaches that cross-sectional views subsequent to FIG. 13 correspond to line B-B of FIG. 8 (¶ [0038]), which does not illustrate a cross-sectional view of the alignment marks, and also notes that a person skilled in the art may “readily extrapolate the indicated processing to structures that may be produced in other active signal regions” (¶ [0038]).
Further, since FIG. 12 illustrated the opening in photoresist 300 (¶ [0035]) which included the openings which Hu characterizes as being used to form alignment marks after further processing (FIG. 12, 300AB, 500AB, 305AB ¶ [0028]), a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to process the device of Hu such that the alignment mark is formed within the dielectric layer, in order to prepare the alignment marks for the further processing steps in the device’s processing (e.g. aligning masks 1710/1810 ¶ [0045-0046]), since the alignment mark openings are exposed at the same time as the metal line openings which were illustrated as filled in FIG. 14 and Hu taught that a person skilled in the art may “readily extrapolate the indicated processing to structures that may be produced in other active signal regions”.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Hu as applied to claim 17 above, and further in view of Wang.
Hu discloses the limitations of claim 17 as detailed above but does not further disclose that the portion of the alignment mark vertically overlaps at least one of the semiconductor devices.
However, Wang discloses methods for forming devices on wafers (the methods used to form the embodiments discussed in ¶ [0039]) which comprise an alignment mark (FIG. 4B, alignment pattern AP ¶ [0039]) which overlaps at least one semiconductor device (FIG. 4B, semiconductor devices 120a and 120b; while not shown in FIG. 4B, a non-shown embodiment wherein alignment pattern AP overlaps both semiconductor devices 120a and 120b is explicitly contemplated). Having taught a number of different embodiments for the overlapping property of the alignment mark, Wang demonstrates that the selection of the alignment mark’s size and positional overlap relative to other device features is a result-effective variable which may be adjusted based on various practical concerns (e.g. increasing size to improve the detection capability, or decreasing size to reduce the amount of etching or fill material required).
Hu and Wang both pertain to the field of methods for forming devices on wafers, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the method of Hu in view of Wang such that the portion of the alignment mark vertically overlaps at least one of the semiconductor devices, in order to form an alignment mark with increased size to improve its detection capability.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Hu as applied to claim 16 above, and further in view of US patent US 6660612 B1 (Chang et al hereinafter Chang).
Hu discloses the limitations of claim 16 as detailed above but does not further disclose that the alignment mark comprises a grating of periodic structures.
However, Chang discloses a semiconductor device (Abstract) formed on a wafer (Col. 5 lines 6-16) and comprising alignment marks (FIGS. 4-8 illustrate registration features 400, 500, 600, 700, and 800 each of which include alignment marks Col. 5 lines 17-60), wherein the alignment marks may be configured as solid blocks (FIG. 4, alignment marks 401, 403, 405, and 407, which have an analogous solid-block structure to the alignment marks disclosed in Hu) or alternatively as a grating of periodic structures (FIGS. 5-7 each present configurations of alignment marks having periodic grating structures 509, 601, or 703). Chang also teaches that different spacings between the trench structures of the alignment marks may provide varied physical support of the device and alignment accuracy (Col. 6 lines 14-50).
Hu and Chang both pertain to the field of methods for forming devices on wafers, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the method of Hu in view of Chang such that the alignment mark comprises a grating of periodic structures, as Chang has demonstrated such a configuration to be a known and alternative design structure, which may further balance physical support of the device and alignment accuracy.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Hu as applied to claim 21 above, and further in view of Wang.
Hu discloses the limitations of claim 21 as detailed above but does not further disclose that the alignment mark vertically overlaps the semiconductor devices in both the first device region and the second device region.
However, Wang discloses methods for forming devices on wafers (the methods used to form the embodiments discussed in ¶ [0039]) which comprise an alignment mark (FIG. 4B, alignment pattern AP ¶ [0039]) which overlaps semiconductor devices in a first and second device region (FIG. 4B, semiconductor devices 120a and 120b in their respective regions; while not shown in FIG. 4B, a non-shown embodiment wherein alignment pattern AP overlaps both semiconductor devices 120a and 120b is explicitly contemplated). Having taught a number of different embodiments for the overlapping property of the alignment mark, Wang demonstrates that the selection of the alignment mark’s size and positional overlap relative to other device features is a result-effective variable which may be adjusted based on various practical concerns (e.g. increasing size to improve the detection capability, or decreasing size to reduce the amount of etching or fill material required).
Hu and Wang both pertain to the field of methods for forming devices on wafers, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the method of Hu in view of Wang such that the alignment mark vertically overlaps the semiconductor devices in both the first device region and the second device region, in order to form an alignment mark with increased size to improve its detection capability.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Hu in view of Wang as applied to claim 22 above, and further in view of US patent publication US 20100144063 A1 (Furumiya et al hereinafter Furumiya).
Hu in view of Wang discloses the limitations of claim 22 as detailed above but does not further disclose forming the alignment mark further comprises forming another alignment mark over a scribe line region that surrounds the first device region and the second device region, wherein the another alignment mark non-overlaps the first device region and the second device region. Hu does teach that scribe line regions surround the first device region and the second device region when forming and performing singulation on a plurality of their disclosed devices (FIG. 28, scribe lines 2830 drawn up to perform singulation ¶ [0055]).
Further, Furumiya discloses a method of forming a semiconductor device (the method for forming the device of FIG. 4 ¶ [0013-0016]) which includes forming another alignment mark (FIG. 4, alignment mark 108 ¶ [0027]) over a scribe line region (FIG. 4, scribe line region 106, which surrounds semiconductor device regions 104 ¶ [0027]) that surrounds the first device region and the second device region, wherein the another alignment mark non-overlaps the first device region and the second device region (FIG. 4, alignment mark 108 does not overlap device regions 104). Further, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to include a scribe-line region alignment mark in order to help ensure the dicing/singulation process is performed accurately.
Hu, Wang, and Furumiya all pertain to the field of methods for forming devices on wafers, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the method of Hu in view of Wang further in view of Furumiya to include forming the alignment mark further comprises forming another alignment mark over a scribe line region that surrounds the first device region and the second device region, wherein the another alignment mark non-overlaps the first device region and the second device region, in order to include a scribe-line region alignment mark in order to help ensure the dicing/singulation process is performed accurately.
Claims 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Hu as applied to claim 16 above, and further in view of US patent publication US 20150108611 A1 (Kumagai et al hereinafter Kumagai).
Regarding claim 24, Hu discloses the limitations of claim 16 as detailed above but does not further disclose that the first device region and the second device region are spaced apart from each other through a shallow trench isolation structure within the non-device region. Hu does however teach that a shallow trench isolation structure may be formed in substrate 200 to isolate active regions in substrate 200 (non-illustrated shallow trench isolation structures STI, ¶ [0014]), but does not further elaborate on particular placement of the STI structures, such details not of particular emphasis in the disclosure of their invention.
However, Kumagai discloses a method of forming a semiconductor device (a method to form the device of FIG. 3 ¶ [0015]) which comprises a plurality of semiconductor devices (FIG. 3, transistors formed of gate electrodes 15, source drain regions 16, plugs 17, local wirings 19 ¶ [0114-0116]) each of which are separated from one another by a shallow trench isolation structure (FIG. 3, STI insulating film 14 ¶ [0114]), which is used to partition the semiconductor devices (¶ [0114]).
Hu and Kumagai both pertain to the field of forming devices on wafers, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the method of Hu in view of Kumagai to include the first device region and the second device region are spaced apart from each other through a shallow trench isolation structure within the non-device region, in order to partition the semiconductor devices from one another as was illustrated by Kumagai, for example to mitigate the possibility of parasitic capacitance between the devices in the first and second device regions.
Regarding claim 25, Hu in view of Kumagai discloses the limitations of claim 24 as detailed above, and they further disclose that the alignment mark vertically overlaps the shallow trench isolation structure within the non-device region (in view of the combination of Hu and Kumagai, the alignment marks 300AB/500AB in non-device stitching region 110AB of Hu FIG. 12 will overlap an STI structure between devices in the first and second device regions of Hu, as may be illustrated by STI insulating film 14 of Kumagai FIG. 3 being overlapped by alignment mark 3, Kumagai ¶ [0113]).
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US patent publications US 20230053037 A1, US 20220246537 A1, US 20220059559 A1, US 20210167282 A1, and US 20190057939 A1.
Conclusion
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/E.R.C./Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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