The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
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DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of the embodiment of figures 1-8 in the reply filed on 07/15/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 7 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There is no support in the specification (and especially in the embodiment of figures 1-8) for the claimed limitation of another one contact penetrating a portion of the second stopper insulating layer provided to be opposed to an uppermost surface of the second stacked portion in the first direction, without penetrating the second interlayer insulating layer”, as recited in claim 7, because the detailed discerption does not mention the above elements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-9, 11-12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Totoki et al. (11,488,975).
Regarding claims 1 and 11, Totoki et al. teach in figure 26 and related text a semiconductor memory device comprising:
a stacked body including a first stacked portion 132-146 including a plurality of first conductive layers 146 stacked to be apart from each other in a first direction and having a first end portion stepwise processed along a second direction crossing the first direction, and a second stacked portion 232-246 provided on an upper layer side of the first stacked portion, including a plurality of second conductive layers 246 stacked to be apart from each other in the first direction, and having a second end portion arranged beside the first end portion in the second direction and stepwise processed along the second direction;
a plurality of pillar structures 82 each extending along the first direction in the stacked body;
a first interlayer insulating layer 165 covering the first end portion;
a second interlayer insulating layer 265 provided on an upper layer side of the first interlayer insulating layer and covering the second end portion;
a first stopper insulating layer 170 provided at least between the first interlayer insulating layer 165 and the second interlayer insulating layer 265 and above the first end portion, including a first portion extending flat along a plane perpendicular to the first direction above the first end portion throughout the first end portion in the second direction;
a second stopper insulating layer 270 including at least a first portion provided on an upper layer side of the second interlayer insulating layer 265 and above the second end portion;
a plurality of first contacts 50, 60L (see figure 10E) penetrating the second interlayer insulating layer, the first portion of the first stopper insulating layer and the first interlayer insulating layer, and connected to different first conductive layers, respectively, of the plurality of first conductive layers; and
a plurality of second contacts (another 50, 60L) penetrating the first portion of the second stopper insulating layer and the second interlayer insulating layer, and connected to different second conductive layers, respectively, of the plurality of second conductive layers.
Totoki et al. do not explicitly state that the plurality of pillar structures each including a semiconductor layer, and wherein the first and second stopper insulating layers are formed of a material with a main component which is different from that of the material of the first interlayer insulating layer and that of the material of the second interlayer insulating layer. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the plurality of pillar structures wherein each including a semiconductor layer, and to form the first and second stopper insulating layers of silicon nitride, in Totoki et al.’s device, in order to simplify the processing of making the device (by using conventional semiconductor material) and in order to provide better protection to the device (by using silicon nitride), respectively.
Regarding the claimed limitations of using specific materials, it is noted that substitution of materials is not patentable even when the substitution is new and useful. Safetran Systems Corp. v. Federal Sign & Signal Corp. (DC NIII, 1981) 215 USPQ 979.
It is further held that it is within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007) (“The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.”).
Regarding claim 2, Totoki et al. teach in figure 26 and related text a plurality of third contacts (another 50,60L) penetrating a second portion of the second stopper insulating layer provided to be opposed to an uppermost surface of the second stacked portion in the first direction, and each connected to the semiconductor layer of a respective pillar structure of the plurality of pillar structures.
Regarding claim 5, Totoki et al. teach in figure 26 and related text that the plurality of first contacts further penetrate a third portion of the second stopper insulating layer provided on an upper layer side of the second interlayer insulating layer and above the first end portion.
Regarding claims 6 and 12, Totoki et al. teach in figure 26 and related text one contact 84 penetrating the second interlayer insulating layer 265 provided to be opposed to an uppermost surface of the first stacked portion in the first direction, without penetrating the first interlayer insulating layer, and connected to an uppermost first conductive layer of the plurality of first conductive layers, but does not teach that said one contact 84 penetrating a portion of the first stopper insulating layer 170. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the plurality of pillar structures wherein each including a semiconductor layer, and to form that said one contact penetrating a portion of the first stopper insulating layer, in Totoki et al.’s device, in order to improve the contact resistance of the device.
Regarding claim 7, Totoki et al. teach in figure 26 and related text another one contact 84 (the most left contact) penetrating a portion of the second stopper insulating layer 270 provided to be opposed to an uppermost surface of the second stacked portion in the first direction, without penetrating the second interlayer insulating layer, and connected to an uppermost second conductive layer of the plurality of second conductive layers.
Regarding claim 8, Totoki et al. do not teach that the first stopper insulating layer and the second stopper insulating layer are formed of a same material.
would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first stopper insulating layer and the second stopper insulating layer of a same material, in Totoki et al.’s device, in order to simplify the processing steps of making the device.
Regarding claim 9, Totoki et al. teach in figure 26 and related text a level of upper ends of the plurality of first contacts in a height direction and a level of upper ends of the plurality of second contacts in the height direction are substantially identical to each other.
Regarding claim 16, Totoki et al. teach in figure 26 and related text the first stopper insulating layer 170 is not provided between the first stacked portion and the second stacked portion (see the left side in figure 9).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
9/19/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
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