DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 03/23/2026 has been entered.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Non-Final Reject" filed on 03/23/2026, related to “neither Glenn nor Kitnarong however disclose "iii) plating the exposed portion of the at least two terminals with a metal plating material ... v) plating the exposed plated portion of the at least two terminals with a further metal plating material... as recited in claim 1”, have been fully considered, but the arguments are not persuasive. Glenn reference (US 20020038714 A1) disclose a frame made of copper in [0030] and including plating of copper on the frame in [0011], Figs. 1,8, but it does not disclose an additional plating with a further metal plating material, however Kitnarong reference (US 20200211936 A1) discloses a tin electroplating process on exposed copper surfaces of a leadframe in [0079], Fig. 9A. Since Glenn’s frame and Kitnarong’s frame are made of copper, it would be obvious that Glenn looking for an additional plating process for improving solder connection of such IC packages to a PCB or other structure ([0002], Kitnarong), to select the tin plating process disclosed by Kitnarong, see detail below.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1,4-5 and 10-11 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Glenn (US 20020038714 A1, hereinafter Glenn, of the record) in view of Kitnarong et al. (US 20200211936 A1, hereinafter Kitnarong, of the record).
Re: Independent Claim 1, Glenn discloses a method for manufacturing a semiconductor package assembly, the method comprising the steps of:
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Glenn’s Figure 8-Annotated.
i) forming at least one semiconductor package (a completed package in [0024,0061], Figs. 1,8) by the following sub-steps:
i1) providing a lead frame (20 leadframe including frame 21 and die pad 24 and tabs 30 in [0007,0032-0033, 0035,0063], Figs. 1,2,8) made from a metal material (20 made of copper in [0030], Figs. 1,2,8) having a first frame side (upper surface of 20(24)(30) Figs. 2,8-Annotated) and a second frame side (lower surface of 20(24)(30) Figs. 2,8-Annotated) opposite to the first frame side (upper surface of 20(24)(30) Figs. 2,8-Annotated) and having a plurality of terminals (30 tabs in [0007,0035,0063], Figs. 1,2,8);
i2) providing at least one silicon die structure (56 integrated circuit die in [0008,0066], Figs. 1,8) having a first die side (upper surface of 56 Fig. 8-Annotated) and a second die side (lower surface of 56 Fig. 8-Annotated) opposite to the first side (upper surface of 56 Fig. 8-Annotated) with the second die side (lower surface of 56 Fig. 8-Annotated) on the first frame side (upper surface of 24 a portion of 20(24)(30) Figs. 2,8-Annotated) of the lead frame (56 on die pad 24 in [0008,0032-0033, 0066], Figs. 1,8);
i3) electrically and mechanically connecting (a bond wire 58 connecting electrically and mechanically the die 56 with tabs 30 in [0009,0073], Figs. 1,8) the at least one silicon die structure (56 Fig. 8) to the plurality of terminals (30 Figs.2, 8) of the lead frame (20 Figs. 2,8); and
ii) encapsulating (applies a viscous encapsulant material onto the upward facing first surface of the leadframe in [0010,0058], Figs. 1,8) the at least one silicon die structure (56 Fig. 8) and the plurality of terminals (30 Figs.2, 8) with a molding resin (40 encapsulant material in [0058], Figs. 1,8) leaving at least a portion of at least two terminals (30 Figs.2, 8) exposed ([0011], Figs. 1), thereby forming at least one encapsulated semiconductor package assembly (Figs. 1,8); wherein the method further comprises the step of:
iii) plating (plates the exposed surfaces of the leadframe, including the exposed second surfaces of the tabs with a metal, such as copper in [0011], Figs. 1,8) the exposed portion of the at least two terminals (30 Figs.2, 8) with a metal plating material (copper in [0011]), with the metal plating material being the same as the metal material of the lead frame (20 Figs. 2,8, made of copper in [0030]).
Glenn does not expressly disclose the step wherein v) plating the exposed plated portion of the at least two terminals with a further metal plating material different from the metal plating material used in the plating step iii).
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Kitnarong’s Figure 9A-Annotated.
However, in the same manufacturing of the semiconductor device field of endeavor, Kitnarong discloses the step of plating the exposed plated portion (Kitnarong: tin electroplating process on exposed copper surfaces of leadframe strip 822 of 860 in [0079], Fig. 9A) of the at least two terminals (Kitnarong: 860 die attach pads in [0077], Fig. 9A) with a further metal plating material (Kitnarong: Tin in [0079]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Kitnarong’s method of plating the exposed plated portion of the at least two terminals with a further metal plating material different from the metal plating material to Glenn’s method to have the step wherein v) plating the exposed plated portion of the at least two terminals with a further metal plating material different from the metal plating material used in the plating step iii) for improved solder connection of such IC packages to a PCB or other structure ([0002], Kitnarong).
Re: Claim 4, Glenn modified by Kitnarong discloses the method for manufacturing a semiconductor package assembly according to claim 1, further comprising the step of: vi) after step v), singulating (Glenn: cuts the encapsulated portions of the leadframe with a saw in [0012], Figs. 1-2,7) the encapsulated semiconductor package from the lead frame (Glenn: 20 Figs. 2,8), thereby forming a single semiconductor package assembly (Glenn: Figs. 1,7).
Re: Claim 5, Glenn modified by Kitnarong discloses a semiconductor package assembly (Glenn’s package Fig. 8 modified by Kitnarong, see claim 1 rejection) composed of a silicon die structure electrically and mechanically attached to at least two terminals of the plurality of terminals and encapsulated by a molding resin so that a portion of the at least two terminals are exposed, and wherein the exposed portions of the at least two terminals are plated with a metal plating material according to the method steps of claim 1 (Glenn’s package Fig. 8 modified by Kitnarong, see claim 1 rejection).
Re: Claim 10, Glenn modified by Kitnarong discloses a semiconductor package assembly (Glenn’s package Fig. 8 modified by Kitnarong, see claims 1 and 4 rejections) composed of a silicon die structure electrically and mechanically attached to at least two terminals of the plurality of terminals and encapsulated by a molding resin so that a portion of the at least two terminals are exposed, and wherein the exposed portions of the at least two terminals are plated with a metal plating material according to the method steps of claim 4 (Glenn’s package Fig. 8 modified by Kitnarong, see claims 1 and 4 rejections).
Re: Claim 11, Glenn modified by Kitnarong discloses the semiconductor package assembly according to claim 5, wherein the semiconductor package assembly (Glenn’s package Fig. 8 modified by Kitnarong, see claims 1 and 4 rejections) is a leadless semiconductor package assembly (Glenn: the tabs 30 are the contacts of the package in [0035], Figs. 2, 8).
Claim(s) 2 and 7 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Glenn in view of Kitnarong and further in view of Wang et al. (US 20220157756 A1, hereinafter Wang, of the record).
Re: Claim 2, Glenn modified by Kitnarong discloses the method for manufacturing a semiconductor package assembly according to claim 1,
Glenn modified by Kitnarong does not expressly disclose wherein step iii) further comprises plating the exposed portion of the at least two terminals with a layer of 30-50 µm of metal plating material.
However, in the same manufacturing of semiconductor device field of endeavor, Wang discloses a layer (12 first layer made of copper in [0037], Fig. 1) of 30-50 µm (greater than 10 microns in [0037], Fig. 1) of metal plating material.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Wang’s method of a layer of 30-50 µm of metal plating material to the combination of the Glenn and Kitnarong method to obtain wherein step iii) further comprises plating the exposed portion of the at least two terminals with a layer of 30-50 µm of metal plating material to electrically couple with a printed circuit board or other surfaces within an electronic device ([0038], Wang).
Re: Claim 7, Glenn modified by Kitnarong and Wang discloses the method for manufacturing a semiconductor package assembly according to claim 2, further comprising the step of: vi) after step v), singulating (Glenn: cuts the encapsulated portions of the leadframe with a saw in [0012], Figs. 1-2,7) the encapsulated semiconductor package from the lead frame (Glenn: 20 Figs. 2,8), thereby forming a single semiconductor package assembly (Glenn: Figs. 1,7).
Claim(s) 6 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Glenn in view of Kitnarong in view of Wang and further in view of Pielmeier et al. (US 20200291538 A1, hereinafter Pielmeier, of the record).
Re: Claim 6, Glenn modified by Kitnarong and Wang discloses the method for manufacturing a semiconductor package assembly according to claim 2,
further comprising the step of: iv) after step ii) but before step iii), subjecting the exposed portion of the at least two terminals with to a surface roughening treatment.
Glenn modified by Kitnarong and Wang does not expressly disclose further comprising the step of: iv) after step ii) but before step iii), subjecting the exposed portion of the at least two terminals to a surface roughening treatment.
However, in the same manufacturing of semiconductor device field of endeavor, Pielmeier discloses subjecting a metal structure (a package lead with plated copper surface in [0046, 0048], Fig. 7) to a surface roughening treatment (Micro-etching process in [0048], Fig. 7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Pielmeier’s method of subjecting a metal structure to a surface roughening treatment to the combination of the Glenn, Kitnarong and Wang method to obtain further comprising the step of: iv) after step ii) but before step iii), subjecting the exposed portion of the at least two terminals to a surface roughening treatment to have an improved technique for limiting solder over spreading/overflow for flip-chip semiconductor packages ([0004], Pielmeier).
Claim(s) 3 and 8-9 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Glenn in view of Kitnarong and further in view of Pielmeier et al. (US 20200291538 A1, hereinafter Pielmeier, of the record).
Re: Claim 3, Glenn modified by Kitnarong discloses the method for manufacturing a semiconductor package assembly according to claim 1,
Glenn modified by Kitnarong does not expressly disclose further comprising the step of: iv) after step ii) but before step iii), subjecting the exposed portion of the at least two terminals to a surface roughening treatment.
However, in the same manufacturing of semiconductor device field of endeavor, Pielmeier discloses subjecting a metal structure (a package lead with plated copper surface in [0046, 0048], Fig. 7) to a surface roughening treatment (Micro-etching process in [0048], Fig. 7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Pielmeier’s method of subjecting a metal structure to a surface roughening treatment to the combination of the Glenn and Kitnarong method to obtain further comprising the step of: iv) after step ii) but before step iii), subjecting the exposed portion of the at least two terminals to a surface roughening treatment to have an improved technique for limiting solder over spreading/overflow for flip-chip semiconductor packages ([0004], Pielmeier).
Re: Claim 8, Glenn modified by Kitnarong and Pielmeier discloses the method for manufacturing a semiconductor package assembly according to claim 3, further comprising the step of: vi) after step v), singulating (Glenn: cuts the encapsulated portions of the leadframe with a saw in [0012], Figs. 1-2,7) the encapsulated semiconductor package from the lead frame (Glenn: 20 Figs. 2,8), thereby forming a single semiconductor package assembly (Glenn: Figs. 1,7).
Re: Claim 9, Glenn modified by Kitnarong and Pielmeier discloses a semiconductor package assembly (Glenn’s package Fig. 8 modified by Kitnarong and Pielmeier, see claims 1 and 3 rejections) composed of a silicon die structure electrically and mechanically attached to at least two terminals of the plurality of terminals and encapsulated by a molding resin so that a portion of the at least two terminals are exposed, and wherein the exposed portions of the at least two terminals are plated with a metal plating material according to the method steps of claim 3 (Glenn’s package Fig. 8 modified by Kitnarong and Pielmeier, see claims 1 and 3 rejections).
Second rejection of claim 1
Claim(s) 1,5 and 12 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kitnarong in view of Glenn.
Re: Independent Claim 1, Kitnarong discloses a method for manufacturing a semiconductor package assembly, the method comprising the steps of:
i) forming at least one semiconductor package (500 package in [0017], Figs. 5,7) by the following sub-steps:
i1) providing a lead frame (504 leadframe including leads 512 and die pad 510 in [0017], Figs. 5,7) made from a metal material (504 made of copper in [0017], Figs. 5,7) having a first frame side (upper surface of 504 Figs. 5,7) and a second frame side (lower surface of 504 Figs. 5,7) opposite to the first frame side (upper surface of 504 Figs. 5,7) and having a plurality of terminals (leads 512 in [0017], Figs. 5,7);
i2) providing at least one silicon die structure (502 die in [0017], Figs. 5,7) having a first die side (upper surface of 502 Figs. 5,7) and a second die side (lower surface of 502 Figs. 5,7) opposite to the first side (upper surface of 502 Figs. 5,7) with the second die side (lower surface of 502 Figs. 5,7) on (502 on 510 Figs. 5,7) the first frame side (upper surface of 504 Figs. 5,7) of the lead frame (504 in Figs. 5,7);
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i3) electrically and mechanically connecting (electrically and mechanically the die 502 and leads 512 through wire bond 514 in [0017], Figs. 5,7) the at least one silicon die structure (502 die, Figs. 5,7) to the plurality of terminals (leads 512, Figs. 5,7) of the lead frame (504 in Figs. 5,7); and
Kitnarong’s Figure 7-Annotated.
ii) encapsulating (IC structure is encapsulated by a mold compound in [0023], Figs. 5,7) the at least one silicon die structure (502 die, Figs. 5,7) and the plurality of terminals (leads 512, Figs. 5,7) with a molding resin (mold compound in [0023], Figs. 5,7) leaving at least a portion of at least two terminals (leads 512, Figs. 5,7) exposed (Fig. 7), thereby forming at least one encapsulated semiconductor package assembly (mold-encapsulated IC structures, Figs. 5,7); wherein the method further comprises the step of:
plating the exposed plated portion (tin plating 520 in [0024], Fig. 7) of the at least two terminals (leads 512, Figs. 5,7) with a metal plating material (in [0024], Fig. 7).
Kitnarong does not expressly disclose the step iii) plating the exposed portion of the at least two terminals with a metal plating material, with the metal plating material being the same as the metal material of the lead frame, and v) plating the exposed plated portion of the at least two terminals with a further metal plating material different from the metal plating material used in the plating step iii).
However, in the same manufacturing of the semiconductor device field of endeavor, Glenn discloses iii) plating (plates the exposed surfaces of the leadframe, including the exposed second surfaces of the tabs with a metal, such as copper in [0011], Figs. 1,8) the exposed portion of the at least two terminals (Glenn: 30 Figs.2, 8) with a metal plating material (Glenn: copper in [0011]), with the metal plating material being the same as the metal material of the lead frame (Glenn: 20 made of copper in [0030], Figs. 2,8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Glenn’s method of plating the exposed portion of the at least two terminals with a metal plating material, with the metal plating material being the same as the metal material of the lead frame to Kitnarong’s method to have iii) plating the exposed portion of the at least two terminals with a metal plating material, with the metal plating material being the same as the metal material of the lead frame, and v) plating the exposed plated portion of the at least two terminals with a further metal plating material different from the metal plating material used in the plating step iii) for facilitated by the electrical interconnection of the components of leadframe ([0057], Glenn).
Re: Claim 5, Kitnarong modified by Glenn discloses a semiconductor package assembly (Kitnarong’s package Fig. 5 modified by Glenn, see claim 1- second rejection) composed of a silicon die structure electrically and mechanically attached to at least two terminals of the plurality of terminals and encapsulated by a molding resin so that a portion of the at least two terminals are exposed, and wherein the exposed portions of the at least two terminals are plated with a metal plating material according to the method steps of claim 1 (Kitnarong’s package Fig. 5 modified by Glenn, see claim 1- second rejection).
Re: Claim 12, Glenn modified by Kitnarong discloses the semiconductor package assembly according to claim 5, wherein the semiconductor package assembly (Kitnarong’s package Fig. 5 modified by Glenn, see claim 1- second rejection) is a leaded semiconductor package assembly (Kitnarong’s package Fig. 5 modified by Glenn, is a lead package, see claim 1- second rejection).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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