DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 9 – 14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 22 December 2025.
Applicant’s election without traverse of Species I, as represented in at least Fig. 3a, in the reply filed on 22 December 2025 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Regarding Claim 5,
This claim recites the limitation “a separating layer”; however, no such layer is found in at least Fig. 3a of the elected Species I.
Regarding Claim 7,
This claim recites the limitation “a third section having a third height”; however, no such section is found in at least Fig. 3a of the elected Species I.
Regarding Claim 15,
This claim recites the limitation “an undoped GaN layer”; however, no such layer is found in at least Fig. 3a of the elected Species I.
Therefore, the above limitations must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: HYBRID P-GAN GATE GAN HEMT
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4 – 7, & 17 – 18 are rejected under 35 U.S.C. 102 as being anticipated by OH (US 20210336045 A1).
Regarding Claim 1,
OH discloses:
A field effect transistor (FET) device (Fig. 22: 600), comprising:
a substrate (Fig. 23: 110);
a gallium nitride (GaN) structure (Fig. 25: 120/130/640s; Par. 130) covering a portion of the substrate;
a gate metal layer (Fig. 25: 650/660; Par. 131 & Fig. 2: 150/160; Par. 84 – 88, where 650/660 & 150/160 comprise the same materials, respectively; Par. 107 & 111) on top of the GaN structure;
wherein the GaN structure comprises:
at least one first section (Fig. 25: 640 under horizontal 640/650 interface) having a first height, and
a second section (Fig. 25: 640 under horizontal 640/660 interface) having a second height that is smaller than the first height;
wherein a first interface (Fig. 25: 640/650 interface) between the at least one first section of the GaN structure and the gate metal layer has ohmic contact properties (Par. 131); and
wherein a second interface (Fig. 25: 640/660 interface) between the second section of the GaN structure and the gate metal layer has non-ohmic contact properties (Par. 132).
Regarding Claim 2,
OH discloses:
The FET device of claim1,
wherein the first interface forms an ohmic contact (Par. 131), and/or
wherein the second interface forms a Schottky junction (Par. 132) or a p-n junction.
The Examiner requests, in response to this Office Action, Applicant cancel the limitation “or a p-n junction” from Lin. 3 of Claim 2, as this limitation is not drawn to elected Species I but is, instead, drawn to non-elected Species II – V.
Regarding Claim 4,
OH discloses:
The FET device of claim 1,
wherein the GaN structure comprises a plurality of first sections that are separated from each other (As seen in Fig. 25).
Regarding Claim 5,
OH discloses:
The FET device of claim 1,
wherein a separating layer (Fig. 25: 660) is arranged around the first interface on the GaN structure to physically separate the first interface from the second interface (As seen in Fig. 22, 23, & 25).
Regarding Claim 6,
OH discloses:
The FET device of claim 1,
wherein the GaN structure comprises a sloped transition region from the first section to the second section.
(Fig. 25: the GaN structure comprises a vertically sloped and instantaneous transition region from the first section to the second section.)
Regarding Claim 7,
OH discloses:
The FET device of claim 1,
wherein the GaN structure further comprises a third section (Fig. 25: 130) having a third height that is different from the first and the second height (As seen in Fig. 25).
Regarding Claim 17,
OH discloses:
The FET device of claim 1,
wherein the FET device is a GaN-gate high electron mobility transistor (HEMT) device (Par. 71).
Regarding Claim 18,
OH discloses:
Method of fabricating a field effect transistor (FET) device (Fig. 5 – 8), comprising the steps of:
providing a substrate (Fig. 5: 110);
forming a gallium nitride (GaN) structure (Fig. 5 – 6: 140; Par. 82) on top of the substrate,
wherein the GaN structure comprises at least one first section (Fig. 7: section of 140 under 150) having a first height, and a second section (Fig. 7: section of 140 not under 150) having a second height that is smaller than the first height;
forming a gate metal layer (Fig. 7 – 8: 150/160; Par. 84 – 88) on top of the GaN structure;
wherein a first interface (Fig. 8: 140/150 interface) between the at least one first section of the GaN structure and the gate metal layer has ohmic contact properties (Par. 85), and
wherein a second interface (Fig. 8: 140/160 interface) between the second section of the GaN structure and the gate metal layer has non-ohmic contact properties (Par. 87).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over OH.
Regarding Claim 3,
OH does not disclose:
The FET device of claim 1,
wherein the first interface makes up less than 10% of a total interface area between the GaN structure and the gate metal layer, the total interface area comprising the first interface and the second interface.
However, OH does disclose simulated data (Fig. 4; Par. 94) providing the relationship between gate leakage current and the percentage the second interface—and, thus, the first interface—makes up of the total interface area between the GaN structure and the gate metal layer, the total interface area comprising the first interface and the second interface.
Further, this data is provided for the scenario where the first interface makes up 7% (Fig. 4: 93% trendline) of the total interface area between the GaN structure and the gate metal layer, the total interface area comprising the first interface and the second interface.
As such, OH recognizes the percentage the first interface makes up of the total interface area between the GaN structure and the gate metal layer, the total interface area comprising the first interface and the second interface, is a result effective variable, as said percentage provides a means to balance the amount of gate leakage current and turn-on resistance reduction (OH Par. 97). Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to select a value of said percentage in OH to fall within the claimed range as a means to strike a desired balance between gate current leakage and turn-on resistance reduction.
Claims 8, 15, 16, & 19 are rejected under 35 U.S.C. 103 as being unpatentable over OH in view of OKAWA (US 20160380091 A1).
Regarding Claim 8,
OH discloses:
The FET device of claim 1,
wherein the GaN structure comprises a p-doped GaN, pGaN, layer (Fig 25: 640; Par. 130)
OH does not disclose:
wherein a concentration of p-dopants in the pGaN layer is higher in a region below the first interface than in a region below the second interface.
OKAWA discloses:
wherein a concentration of p-dopants (As seen in Fig. 9) in the pGaN layer (Fig. 9: 34; Par. 33 & 51) is higher in a region (Fig. 9: 34a) below the first interface (Fig. 9: 38a) than in a region (Fig. 9: 34b) below the second interface (Fig. 9: 37a).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of OH with those of OKAWA to enable a concentration of p-dopants in the pGaN layer to be higher in a region below the first interface than in a region below the second interface in OH according to the teachings of OKAWA for the further advantage of suppressing undesirable gate-leakage current (OKAWA Par. 51). Further still, a higher concentration of p-dopants in the pGaN layer below the first interface is known in the art to improve the ohmic characteristics of said first interface.
Regarding Claim 15,
OH discloses:
The FET device of claim 8,
wherein the GaN structure further comprises an undoped GaN layer (Fig. 25: 120; Par. 75).
Regarding Claim 16,
OH discloses:
The FET device of claim 1,
wherein the gate metal layer is formed by a metal stack (As seen in Fig. 25),
OH does not disclose:
wherein the metal stack comprises any one of the following material combinations: Ni/Au, Ni/Ag, Pd/Au, Cr/Au, Pt/Au, Ti/Pt/Au, Ni/Si, W/Si, Ti/Al, Ti/Al/Ti, or TiN/AI/TiN.
OKAWA discloses:
wherein the metal stack (Fig. 9: 37/38) comprises any one of the following material combinations: Ni/Au, Ni/Ag, Pd/Au, Cr/Au, Pt/Au, Ti/Pt/Au, Ni/Si, W/Si, Ti/Al, Ti/Al/Ti, or TiN/AI/TiN (Par. 35: 38 may comprise Pt, Pb, or an alloy thereof & Par. 36: 37 may comprise Ni, W, Ti, Al, or an alloy thereof).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of OH with those of OKAWA to enable the metal stack to comprise Ti/Al or Ti/Al/Ti in OH according to the teachings of OKAWA, as one of ordinary skill in the art would have recognized the finite number of predictable material combinations for the metal stack. As such, absent unexpected results, it would have been obvious to one of ordinary skill in the art to try said material combinations in order to determine which yields the best device functionality.
Regarding Claim 19,
OH discloses:
The method of claim 18,
wherein the GaN structure comprises a p-doped GaN, pGaN, layer (Fig 2: 140; Par. 82);
OH does not disclose:
wherein a concentration of p-dopants in the pGaN layer is higher in a region below the first interface than in a region below the second interface.
OKAWA discloses:
wherein a concentration of p-dopants (As seen in Fig. 9) in the pGaN layer (Fig. 9: 34; Par. 33 & 51) is higher in a region (Fig. 9: 34a) below the first interface (Fig. 9: 38a) than in a region (Fig. 9: 34b) below the second interface (Fig. 9: 37a).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of OH with those of OKAWA to enable a concentration of p-dopants in the pGaN layer to be higher in a region below the first interface than in a region below the second interface in OH according to the teachings of OKAWA for the further advantage of suppressing undesirable gate-leakage current (OKAWA Par. 51). Further still, a higher concentration of p-dopants in the pGaN layer below the first interface is known in the art to improve the ohmic characteristics of said first interface.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.S.S./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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