DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 203, 204, (N), and (N-1). Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11-15, 17, and 18 are rejected under 35 U.S.C. 102(a)(1) as being previously disclosed by Jiangfeng et al. (CN 103035706 A).
Regarding claim 11, Jiangfeng et al. teaches a semiconductor component [¶ 0001], comprising:
two electrodes configured vertically one above the other [Fig. 3, source electrode 301 and drain electrode 307];
a substrate made of gallium nitride (GaN) [Fig. 3, substrate 306];
a shielding layer (308, blocking layer, equivalent to applicant’s shielding layer) for forming a space charge zone for shielding of an electric field when the semiconductor component is connected in a blocking operation (off state) or a reverse direction [¶¶ 0003-0004], wherein the shielding (blocking) layer has gallium and/or nitrogen in addition to aluminum or indium [Fig. 3, blocking layer 308 and ¶ 0007], and is constructed or doped such that at least one region effectively acting as a p-doped semiconductor is formed in a vicinity of a region effectively acting as an n-doped semiconductor [Fig. 3, blocking layer 308 and buffer layer 305 and ¶ 0007].
Regarding claim 12, Jiangfeng et al. teaches the component of claim 11, wherein the semiconductor component is a diode or transistor [¶ 0001].
Regarding claim 13, Jiangfeng et al. teaches the component of claim 11, wherein the shielding layer (blocking layer) has or is formed of homogeneous p-doped aluminum nitride (AIN), or aluminum gallium nitride (AlGaN), or indium nitride (InN), or indium gallium nitride (InGaN) [Fig. 3, blocking layer 308 and ¶ 0007].
Regarding claim 14, Jiangfeng et al. teaches the component of claim 11, wherein the region effectively acting as a p-doped semiconductor is formed without an addition of foreign ions, using only: (i) gallium (Ga) and/or nitrogen (N), and (ii) aluminum (Al) or indium (In) [Fig. 3, blocking layer 308 and ¶ 0007].
Regarding claim 15, Jiangfeng et al. teaches the component of claim 14, wherein the shielding layer (blocking layer) has at least a gradual change in aluminum content or indium content in a direction of a layer thickness [¶ 0009, aluminum content increases from 0 to A from top to bottom].
Regarding claim 17, Jiangfeng et al. teaches the component of claim 15, wherein an extension of the shielding (blocking) layer in a vertical direction is formed adjacent to the gallium nitride substrate [Fig. 3, adjacent taken to mean nearby and blocking layer 308 is seen to be vertically adjacent to the gallium nitride substrate 306].
Regarding claim 18, Jiangfeng et al. teaches the component of claim 15, wherein the shielding (blocking) layer forms a drift (buffer) layer of a transistor situated on the gallium nitride substrate [Fig. 3, blocking layer 308 and buffer layer 305 and ¶ 0007, the way buffer layer is used in this application is the same as what a drift layer is seen to do].
Claim(s) 19-22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takatani et al. (US PGPub 2021/0226019).
Regarding claim 19, Takatani et al. teaches a method for producing a semiconductor component having two electrodes configured vertically one above the other [¶¶ 0003 and 0066], the method comprising:
depositing a layer sequence on a gallium nitride substrate [¶ 0003, epitaxial growth of drift layer on a gallium nitride substrate], including:
in a region that is situated indirectly between two electrodes configured vertically one above the other [Fig. 17(a) and ¶ 0003], forming a shielding (barrier) layer in which aluminum or indium is deposited and/or doped with gallium and/or nitrogen [¶¶ 0003 and 0008] in such a way that at least one region effectively acting as a p-doped semiconductor is formed in a vicinity of a region effectively acting as an n-doped semiconductor [¶¶ 0003 and 0008].
Regarding claim 20, Takatani and Shirota teaches the method of claim 19, wherein the semiconductor is a diode or transistor [¶ 0002].
Regarding claim 21, Takatani and Shirota teaches the method of claim 19, wherein during the formation of the shielding layer, an aluminum content or an indium content is gradually varied over a layer thickness at least once between a minimum content and a maximum content and/or between a maximum content and a minimum content [¶ 0003, drift layer 1101 (seen in figure 17(a)) may adopt AlGaN with a composition gradient].
Regarding claim 22, Takatani and Shirota teaches the method of claim 19, wherein with the shielding (barrier) layer, an entire drift layer of a transistor is formed [¶ 0003].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jiangfeng et al. as applied to claim 15 above, and further in view of Xing et al. (US 9362389 B2).
Regarding claim 16, Jiangfeng et al. teaches the aforementioned information that teaches the semiconductor component of claim 15.
Jiangfeng et al. does not teach a double gradual change in aluminum content or indium content.
Xing et al. teaches a gradual (graded) increase in aluminum content in the n-type polarized layer leading toward the p-type polarized layer and where the two layers meet, the aluminum content is at a maximum, which gradually decreases further along the thickness of the layer to a minimum of aluminum [Fig. 15A].
It would have been obvious to a person of ordinary skill in the art before the effective filing date
of the claimed invention to implement the gradual change in aluminum content as required by the claims, because the double gradual change is seen to present a higher breakdown voltage and prevents vertical breakdown on the drain side of the p-n junction [¶¶ 0065-0067 in Xing et al.]. Also, the gradual/graded change eliminates the abrupt bandgap that is seen in a conventional heterojunction gap.
Related Art
Reference Wang and Lue (US 7642585 B2) was also in consideration for claim 16. Wang and Lue discuss further in depth a double gradual change in content. The discussion was more generalized and in-depth, focusing on tunnel dielectric structures. This could still be utilized as a person with ordinary skill in the art would be able to recognize the same reasoning a double gradual change in composition would be used in a tunnel dielectric structure, to ensure minimal charge loss and voltage breakdown, would still be applicable to a shielding layer for the same reasoning.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NOOR MOHAMMAD ISMAIL TAHIR whose telephone number is (571)272-6166. The examiner can normally be reached Monday Friday, 8 a.m. 5 p.m. ET..
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/NOOR MOHAMMAD ISMAIL TAHIR/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893