DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 07/20/2026 has been entered. Claims 1-14 and 21-26 are pending.
Claims 15-20 are canceled.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Non-Final Reject" filed on 07/20/2026, have been fully considered.
The applicant’s amendments/arguments of claim 1 are not persuasive and some of them are moot because do not apply to new ground of rejections with a new reference, US 20230048500 A1 to Malouin, being used in the current rejection, see detail below.
The applicant’s amendment/arguments of claim 10 related to “the proposed combination of Matsushiba and Gupta is improper because it would render Matsushiba inoperable for its intended purpose” are not persuasive because Matsushiba (US 20090116194 A1) describes an opening 44 to allow the heat transfer from the bottom side of the device, wherein the bottom thermally conductive member 30,42,40 is in contact with the substrate 34, Matsushiba does not disclose details of elements included in the substrate 34, such as a voltage regulator. However, Gupta (US 20080155990 A1) discloses a similar device including voltage regulator 112 in a back side of the substrate 110 and having a heat spreader 106 in a path of the heat dissipation, this indicates a back-side cooling. Then, the combination of Matsushiba and Gupta does not result in the inoperability of Matsushiba’s device because Gupta’s voltage regulator included in the semiconductor substrate are both cooler front the back side of the device.
The applicant’s amendments/arguments of claim 21 are not persuasive and some of them are moot because do not apply to new ground of rejections with a new reference, US 20150252217 A1 to Czubarow, being used in the current rejection, see detail below.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5 and 6 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ma et al.
(US 6219243 B1, hereinafter Ma, of the record) in view of Malouin et al. (US 20230048500 A1, hereinafter Malouin).
Re: Independent Claim 1, Ma teaches an integrated circuit system (Fig. 1) comprising:
PNG
media_image1.png
458
978
media_image1.png
Greyscale
Ma’s Figure 1-Annotated.
a circuit board (130 circuit board in Col. 4, line 14, Fig.1) having a top side (top130 Fig.1-Annotated) and a bottom side (bottom130 Fig.1-Annotated) and defining an opening (135 in Col. 4, line 14, Fig.1) from the top side to the bottom side;
a bottom boiling plate (140 heat spreader, a metal as a boiling material in Col. 4, line 12, Fig.1) having a recessed portion (R140 Fig.1-Annotated) and having a projection (P140 Fig.1-Annotated) with a terminal surface (165 in Col. 4, line 13, Fig.1), wherein the recessed portion (R140 Fig.1-Annotated) is located below the bottom side (bottom130 Fig.1-Annotated) of the circuit board (130), wherein the projection (P140 Fig.1-Annotated) extends through the opening (135), and wherein the terminal surface (165 Fig.1) is located above the top side (top130 Fig.1-Annotated) of the circuit board (130);
a semiconductor substrate (110 an integrated circuit die as a semiconductor die in Col. 3, line 44-45, Fig.1) located over the top side of the circuit board (130) and including semiconductor devices (including integrated circuits in Col. 3, lines 18-20, 44-45, Fig.1); and
a top boiling plate (150 heat spreader a metal as a boiling material in Col. 4, lines 35-36, Fig.1) located over the semiconductor substrate (110), wherein the bottom boiling plate (140) and the top boiling plate (150) are configured to dissipate heat away from the integrated circuit system (in Col. 4, lines 41-46, Fig.1).
Ma does not expressly disclose a dielectric cooling liquid in contact with an outer surface of the top boiling plate and an outer surface of the bottom boiling plate, wherein the bottom boiling plate and the top boiling plate are configured to dissipate the heat by boiling of the dielectric cooling liquid at the outer surfaces.
However, in the same semiconductor device field of endeavor, Malouin discloses a dielectric cooling liquid (210 dielectric fluid in [0037], Fig. 2) in contact with an outer surface of the top boiling plate (204-207-top, a top region of electronic components 204-207 in [0034], Fig. 2) and an outer surface of the bottom boiling plate (204-207-bottom, a bottom region of electronic components 204-207 in [0034], Fig. 2), wherein the bottom boiling plate (204-207-top) and the top boiling plate (204-207-bottom) are configured to dissipate the heat by boiling of the dielectric cooling liquid (210) at the outer surfaces ([0034]).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Malouin’s feature of a dielectric cooling liquid in contact with an outer surface of the top boiling plate and an outer surface of the bottom boiling plate, wherein the bottom boiling plate and the top boiling plate are configured to dissipate the heat by boiling of the dielectric cooling liquid at the outer surfaces to Ma’s device in order to have the predictable result of accelerating and directing the flow of coolant fluid toward the high-heat-generating electronic component (abstract, Malouin) resulting in improved heat management performance over air cooling (see paragraph 5 of Malouin).
Re: Claim 2, Ma modified by Malouin discloses the integrated circuit system of claim 1, wherein the semiconductor substrate (110, Ma) has a back side facing the terminal surface (165 Fig.1, Ma) of the bottom boiling plate (140 heat spreader in Col. 4, line 12, Fig.1, Ma) and a front side, wherein the semiconductor devices (including integrated circuits in Col. 3, lines 18-20, 44-45, Fig.1, Ma) are formed on the front side.
Re: Claim 5, Ma modified by Malouin discloses the integrated circuit system of claim 2, further comprising a connector (136 conductive material in Col. 3, lines 51-52, Fig.1, Ma) electrically connecting the semiconductor devices (including integrated circuits in Col. 3, lines 18-20, 44-45, Fig.1, Ma) to the circuit board (130, Ma), wherein the connector (136, Ma) is located between the top side of the circuit board (130, Ma) and the back side of the semiconductor substrate (110, Ma).
Re: Claim 6, Ma modified by Malouin discloses the integrated circuit system of claim 1, wherein the semiconductor substrate (110, Ma) has a back side facing the terminal surface (165 Fig.1, Ma) of the bottom boiling plate (140 heat spreader in Col. 4, line 12, Fig.1, Ma) and a front side, wherein the semiconductor devices (including integrated circuits in Col. 3, lines 18-20, 44-45, Fig.1, Ma) are formed on dies (as a semiconductor die in Col. 3, lines 18-20, 44-45, Ma), and wherein the dies (110 including dies, Ma) are located on the front side of the semiconductor substrate (110, Ma).
Claim(s) 3-4 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ma in view of Malouin and further in view of Gupta et al. (US 20080155990 A1, hereinafter Gupta, of the record).
Re: Claim 3, Ma modified by Malouin discloses the integrated circuit system of claim 2,
Ma modified by Malouin does not disclose further comprising a voltage regulator module (VRM) on the back side of the semiconductor substrate and electrically connected to at least one of the semiconductor devices.
However, in the same semiconductor device field of endeavor, Gupta discloses a voltage regulator module (VRM) (112 voltage regulator in [0009], Fig. 2) on the back side of the semiconductor substrate (110 substrate in [0009], Fig. 2) and electrically connected to at least one of the semiconductor devices (108 die in [0009], Fig. 2).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Gupta’s feature of a voltage regulator module (VRM) on the back side of the semiconductor substrate and electrically connected to at least one of the semiconductor devices to the combination of Ma and Malouin in order to have the predictable result of removing a system board parasitic influences and improving a voltage droop ([0002], Gupta).
Re: Claim 4, Ma modified by Malouin and Gupta discloses the integrated circuit system of claim 3, further comprising a thermal interface material (TIM) (160 thermal grease in Col. 4, lines 31-34, Fig.1, Ma) contacting the terminal surface (165, Fig.1, Ma) of the bottom boiling plate (140, Fig.1, Ma) and the VRM (112 from Gupta applied to Ma).
Claim(s) 7 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ma in view of Malouin and further in view of Vandentop et al. (US 6580611 B1, hereinafter Vandentop, of the record).
Re: Claim 7, Ma modified by Malouin discloses the integrated circuit system of claim 6,
Ma modified by Malouin does not expressly disclose further comprising a thermal interface material (TIM) contacting the dies and the top boiling plate.
However, in the same semiconductor device field of endeavor, Vandentop discloses a thermal interface material (TIM) (TIM in Col. 3, lines 31-36, Fig.3) contacting the dies (4 in Col. 3, lines 31-36, Fig.3) and the top boiling plate (12 in Col. 3, lines 31-36, Fig.3).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Vandentop’s feature of a thermal interface material (TIM) contacting the dies and the top boiling plate to the combination of Ma and Malouin in order to have the predictable result of providing cooling on both sides of the device while eliminating the large thermal barrier of the substrate (Col. 1, lines 39-41, Vandentop).
Claim(s) 8-9 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ma in view of Malouin and further in view of Liang et al. (US 20220375821 A1, hereinafter Liang, of the record).
Re: Claim 8, Ma modified by Malouin discloses the integrated circuit system of claim 1,
Ma modified by Malouin does not disclose further comprising: a top bolt coupling the top boiling plate to the circuit board; and a bottom bolt coupling the bottom boiling plate to the circuit board.
However, in the same semiconductor device field of endeavor, Liang discloses a top bolt (52 first fastener in [0093], Fig. 2) coupling the top boiling plate (4,41 heat sink 4 including a heat dissipation substrate 41 in [0083], Figs. 1,2) to the circuit board (11 PCB in [0091], Fig. 2); and a bottom bolt (51 second fastener in [0093], Fig. 2) coupling the bottom boiling plate (12 protection plate in [0091], Fig. 2) to the circuit board (11).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to modify the Ma’s top boiling plate according to the Liang’s feature having a top bolt coupling the top boiling plate to the circuit board; and a bottom bolt coupling the bottom boiling plate to the circuit board in order to have the predictable result of increasing rigidity of the PCB assembly at the corresponding bare die and to mitigate deformation of the PCB assembly at the bare die, and improve reliability of a connection between the bare die and the PCB assembly ([0062], Liang).
Re: Claim 9, Ma modified by Malouin discloses the integrated circuit system of claim 1,
Ma modified by Malouin does not disclose further comprising a ring enclosing an outer periphery of the semiconductor substrate, wherein: the top boiling plate has base portion and a sag portion; the ring terminates at an uppermost surface located below the base portion of the top boiling plate; and the sag portion of the top boiling plate is surrounded by the ring.
PNG
media_image2.png
394
769
media_image2.png
Greyscale
Liang’s Figure 2-Annotated.
However, in the same semiconductor device field of endeavor, Liang discloses a ring (3 reinforcing frame surrounding the die 2 in [0083], Fig. 2) enclosing an outer periphery ([0083]) of the semiconductor substrate (2 bare die in [0083], Fig. 2), wherein: the top boiling plate (4,41 heat sink 4 including a heat dissipation substrate 41 in [0083], Figs. 1,2) has base portion (base-4,41 Fig. 2-Annotated) and a sag portion (sag-4,41 Fig. 2-Annotated); the ring (3) terminates at an uppermost surface located below the base portion (base-4,41 Fig. 2-Annotated) of the top boiling plate (4,41); and the sag portion (sag-4,41 Fig. 2-Annotated) of the top boiling plate (4,41) is surrounded by the ring (3).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to modify the Ma’s top boiling plate according to the Liang’s feature of a ring enclosing an outer periphery of the semiconductor substrate, wherein: the top boiling plate has base portion and a sag portion; the ring terminates at an uppermost surface located below the base portion of the top boiling plate; and the sag portion of the top boiling plate is surrounded by the ring in order to have the predictable result of increasing rigidity of the PCB assembly at the corresponding bare die, and to mitigate deformation of the PCB assembly at the bare die, and improve reliability of a connection between the bare die and the PCB assembly ([0062], Liang).
Claim(s) 10-14 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Matsushiba et al. (US 20090116194 A1) in view of Gupta et al. (US 20080155990 A1, hereinafter Gupta, of the record).
Re: Independent Claim 10, Matsushiba discloses an integrated circuit system (Fig. 2) comprising:
PNG
media_image3.png
383
549
media_image3.png
Greyscale
Matsushiba’s Figure 2-Annotated.
a circuit board (32 circuit board in [0013], Fig.2) having a top side (top32 Fig.2-Annotated) and a bottom side (bottom32 Fig.2-Annotated) and defining an opening (44 opening in [0014], Fig.2) from the top side to the bottom side;
a semiconductor substrate (34 semiconductor chip, a semiconductor substrate including a CPU or an ASIC in [0013], Fig.2) having a front side (front34 Fig.2-Annotated) and a back side (back34 Fig.2-Annotated), located over the top side (top32 Fig.2-Annotated) of the circuit board (32), and including semiconductor devices ([0013]) on the front side (front34 Fig.2-Annotated);
a bottom thermally conductive member (30,42,40 bottom plate 30, thermally conductive member 42, thermally conductive elastic member 40, in [0015], Fig.2) extending through the opening (44) in the circuit board (32).
Matsushiba does not expressly disclose a voltage regulator module (VRM) on the back side of the semiconductor substrate and electrically connected to at least one of the semiconductor devices; a bottom thermally conductive member in thermal communication with the VRM to dissipate heat away from the back side of the semiconductor substrate, wherein the voltage regulator module is interposed between the back side of the semiconductor substrate and the bottom thermally conductive member, such that the bottom thermally conductive member is spaced from the back side of the semiconductor substrate by at least a thickness of the voltage regulator module.
However, in the same semiconductor device field of endeavor, Gupta discloses a voltage regulator module (VRM) (112 voltage regulator in [0009], Fig. 2) on the back side of the semiconductor substrate (110 substrate in [0009], Fig. 2) and electrically connected to at least one of the semiconductor devices (108 die in [0009], Fig. 2).
Therefore, Matsushiba in view of Gupta teaches a bottom thermally conductive member (30,42,40 in [0015], Fig.2, Matsushiba) in thermal communication with the VRM (112 in [0009], Fig. 2, Gupta) to dissipate heat away from the back side of the semiconductor substrate (34 in [0013], Fig.2, Matsushiba), wherein the voltage regulator module (112 in [0009], Fig. 2, Gupta) is interposed between the back side of the semiconductor substrate (34 in [0013], Fig.2, Matsushiba) and the bottom thermally conductive member (30,42,40, Matsushiba), such that the bottom thermally conductive member (30,42,40, Matsushiba) is spaced from the back side of the semiconductor substrate (34 in [0013], Fig.2, Matsushiba) by at least a thickness of the voltage regulator module (112 in [0009], Fig. 2, Gupta).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Gupta’s feature of a voltage regulator module (VRM) on the back side of the semiconductor substrate and electrically connected to at least one of the semiconductor devices to Matsushiba’s device in order to have the predictable result of removing a system board parasitic influences and improving a voltage droop ([0002], Gupta).
Re: Claim 11, Matsushiba modified by Gupta discloses the integrated circuit system of claim 10, wherein: the bottom thermally conductive member (30,42,40, Fig.2, Matsushiba) includes a base portion (base region of P30,42,40, Fig.2-Annotated, Matsushiba) located below the bottom side of the circuit board (32, Fig.2, Matsushiba) and a projection (P30,42,40, Fig.2-Annotated, Matsushiba) extending upward from the base portion (base region of P30,42,40, Fig.2-Annotated, Matsushiba) through the opening (44 opening in [0014], Fig.2) to a terminal surface (54, Fig.2, Matsushiba) in thermal communication (112 from Gupta allows heat transfer from Matsushiba’s substrate 34 because the Matsushiba’s 44 is the heat path, Fig. 2) with the voltage regulator module (112 from Gupta applied to Matsushiba); and the opening (44 opening in [0014], Fig.2) has a first width (a width of the opening in Fig.2), the projection (P30,42,40, Fig.2-Annotated, Matsushiba) has a second width (a width of the projection P30,42,40 in Fig.2) less than the first width, and the base portion (base region of P30,42,40, Fig.2-Annotated, Matsushiba) has a third width (a width of base region of P30,42,40 in Fig.2) greater than the second width (Fig.2-Annotated, Matsushiba).
Claim(s) 12 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Matsushiba in view of Gupta and further in view of Colgan et al. (US 20240203822 A1, hereinafter Colgan).
Re: Claim 12, Matsushiba modified by Gupta discloses the integrated circuit system of claim 10,
Matsushiba modified by Gupta does not disclose the semiconductor substrate comprises a through-silicon via interposer-based structure; and the semiconductor devices are formed in a plurality of dies disposed on the front side of the semiconductor substrate.
However, in the same semiconductor device field of endeavor, Colgan discloses the semiconductor substrate (114 interposer in [0030], Fig. 1) comprises a through-silicon via interposer-based structure (114 interposer with through-silicon vias 124 connecting the RDLs in [0030], Fig. 1); and the semiconductor devices (semiconductor devices such as processors or computational units are formed in a plurality of dies 102 and 112 in [0030], Fig. 1) are formed in a plurality of dies (102 and 112 chips in [0038], Fig. 1) disposed on the front side of the semiconductor substrate (114, Fig. 1).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Colgan’s feature of the semiconductor substrate comprises a through-silicon via interposer-based structure; and the semiconductor devices are formed in a plurality of dies disposed on the front side of the semiconductor substrate to the combination of Matsushiba, Gupta in order to have the predictable result of including more electrical connections in the device ([0030], Colgan).
Claim(s) 13 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Matsushiba in view of Gupta and further in view of Malouin.
Re: Claim 13, Matsushiba modified by Gupta discloses the integrated circuit system of claim 10,
Matsushiba modified by Gupta does not disclose further comprising: further comprising: a tank containing a cooling liquid, wherein the circuit board, the semiconductor substrate, the voltage regulator module, and the bottom thermally conductive member are located within the cooling liquid.
However, in the same semiconductor device field of endeavor, Malouin discloses a tank containing a cooling liquid (210 dielectric fluid in [0037], Fig. 2).
Therefore, Matsushiba in view of Gupta and Malouin teaches wherein the circuit board (32 in [0013], Fig.2, Matsushiba), the semiconductor substrate (34 in [0013], Fig.2, Matsushiba), the voltage regulator module (112 in [0009], Fig. 2, Gupta), and the bottom thermally conductive member (30,42,40, in [0015], Fig.2, Matsushiba) are located within the cooling liquid (210 dielectric fluid in [0037], Fig. 2, Malouin).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Malouin’s feature of a tank containing a cooling liquid to the combination of the Matsushiba and Gupta in order to have the predictable result of accelerating and directing the flow of coolant fluid toward the high-heat-generating electronic component (abstract, Malouin) resulting in improved heat management performance over air cooling (see paragraph 5 of Malouin).
Claim(s) 14 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Matsushiba in view of Gupta and further in view of Shao et al. (US 20210384103 A1, hereinafter Shao).
Re: Claim 14, Matsushiba modified by Gupta discloses the integrated circuit system of claim 10, further comprising a thermal interface material layer (thermally conductive material in [0016], Matsushiba) between the voltage regulator module (112 from Gupta applied to Matsushiba) and the bottom thermally conductive member (30,42,40 bottom plate 30, thermally conductive member 42, thermally conductive elastic member 40, in [0015], Fig.2, Matsushiba).
Matsushiba modified by Gupta does not disclose the thermal interface material layer comprising a metal-containing matrix material layer and polymer particles coated with a metal cover and embedded within the metal-containing matrix material layer.
However, in the same semiconductor device field of endeavor, Shao discloses the thermal interface material layer comprising a metal-containing matrix material layer (140 in [0039]) and polymer particles (132 in [0040]) coated with a metal cover (137 in [0040]) and embedded within the metal-containing matrix material layer (140 in [0039]).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Shao’s feature of thermal interface material layer comprising a metal-containing matrix material layer and polymer particles coated with a metal cover and embedded within the metal-containing matrix material layer to the combination of the Matsushiba and Gupta in order to have the predictable result of reducing the thermal resistance between the semiconductor die 100 and the heat-dissipating feature ([0040], Shao).
Claim(s) 21, 24-25 and 26 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Mallik et al. (US 20040173901 A1, hereinafter Mallik, of the record) in view of Nagesh et al. (US 5155661 A, hereinafter Nagesh, of the record) and further in view of Czubarow et al. (US 20150252217 A1, hereinafter Czubarow).
Re: Independent Claim 21, Mallik discloses an integrated circuit system (Fig. 3) comprising:
PNG
media_image4.png
420
690
media_image4.png
Greyscale
Mallik’s Figure 3-Annotated.
a semiconductor substrate (390 chip in [0033], Fig. 3) having a front side (front-390 Fig. 3-Annotated) and a back side (back-390 Fig. 3-Annotated) and a periphery (P-390 Fig. 3-Annotated);
a die (die included in 390 in [0033], Fig. 3) on the front side of the semiconductor substrate (390);
a top thermally conductive member (310-120 heat sink 310 and heat-conducting substrate 120 in [0033], Fig. 3) having a base portion (base-310-120 Fig. 3-Annotated) and a sag portion (sag-310-120 Fig. 3-Annotated) extending from the base portion (base-310-120 Fig. 3-Annotated); and
a bottom thermally conductive member (320 heat sink in [0033], Fig. 3) having a base portion (base-320 Fig. 3-Annotated) and a mesa portion (mesa-320 Fig. 3-Annotated) extending from the base portion (base-320 Fig. 3-Annotated).
Mallik does not expressly disclose a top ring located on the front side of the semiconductor substrate at the periphery, the top ring defining a top inner gap between opposite sides of the top ring; a bottom ring located on the back side of the semiconductor substrate at the periphery, the bottom ring defining a bottom inner gap between opposite sides of the bottom ring; a die located in the top inner gap, wherein the die is electrically connected to the semiconductor substrate via a plurality of die-to-substrate connectors located between the die and the front side of the semiconductor substrate;
wherein the sag portion is located in the top inner gap, wherein the mesa portion is located in the bottom inner gap.
However, in the same semiconductor device field of endeavor, Nagesh discloses a top ring (32 ring in Col. 2, line 64, Fig.2) located on the front side of the PCB (12 PCB in Col. 2, lines 55-56, Fig. 2) at the periphery (outer sides of 12, Fig. 2), the top ring (32) defining a top inner gap (Fig. 2) between opposite sides of the top ring (32); a bottom ring (34 ring in Col. 2, lines 64-65, Fig.2) located on the back side of the PCB (12 PCB in Col. 2, lines 55-56, Fig. 2) at the periphery (outer sides of 12, Fig. 2), the bottom ring (34) defining a bottom inner gap (Fig. 2) between opposite sides of the bottom ring (34).
Therefore, Mallik in view of Nagesh teaches a top ring (32 ring in Col. 2, line 64, Fig.2, Nagesh) located on the front side of the semiconductor substrate (390 chip in [0033], Fig. 3, Mallik) at the periphery, the top ring (32, Nagesh) defining a top inner gap (Fig. 2, Nagesh) between opposite sides of the top ring (32, Nagesh); a bottom ring (34 ring in Col. 2, lines 64-65, Fig.2, Nagesh) located on the back side of the semiconductor substrate (390 chip in [0033], Fig. 3, Mallik) at the periphery, the bottom ring (34, Nagesh) defining a bottom inner gap (Fig. 2, Nagesh) between opposite sides of the bottom ring (34, Nagesh); a die (die included in 390 in [0033], Fig. 3, Mallik) located in the top inner gap, wherein the sag portion (sag-310-120 Fig. 3-Annotated, Mallik) is located in the top inner gap (Nagesh applied to Mallik), wherein the mesa portion (mesa-320 Fig. 3-Annotated, Mallik) is located in the bottom inner gap (Nagesh applied to Mallik).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Nagesh’s top ring on the front side of the Mallik’s PCB and to include Nagesh’s bottom ring to the back side of the Mallik’s PCB in order to have the predictable result of more easily and reliably providing electrical connection between the substrate and the printed circuit board (Col. 2, lines 33-35, Nagesh).
Mallik modified by Nagesh does not expressly disclose wherein the die is electrically connected to the semiconductor substrate via a plurality of die-to-substrate connectors located between the die and the front side of the semiconductor substrate.
However, in the same semiconductor device field of endeavor, Czubarow discloses wherein the die (23 a die in [0086], Fig. 2) is electrically connected to the semiconductor substrate (185 a substrate in [0086], Fig. 2) via a plurality of die-to-substrate connectors (144 solder balls in [0086], Fig. 2) located between the die (23) and the front side of the semiconductor substrate (185).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Czubarow’s feature of wherein the die is electrically connected to the semiconductor substrate via a plurality of die-to-substrate connectors located between the die and the front side of the semiconductor substrate to the combination of Mallik and Nagesh in order to have the predictable result of exploiting the full area of the device for a relatively high number of electrical connections ([0086], Czubarow).
Re: Claim 24, Mallik modified by Nagesh and Czubarow discloses the integrated circuit system of claim 21, wherein the top ring (32 from Nagesh applied to Mallik) and the bottom ring (34 from Nagesh applied to Mallik) clamp the periphery of the semiconductor substrate (390, Mallik).
Re: Claim 25, Mallik modified by Nagesh and Czubarow discloses the integrated circuit system of claim 21, further comprising a circuit board (94 printed circuit board in [0031], Fig. 3) having a top side (top-94 in [0031], Fig. 3-Annotated) and a bottom side (bottom-94 in [0031], Fig. 3-Annotated) and defining an opening (O-94 in [0031], Fig. 3-Annotated) from the top side to the bottom side, wherein the mesa portion (mesa-320 Fig. 3-Annotated) of the bottom thermally conductive member (320 Fig. 3) extends through the opening (O-94 in [0031], Fig. 3-Annotated).
Re: Claim 26, Mallik modified by Nagesh and Czubarow discloses the integrated circuit system of claim 21, wherein the top ring (32 from Nagesh applied to Mallik) terminates at an uppermost surface located below the base portion (base-310-120 Fig. 3-Annotated) of the top thermally conductive member (310-120 Fig. 3-Annotated), and wherein the sag portion (sag-310-120 Fig. 3-Annotated) of the top thermally conductive member (310-120 Fig. 3) is surrounded by the top ring (32 from Nagesh applied to Mallik).
Claim(s) 22 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Mallik in view of Nagesh, in view of Czubarow and further in view of Gupta et al. (US 20080155990 A1, hereinafter Gupta, of the record).
Re: Claim 22, Mallik modified by Nagesh and Czubarow discloses the integrated circuit system of claim 21,
Mallik modified by Nagesh and Czubarow does not disclose further comprising a voltage regulator module (VRM) located in the bottom inner gap and on the back side of the semiconductor substrate.
However, in the same semiconductor device field of endeavor, Gupta discloses a voltage regulator module (VRM) (112 voltage regulator in [0009], Fig. 2) on the back side of the semiconductor substrate (110 substrate in [0009], Fig. 2).
Therefore, Mallik in view of Nagesh, Czubarow and Gupta teaches a voltage regulator module (VRM) (112 voltage regulator in [0009], Fig. 2, Gupta) located in the bottom inner gap (Fig. 2, Nagesh) and on the back side of the semiconductor substrate (390 in [0033], Fig. 3, Mallik).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Gupta’s feature of a voltage regulator module (VRM) on the back side of the semiconductor substrate to the combination of Mallik, Nagesh and Czubarow in order to have the predictable result of removing a system board parasitic influences and improving a voltage droop ([0002], Gupta).
Claim(s) 23 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Mallik in view of Nagesh, in view of Gupta and further in view of Vandentop et al. (US 6580611 B1, hereinafter Vandentop, of the record).
Re: Claim 23, Mallik modified by Nagesh, Czubarow and Gupta discloses the integrated circuit system of claim 22,
Mallik modified by Nagesh, Czubarow and Gupta does not disclose further comprising: a top thermal interface material (TIM) layer located in the top inner gap and contacting the die and the sag portion of the top thermally conductive member; and a bottom thermal interface material (TIM) layer located in the bottom inner gap and contacting the VRM and the mesa portion of the bottom thermally conductive member.
However, in the same semiconductor device field of endeavor, Vandentop discloses a thermal interface material (TIM) (TIM in Col. 3, lines 31-36, Fig.3) on the top (12 in Col. 3, lines 31-36, Fig.3) and bottom (18 in Col. 3, lines 31-36, Fig.3) heat sinks.
Therefore, Mallik in view of Nagesh, Czubarow, Gupta and Vandentop teaches a top thermal interface material (TIM) layer (TIM in Col. 3, lines 31-36, Fig.3, Vandentop) located in the top inner gap (Fig. 2, Nagesh) and contacting the die (die included in 390 in [0033], Fig. 3, Mallik) and the sag portion (sag-310-120 Fig. 3-Annotated, Mallik) of the top thermally conductive member (310-120 in [0033], Fig. 3, Mallik); and a bottom thermal interface material (TIM) layer (TIM in Col. 3, lines 31-36, Fig.3, Vandentop) located in the bottom inner gap (Fig. 2, Nagesh) and contacting the VRM (112 voltage regulator in [0009], Fig. 2, Gupta) and the mesa portion (mesa-320 Fig. 3-Annotated, Mallik) of the bottom thermally conductive member (320 heat sink in [0033], Fig. 3 Mallik).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Vandentop’s feature of a thermal interface material (TIM) on the top and bottom heat sinks to the combination of Mallik, Nagesh, Czubarow and Gupta in order to have the predictable result of improving colling by providing cooling on both sides of the device while eliminating the large thermal barrier of the substrate (Col. 1, lines 39-41, Vandentop).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
