Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Applicant’s election without traverse of Group 1, (claims 1-12) in the reply filed on 16 February, 2026 is acknowledged.
Claim rejections - 35 USA § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1,2, 4 8, and 10-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (US Pub 20110139497), hereinafter referred to as Li.
Regarding claim 1, Li teaches a through-silicon via (TSV) comprising a core (Li, 310, Fig. 3), wherein the core extends through a substrate along an axis, wherein the core comprises a conductive material (Li, para. 46); an outer layer (Li, 312, Fig. 3), wherein the outer layer is disposed about the axis and at least partially surrounding the core, wherein the outer layer comprises a superconductive material (Li, para. 46); and an insulating layer (Li, 314, Fig. 3), wherein the insulating layer electrically insulates the core and the outer layer from one another (Li, para. 46).
Regarding claim 2, Li teaches the TSV of claim 1, wherein the core comprises at least one of: Cu, Ni, Co, or Al (Li, para. 46).
Regarding claim 4, Li teaches the TSV of claim 1, wherein the outer layer comprises at least one of: NbTiN, NbN, Nb3Al, Nb, Ti, Al, Ta, or a combination of such materials (Li, para. 46)
Regarding claim 8, Li teaches the TSV of claim 1, wherein the insulating layer comprises at least one of: SiO2 or SiN (Li, para. 46).
Regarding claim 10, Li teaches the TSV of claim 1, wherein the substrate comprises an interposer (Li, 304, fig. 3), wherein the interposer comprises silicon (Li, para. 45)
Regarding claim 11, Li teaches the TSV of claim 1, further comprising a capping layer (Li, 316, fig. 3) forming a surface of the outer layer, wherein the capping layer comprises SiN or TaN (Li, para. 46).
Claim rejections - 35 USA § 102 or § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 9 is rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Li.
Regarding claim 9, Li teaches the TSV of claim 1, wherein the insulating layer comprises a SiO2 film.
Li does not explicitly state that it is deposited using a tetraethyl orthosilicate (TEOS) as a precursor. However, the insulating layer of Li is made of the same material (SiO2) as the claimed invention. Per MPEP 2113, "Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process."
Claim rejections - 35 USA § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3, 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Li.
Regarding claim 3, Li teaches the TSV of claim 1, but does not explicitly teach wherein the core is configured for operation at cryogenic temperatures and has a thermal conductivity of at least 200 W/m.
Li, does however teach that the core may be made of copper (Li, para. 46), which per para. 42 of the instant application has a thermal conductivity of approximately 385W/(m*K).
Thus, thermal conductivity of the core is dependent on the operating temperature.
This means that the operating temperature is not merely a process parameter but a result-effective variable:
If the operating temperature is too low, the thermal conductivity of the core will be insufficient and heat will build up causing damage to the components.
If the operating temperature is too high, the superconductive material will be above its critical temperature and will fail to perform as required
Within the optimal operating temperature range, thermal conductivity is maximized and damage is minimized, enabling reliable operation and reducing damage.
Because the prior art recognizes that a copper core is desirable, and the thermal conductivity is a result of the operating temperature the thermal conductivity is dependent on a result-effective variable. Therefore, it would have been obvious for one of ordinary skill in the art to optimize the operating temperature, and thus the thermal conductivity through routine experimentation. The selection of an operating temperature resulting in a thermal conductivity above 200 W/m would be a predictable result of such optimization, absent evidence of unexpected results or criticality associated specifically with the 200 W/m threshold (See MPEP 2144.05 II).
Regarding claim 6, Li teaches the TSV of claim 1, but does not explicitly teach wherein the outer layer comprises a thickness between 10-100 nm.
However, Li does state that it is advantageous to place multiple vias in close proximity (Li, para. 53). Small vias created through smaller individual components will result in greater via density on a given chip. Therefore, it would have been obvious for one of ordinary skill in the art to optimize this variable through routine experimentation.
Regarding claim 7, Li teaches the TSV of claim 1, wherein the insulating layer comprises a thickness of between 30 nm and 50 nm.
However, Li does state that it is advantageous to place multiple vias in close proximity (Li, para. 53). Small vias created through smaller individual components will result in greater via density on a given chip. Therefore, it would have been obvious for one of ordinary skill in the art to optimize this variable through routine experimentation.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Li, in view of Ramm et al. (US Pub 20230043673), hereinafter referred to as Ramm.
Regarding claim 5, Li teaches the TSV of claim 1, but does not teach wherein the outer layer has a critical temperature of greater than 5K.
However, Ramm teaches a superconducting layer element with a critical temperature of 17K (Ramm, para. 68).
Therefore it would have been obvious to one of ordinary skill, in the art at the time, to
modify the superconductor layer of Li according to the teachings of Ramm to create a
superconductor layer with a critical temperature greater than 10K lowering energy costs for cooling the device.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Das et al. (US Pub 20170373044).
Regarding claim 12, Li teaches the TSV of claim 1, further comprising a top contact (Li, 326 and 328, Fig. 3, the outer and inner conductive portions each have their own bumps).
Li does not explicitly teach wherein the top contact comprises: an indium bump that is electrically coupled to the outer layer; and a copper bump that is electrically coupled to the core.
However, Das teaches conductive structures wherein copper micro bumps (Das, 1422, Fig. 14a, para. 415) are used for the conductive portions and indium bumps (Das, 1514, Fig. 15, paras. 417-423) are used for cryogenic electronic packages.
Therefore it would have been obvious to one of ordinary skill in the art, before the filing date of the invention, to combine the TSV of Li with the copper and indium bumps of Das to create a top contact with a copper bump electrically coupled to the core and an indium bump electrically coupled to the outer layer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Watanabe et al. (US Pub 20230034867) teaches a TSV with a copper core and a superconducting outer layer.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 7:30-5:00.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893