Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim rejections - 35 USA § 102 or § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4 and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US Pub 20110139497), hereinafter referred to as Li, Abraham (US Pub. 20180005887) hereinafter referred to as Abraham and Watanabe (US Pub. 20230034867), hereinafter referred to as Watanabe.
Regarding claim 1, Li teaches a through-silicon via (TSV) comprising a core (Li, 310, Fig. 3, para. 46), wherein the core extends through a substrate along an axis, wherein the core comprises a conductive material (Li, para. 46); an outer layer (Li, 312, Fig. 3, para. 46), wherein the outer layer is disposed about the axis and at least partially surrounding the core, and an insulating layer (Li, 314, Fig. 3, para. 46), wherein the insulating layer electrically insulates the core and the outer layer from one another (Li, para. 46).
Li does not explicitly teach wherein the outer layer comprises a superconductive material; nor does it teach an intermetallic layer comprising a metal, wherein the intermetallic layer is disposed between the core and the insulating layer.
Li does teach wherein the outer layer can contain aluminum (Li, para. 46).
Additionally, Watanabe teaches a coaxial TSV (Watanabe, central conductor 110, external conductor 120, Fig. 2, para. 56). and explicitly states in paragraph [0070]: “Each of the central conductor 110 and the external conductor 120 is metal… or metal such as niobium (Nb) or aluminum (Al) that is made of a superconducting material.” Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to utilize the aluminum layer of Watanabe as the outer layer in order to provide superconductive capability by lowering the electrical resistivity (Watanabe, para. 70)
Finally, Abraham teaches a metallic wettabale stack layer (Abraham, 504, Fig. 10, para. 41) disposed directly on the core (Abraham, 702, Fig. 10, para. 43).
Therefore it would have been obvious to one having ordinary skill in the art to have combined the wettable stack layer of Abraham with the device of Li in order to ensure that substantially no voids are left in the via after manufacture (Abraham, para. 45).
Regarding claim 2, modified Li teaches the TSV of claim 1, wherein the core comprises at least one of: Cu, Ni, Co, or Al (Li, para. 46).
Regarding claim 3, modified Li teaches the TSV of claim 1, but does not explicitly teach wherein the core is configured for operation at cryogenic temperatures and has a thermal conductivity of at least 200 W/m.
Li, does however teach that the core may be made of copper (Li, para. 46), which per para. 42 of the instant application has a thermal conductivity of approximately 385W/(m*K).
Thus, thermal conductivity of the core is dependent on the operating temperature.
This means that the operating temperature is not merely a process parameter but a result-effective variable:
If the operating temperature is too low, the thermal conductivity of the core will be insufficient and heat will build up causing damage to the components.
If the operating temperature is too high, the superconductive material will be above its critical temperature and will fail to perform as required
Within the optimal operating temperature range, thermal conductivity is maximized and damage is minimized, enabling reliable operation and reducing damage.
Because the prior art recognizes that a copper core is desirable, and the thermal conductivity is a result of the operating temperature the thermal conductivity is dependent on a result-effective variable. Therefore, it would have been obvious for one of ordinary skill in the art to optimize the operating temperature, and thus the thermal conductivity through routine experimentation. The selection of an operating temperature resulting in a thermal conductivity above 200 W/m would be a predictable result of such optimization, absent evidence of unexpected results or criticality associated specifically with the 200 W/m threshold (See MPEP 2144.05 II).
Regarding claim 4, modified Li teaches the TSV of claim 1, wherein the outer layer comprises at least one of: NbTiN, NbN, Nb3Al, Nb, Ti, Al, Ta, or a combination of such materials (Li, para. 46).
Regarding claim 7, modified Li teaches the TSV of claim 1, but does not explicitly teach wherein the insulating layer comprises a thickness of between 30 nm and 50 nm.
However, Li does state that it is advantageous to place multiple vias in close proximity (Li, para. 53). Small vias created through smaller individual components will result in greater via density on a given chip.
Additionally, Watanabe teaches a wiring substrate with a central conductor (Watanabe, 110, Fig. 2, paras. 56, 70) surrounded by an insulating layer (Watanabe, 102, Fig. 2, para. 56) and further surrounded by an external conductor(Watanabe, 120, Fig. 2, paras. 56, 70). Watanabe further states that the width (Watanabe, W1, Fig 3, para. 69) of the insulating layer should be designed in such a way as to minimize the reflection when an electrical system is connected to both ends of the electrode and a signal is transmitted. Watanabe lists the circuit’s impedance, the signal’s frequency and the target reflection for the given circuit.
Because the prior art recognizes the thickness of the insulating layer directly affects the reflection of the signal and states that the thickness may be designed to make the reflection small, the reflection is a result affective variable.
Therefore, it would have been obvious for one of ordinary skill in the art to optimize this variable through routine experimentation. The selection of a thickness between 30 nm and 50 nm would be a predictable result of such optimization, absent evidence of unexpected results or criticality associated with the 30 nm to 50 nm range (See MPEP 2144.05 II)
Regarding claim 8, modified Li teaches the TSV of claim 1, wherein the insulating layer comprises at least one of: SiO2 or SiN (Li, para. 46).
Regarding claim 9, modified Li teaches the TSV of claim 1, wherein the insulating layer comprises a SiO2 film (Li, para. 46).
Li does not explicitly state that it is deposited using a tetraethyl orthosilicate (TEOS) as a precursor. However, the insulating layer of Li is made of the same material (SiO2) as the claimed invention. Per MPEP 2113, "Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process."
Regarding claim 10, modified Li teaches the TSV of claim 1, wherein the substrate comprises an interposer (Li, 304, fig. 3), wherein the interposer comprises silicon (Li, para. 45)
Claims 6 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Li and Krogstrup et al. (US Pub. 20230012371), hereinafter referred to as Krogstrup
Regarding claim 6, modified Li teaches the TSV of claim 1, but does not explicitly teach wherein the outer layer comprises a thickness between 10-100 nm.
However, Krogstrup teaches a superconducting component with 10 nm thickness (Krogstrup, para. 31). Therefore, it would have been obvious for one of ordinary skill in the art to adopt the thickness of Krogstrup in order to maximize the superconductive gap, thereby increasing the topological gap (Krogstrup, para. 31).
Regarding claim 11, Li teaches a through-silicon via (TSV) comprising a core (Li, 310, Fig. 3, para. 46), wherein the core extends through a substrate along an axis, wherein the core comprises a conductive material (Li, para. 46); an outer layer (Li, 312, Fig. 3, para. 46), wherein the outer layer is disposed about the axis and at least partially surrounding the core, wherein the outer layer comprises a superconductive material (Li, para. 46); and an insulating layer (Li, 314, Fig. 3, para. 46), wherein the insulating layer electrically insulates the core and the outer layer from one another (Li, para. 46).
Li also teaches a capping layer (Li, 316, fig. 3, para. 46) forming a surface of the outer layer, wherein the capping layer comprises SiN or TaN (Li, para. 46).
Li does not teach wherein the capping layer is disposed between the insulating layer and the outer layer, and wherein the capping.
However, Krogstrup teaches a semiconductor device wherein the core (Krogstrup, 10, Fig. 1(F), para. 29) has a stack consisting of; an insulating layer (Krogstrup, 14, Fig. 1F, para. 35), capped by a protective insulating component (Krogstrup, 16, Fig. 1(f), para. 55) and a superconducting element (Krogstrup, 12, Fig. 1(F), para. 31)
Therefore it would have been obvious to incorporate the capping layer of Krogstrup between the insulating and semiconductor layer of Li, using the materials of Li in order to protect the insulating component from etching, allowing a wider variety of etchant to be used (Krogstrup, para. 55).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Li and Abraham in view of Ramm et al. (US Pub 20230043673), hereinafter referred to as Ramm.
Regarding claim 5, modified Li teaches the TSV of claim 1, but does not teach wherein the outer layer has a critical temperature of greater than 5K.
However, Ramm teaches a superconducting layer element with a critical temperature of 17K (Ramm, para. 68).
Therefore it would have been obvious to one of ordinary skill, in the art at the time, to modify the superconductor layer of Li according to the teachings of Ramm to create a superconductor layer with a critical temperature greater than 10K lowering energy costs for cooling the device.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Li and Abraham in view of Das et al. (US Pub 20170373044), hereinafter referred to as Das.
Regarding claim 12, modified Li teaches the TSV of claim 1, further comprising a top contact (Li, 326 and 328, Fig. 3, the outer and inner conductive portions each have their own bumps).
Li does not explicitly teach wherein the top contact comprises: an indium bump that is electrically coupled to the outer layer; and a copper bump that is electrically coupled to the core.
However, Das teaches conductive structures wherein copper micro bumps (Das, 1422, Fig. 14a, para. 415) are used for the conductive portions and indium bumps (Das, 1514, Fig. 15, paras. 417-423) are used for cryogenic electronic packages.
Therefore it would have been obvious to one of ordinary skill in the art, before the filing date of the invention, to combine the TSV of Li with the copper and indium bumps of Das to create a top contact with a copper bump electrically coupled to the core and an indium bump electrically coupled to the outer layer.
Response to Arguments
Applicant’s arguments, see page 6, line 18-page 9, line 3, filed 6/18/2026, with respect to claim 1 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Li and Abraham.
Applicants’ arguments were directed to the addition of an intermetallic layer comprising a metal, wherein the intermetallic layer is disposed between the core and the insulating layer to the original claim 1. Li does not teach such a layer; however Abraham teaches a wetting layer situated directly outside the core and made of titanium and copper (Abraham, para. 41).
Applicants’ arguments, see page 9, line 4-page 11 line 2, filed 6/18/2026, with respect to 11 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Li and Krogstrup.
Applicants’ arguments were directed towards:
1. Claim 11 was changed from a dependent claim to an independent claim by incorporating all the limitations of original claim 1.
2. Adding the limitation wherein the capping layer is disposed between the insulating layer and the outer layer.
The new rejection is based on:
1. All limitations incorporated from original claim 1 are taught by Li.
2. Li teaches an external insulation layer made of the material required in original claim 11, however that layer is situated outside the outer layer, not between the insulating layer and outer layer. Krogstrup teaches a protective insulating component between the insulating layer and the superconducting element to protect the insulating component from etching,
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nanba (US Pub. 20210407928) teaches a quantum device that uses a conductive pillar surrounded by a superconducting core.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:30-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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