Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 15th, 2023, was filed prior to the mailing date of the first office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 9-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maxey et al. (2021/0391478 A1; hereinafter Maxey).
Regarding Claim 1, Maxey (annotated fig. 1C) teaches a semiconductor device ([0017], 100) comprising:
a stacked structure ([0018], [0025], 130I, 110, 112, 142) comprising a plurality of gate structures (plurality of 130I) alternately stacked with a plurality of dielectric layers (plurality of 112, 142); wherein
respective ones of the plurality of gate structures (130I) comprise a gate region (130I) and a gate dielectric layer ([0020], high-k dielectric between 130I and 110, not shown) disposed around the gate region (130I); wherein
respective ones of the plurality of dielectric layers (142) are disposed between a first two-dimensional semiconductor material layer (110, referred to as first two-dimensional material, see annotated fig. 1C) of a plurality of two-dimensional semiconductor material layers (plurality of 110) and a second two-dimensional semiconductor material layer (110, referred to as second two-dimensional material, see annotated fig. 1C) of the plurality of two-dimensional semiconductor material layers (plurality of 110); and wherein
the gate dielectric layer (high-k dielectric between 130I and 110) of the respective ones of the plurality of gate structures (plurality of 130I) contacts at least one of the plurality of two-dimensional semiconductor material layers (plurality of 110).
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Annotated Figure 1C
Regarding Claim 2, Maxey (annotated fig. 1C) teaches the semiconductor device of claim 1, further comprising at least one source/drain region ([0021], 105) disposed on a side of the stacked structure (130I, 110, 112, 142), wherein sides of respective ones of the plurality of two-dimensional semiconductor material layers (plurality of 110) and sides of the respective ones of the plurality of dielectric layers (plurality of 112, 142) are disposed (110 and 112 are disposed on 105, see annotated fig. 1C) on a side of the at least one source/drain region (105).
Regarding Claim 3, Maxey (annotated fig. 1C) teaches the semiconductor device of claim 2, wherein the sides of the respective ones of the plurality of two-dimensional semiconductor material layers (plurality of 110) and the sides of the respective ones of the plurality of dielectric layers (plurality of 112, 142) contact (see annotated fig. 1C) the side of the at least one source/drain region (105).
Regarding Claim 4, Maxey (annotated fig. 1C) teaches the semiconductor device of claim 3, wherein: the stacked structure (130I, 110, 112, 142) further comprises a plurality of spacers ([0021], plurality of 122) disposed on sides of the plurality of gate structures (130I) at least one of over and under the respective ones of the plurality of dielectric layers (plurality of 112, 142); and sides of respective ones of the plurality of spacers (plurality of 122) contact (see annotated fig. 1C) the side of the at least one source/drain region (105).
Regarding Claim 5, Maxey (annotated fig. 1C) teaches the semiconductor device of claim 2, wherein: the stacked structure (130I, 110, 112, 142) further comprises a plurality of spacers ([0021], plurality of 122) disposed on sides of the plurality of gate structures (130I) at least one of over and under the respective ones of the plurality of dielectric layers (plurality of 112, 142); and sides of respective ones of the plurality of spacers (plurality of 122) are coplanar (see annotated fig. 1C) with the sides of the respective ones of the plurality of two-dimensional semiconductor material layers (plurality of 110) disposed on the side of the at least one source/drain region (105).
Regarding Claim 6, Maxey (annotated fig. 1C) teaches the semiconductor device of claim 2, wherein: the stacked structure (130I, 110, 112, 142) further comprises a plurality of spacers ([0021], plurality of 122) disposed on sides of the plurality of gate structures (130I) at least one of over and under the respective ones of the plurality of dielectric layers (plurality of 112, 142); and sides of respective ones of the plurality of spacers (plurality of 122) are coplanar (see annotated fig. 1C) with the sides of the respective ones of the plurality of dielectric layers (plurality of 112, 142) disposed on the side of the at least one source/drain region (105).
Regarding Claim 9, Maxey (annotated fig. 1C) teaches the semiconductor device of claim 1, wherein respective ones of the plurality of two-dimensional semiconductor material layers (plurality of 110) are thinner (see annotated fig. 1C) than the respective ones of the plurality of dielectric layers (plurality of 112, 142).
Regarding Claim 10, Maxey (annotated fig. 1C) teaches a semiconductor device ([0017], 100) comprising:
a nanosheet structure ([0018], [0025], 130I, 110, 112, 142) comprising: a plurality of gate structures (plurality of 130I) alternately stacked with a plurality of dielectric layers (plurality of 112, 142); and
a plurality of two-dimensional semiconductor material layers (plurality of 110), wherein respective ones of the plurality of two-dimensional semiconductor material layers (plurality of 110) are disposed between (see annotated fig. 1C) adjacent ones of the plurality of gate structures (plurality of 130I) and the plurality of dielectric layers (plurality of 112, 142); and
at least one source/drain region ([0021], 105) disposed on a side of the nanosheet structure (130I, 110, 112, 142), wherein the at least one source/drain region (105) comprises a different material ([0019], 110 may be a 2D semiconductor material, [0021], 105 may be a conductive material) from the two-dimensional semiconductor material layers (plurality of 110); wherein
respective ones of the plurality of gate structures (130I) contact (see annotated fig. 1C) at least one of the plurality of two-dimensional semiconductor material layers (110).
Regarding Claim 11, Maxey (annotated fig. 1C) teaches the semiconductor device of claim 10, wherein the respective ones of the plurality of gate structures (130I) comprise a gate region (130I) and a gate dielectric layer ([0020], high-k dielectric between 130I and 110, not shown) disposed around the gate region (130I).
Regarding Claim 12, Maxey (annotated fig. 1C) teaches the semiconductor device of claim 10, wherein sides of the respective ones of the plurality of two-dimensional semiconductor material layers (plurality of 110) and sides of respective ones of the plurality of dielectric layers (plurality of 112, 142) contact (see annotated fig. 1C) a side of the at least one source/drain region (105).
Regarding Claim 13, Maxey (annotated fig. 1C) teaches the semiconductor device of claim 12, wherein: the nanosheet structure (130I, 110, 112, 142) further comprises a plurality of spacers ([0021], plurality of 122) disposed on sides of the plurality of gate structures (plurality of 130I) at least one of over and under the respective ones of the plurality of dielectric layers (plurality of 112, 142); and sides of respective ones of the plurality of spacers (plurality of 122) contact (see annotated fig. 1C) the side of the at least one source/drain region (105).
Regarding Claim 14, Maxey (annotated fig. 1C) teaches the semiconductor device of claim 13, wherein the sides of the respective ones of the plurality of spacers (plurality of 122) are coplanar (see annotated fig. 1C) with the sides of the respective ones of the plurality of two-dimensional semiconductor material layers (plurality of 110).
Regarding Claim 15, Maxey (annotated fig. 1C) teaches the semiconductor device of claim 13, wherein the sides of the respective ones of the plurality of spacers (plurality of 122) are coplanar (see annotated fig. 1C) with the sides of the respective ones of the plurality of dielectric layers (plurality of 112, 142).
Regarding Claim 16, Maxey (annotated fig. 1C) teaches the semiconductor device of claim 10, wherein the respective ones of the plurality of two-dimensional semiconductor material layers (plurality of 110) are thinner (see annotated fig. 1C) than respective ones of the plurality of dielectric layers (plurality of 112, 142).
Regarding Claim 17, Maxey (annotated fig. 1C) teaches the semiconductor device of claim 10, wherein respective ones of the plurality of dielectric layers (plurality of 112, 142) are wider (the length of a dielectric layer 112, 142 is wider than 130I, see annotated fig. 1C) than the respective ones of the plurality of gate structures (plurality of 130I).
Regarding Claim 18, Maxey (annotated fig. 1C) teaches a semiconductor device ([0017], 100) comprising:
a nanosheet structure ([0018], [0025], 130I, 110, 112, 142) comprising: a plurality of gate structures (plurality of 130I) alternately stacked with a plurality of dielectric layers (plurality of 112, 142); and
a plurality of spacers ([0021], plurality of 122) disposed on sides of the plurality of gate structures (plurality of 130I) at least one of over and under respective ones of the plurality of dielectric layers (plurality of 112, 142); and
at least one source/drain region ([0021], 105) disposed on a side of the nanosheet structure (130I, 110, 112, 142); wherein
sides of the respective ones of the plurality of dielectric layers (plurality of 112, 142) contact (see annotated fig. 1C) a side of the at least one source/drain region (105); and wherein
sides of respective ones of the plurality of spacers (plurality of 122) contact the side of the at least one source/drain region (105) and are coplanar (see annotated fig. 1C) with the sides of the respective ones of the plurality of dielectric layers (plurality of 112, 142).
Regarding Claim 19, Maxey (annotated fig. 1C) teaches the semiconductor device of claim 18, wherein: the nanosheet structure (130I, 110, 112, 142) further comprises a plurality of two-dimensional semiconductor material layers (plurality of 110); and respective ones of the plurality of two-dimensional semiconductor material layers (plurality of 110) are disposed between adjacent ones of the plurality of gate structures (plurality of 130I) and the plurality of dielectric layers (plurality of 112, 142).
Regarding Claim 20, Maxey (annotated fig. 1C) teaches the semiconductor device of claim 19, wherein a gate dielectric layer ([0020], high-k dielectric between 130I and 110, not shown) of respective ones of the plurality of gate structures (plurality of 130I) contacts (see annotated fig. 1C) at least one of the plurality of two-dimensional semiconductor material layers (plurality of 110).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Maxey as applied to Claim 2 above, and further in view of Baek et al. (2020/0098862 A1; hereinafter Baek).
Regarding Claim 7, Maxey doesn’t explicitly teach the semiconductor device of claim 2, wherein the at least one source/drain region comprises amorphous silicon.
However, Baek (fig. 1) teaches the at least one source/drain region ([0045], 160) comprises amorphous silicon ([0013]) while still obtaining the predictable result of a source/drain region.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the source/drain material of Baek for the source/drain material of Maxey, since simple substitution of source/drain materials for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding Claim 8, Maxey doesn’t explicitly teach the semiconductor device of claim 2, wherein the at least one source/drain region comprises an epitaxial semiconductor material.
However, Baek (fig. 1) teaches the at least one source/drain region ([0045], 160) comprises an epitaxial semiconductor material ([0055]) while still obtaining the predictable result of a source/drain region.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the source/drain material of Baek for the source/drain material of Maxey, since simple substitution of source/drain materials for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Conclusion
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 February 19, 2026