Detailed Action
This office action is in response to the amendment filed on May 26th, 2026. Claims 1-18 and 21-22 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed May 26th, 2026, have been fully considered but they are not persuasive.
Applicant argues (pgs. 7-9, “Remarks”) that Maxey fails to teach the limitations presented in amended Claims 1, 10, and 18.
However, as seen below, Claims 1 and 10 are now rejected by Gardner. Claim 18 is now rejected by Cheng and Yassine.
Therefore, applicant’s arguments are not persuasive and are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 9-17, and 21-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gardner et al. (2023/0114024 A1; hereinafter Gardner).
Regarding Claim 1, Gardner (fig. 1A) teaches a semiconductor device ([0038], 100) comprising:
a stacked structure ([0038], 250, 115, 235) comprising a plurality of gate structures (plurality of 235) alternately stacked with a plurality of dielectric layers ([0033], plurality of 115 may be dielectric); wherein
respective ones of the plurality of gate structures (235) comprise a gate region ([0039], 145) and a gate dielectric layer ([0039], 140) disposed around the gate region (145); wherein
respective ones of the plurality of dielectric layers (115) are disposed between a first two-dimensional semiconductor material layer (first 250, see fig. 1A) of a plurality of two-dimensional semiconductor material layers (plurality of 250) and a second two-dimensional semiconductor material layer (second 250, see fig. 1A) of the plurality of two-dimensional semiconductor material layers (plurality of 250); wherein
the gate dielectric layer (140) of the respective ones of the plurality of gate structures (plurality of 245) contacts at least one of the plurality of two-dimensional semiconductor material layers (plurality of 250); and wherein
each dielectric layer (115) of the plurality of dielectric layers (plurality of 115) is a continuous layer of a same dielectric material that extends along an entire length (see fig. 1A) of the first two-dimensional semiconductor material layer (first 250) and the second two-dimensional semiconductor material layer (second 250) between which the dielectric layer (115) is disposed.
Regarding Claim 2, Gardner (fig. 1A) teaches the semiconductor device of claim 1, further comprising at least one source/drain region ([0039], 220) disposed on a side of the stacked structure (250, 115, 235), wherein sides of respective ones of the plurality of two-dimensional semiconductor material layers (plurality of 250) and sides of the respective ones of the plurality of dielectric layers (plurality of 115) are disposed on a side of the at least one source/drain region (220).
Regarding Claim 3, Gardner (fig. 1A) teaches the semiconductor device of claim 2, wherein the sides of the respective ones of the plurality of two-dimensional semiconductor material layers (plurality of 250) and the sides of the respective ones of the plurality of dielectric layers (plurality of 115) contact the side of the at least one source/drain region (220).
Regarding Claim 4, Gardner (fig. 1A) teaches the semiconductor device of claim 3, wherein: the stacked structure (250, 115, 235) further comprises a plurality of spacers ([0040], plurality of 125) disposed on sides of the plurality of gate structures (235) at least one of over and under the respective ones of the plurality of dielectric layers (plurality of 115); and sides of respective ones of the plurality of spacers (plurality of 125) contact the side of the at least one source/drain region (220).
Regarding Claim 5, Gardner (fig. 1A) teaches the semiconductor device of claim 2, wherein: the stacked structure (250, 115, 235) further comprises a plurality of spacers ([0040], plurality of 125) disposed on sides of the plurality of gate structures (235) at least one of over and under the respective ones of the plurality of dielectric layers (plurality of 115); and sides of respective ones of the plurality of spacers (plurality of 125) are coplanar with the sides of the respective ones of the plurality of two-dimensional semiconductor material layers (plurality of 250) disposed on the side of the at least one source/drain region (220).
Regarding Claim 6, Gardner (fig. 1A) teaches the semiconductor device of claim 2, wherein: the stacked structure (250, 115, 235) further comprises a plurality of spacers ([0040], plurality of 125) disposed on sides of the plurality of gate structures (235) at least one of over and under the respective ones of the plurality of dielectric layers (plurality of 115); and sides of respective ones of the plurality of spacers (plurality of 125) are coplanar with the sides of the respective ones of the plurality of dielectric layers (plurality of 115) disposed on the side of the at least one source/drain region (220).
Regarding Claim 9, Gardner (fig. 1A) teaches the semiconductor device of claim 1, wherein respective ones of the plurality of two-dimensional semiconductor material layers (plurality of 250) are thinner (see fig. 1A) than the respective ones of the plurality of dielectric layers (plurality of 115).
Regarding Claim 10, Gardner (fig. 1A) teaches a semiconductor device ([0038], 100) comprising:
a nanosheet structure ([0039], 250, 115, 235) comprising: a plurality of gate structures (plurality of 235) alternately stacked with a plurality of dielectric layers ([0033], plurality of 115 may be dielectric); and
a plurality of two-dimensional semiconductor material layers (plurality of 250), wherein respective ones of the plurality of two-dimensional semiconductor material layers (plurality of 250) are disposed between adjacent ones of the plurality of gate structures (plurality of 235) and the plurality of dielectric layers (plurality of 115);
a first source/drain region ([0039], 220) disposed on a first side of the nanosheet structure (250, 115, 235); and
a second source/drain region ([0039], 215) disposed on second side of the nanosheet structure (250, 115, 235); wherein
the first source/drain region (220) and the second source/drain region (215) are comprised of a different material ([0030], 250 is formed from 2D semiconducting materials; [0039], 220 and 215 are formed from metal) from the two-dimensional semiconductor material layers (plurality of 250); wherein
respective ones of the plurality of gate structures (235) contact at least one of the plurality of two-dimensional semiconductor material layers (plurality of 250); and wherein
each dielectric layer (115) of the plurality of dielectric layers (plurality of 115) is a continuous layer of a same dielectric material with a first end of the dielectric layer (115) in contact with the first source/drain region (220) and a second end of the dielectric layer (115) in contact with the second source/drain region (215).
Regarding Claim 11, Gardner (fig. 1A) teaches the semiconductor device of claim 10, wherein the respective ones of the plurality of gate structures (235) comprise a gate region ([0039], 145) and a gate dielectric layer ([0039], 140) disposed around the gate region (145).
Regarding Claim 12, Gardner (fig. 1A) teaches the semiconductor device of claim 10, wherein sides of the respective ones of the plurality of two-dimensional semiconductor material layers (plurality of 250) and sides of respective ones of the plurality of dielectric layers (plurality of 115) contact a side of the first one source/drain region (220) and a side of the second source/drain region (215).
Regarding Claim 13, Gardner (fig. 1A) teaches the semiconductor device of claim 12, wherein: the nanosheet structure (250, 115, 235) further comprises a plurality of spacers ([0040], plurality of 125) disposed on sides of the plurality of gate structures (plurality of 235) at least one of over and under the respective ones of the plurality of dielectric layers (plurality of 115); and sides of respective ones of the plurality of spacers (plurality of 125) contact one of the side of the first source/drain region (220) and the side of the second source/drain region (215).
Regarding Claim 14, Gardner (fig. 1A) teaches the semiconductor device of claim 13, wherein the sides of the respective ones of the plurality of spacers (plurality of 125) are coplanar with the sides of the respective ones of the plurality of two-dimensional semiconductor material layers (plurality of 250).
Regarding Claim 15, Gardner (fig. 1A) teaches the semiconductor device of claim 13, wherein the sides of the respective ones of the plurality of spacers (plurality of 125) are coplanar with the sides of the respective ones of the plurality of dielectric layers (plurality of 115).
Regarding Claim 16, Gardner (fig. 1A) teaches the semiconductor device of claim 10, wherein the respective ones of the plurality of two-dimensional semiconductor material layers (plurality of 250) are thinner (see fig. 1A) than respective ones of the plurality of dielectric layers (plurality of 115).
Regarding Claim 17, Gardner (fig. 1A) teaches the semiconductor device of claim 10, wherein respective ones of the plurality of dielectric layers (plurality of 115) are wider (115 is wider than 145 from the gate structure 235) than the respective ones of the plurality of gate structures (plurality of 245).
Regarding Claim 21, Gardner (fig. 1A) teaches the semiconductor device of claim 1, wherein each dielectric layer of the plurality of dielectric layers (plurality of 115) is formed of a material comprising at least silicon and nitrogen ([0027], dielectrics may be silicon nitride).
Regarding Claim 22, Gardner (fig. 1A) teaches the semiconductor device of claim 10, wherein each dielectric layer of the plurality of dielectric layers (plurality of 115) is formed of a material comprising at least silicon and nitrogen ([0027], dielectrics may be silicon nitride).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Gardner as applied to Claim 2 above, and further in view of Baek et al. (2020/0098862 A1; hereinafter Baek).
Regarding Claim 7, Gardner doesn’t explicitly teach the semiconductor device of claim 2, wherein the at least one source/drain region comprises amorphous silicon.
However, Baek (fig. 1) teaches the at least one source/drain region ([0045], 160) comprises amorphous silicon ([0013]) while still obtaining the predictable result of a source/drain region.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the source/drain material of Baek for the source/drain material of Gardner, since simple substitution of source/drain materials for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding Claim 8, Gardner doesn’t explicitly teach the semiconductor device of claim 2, wherein the at least one source/drain region comprises an epitaxial semiconductor material.
However, Baek (fig. 1) teaches the at least one source/drain region ([0045], 160) comprises an epitaxial semiconductor material ([0055]) while still obtaining the predictable result of a source/drain region.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the source/drain material of Baek for the source/drain material of Gardner, since simple substitution of source/drain materials for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (2024/0379800 A1; hereinafter Cheng) in view of Yassine et al. (6,465,266 B1; hereinafter Yassine).
Regarding Claim 18, Cheng (fig. 16B) teaches a semiconductor device ([0047], 88) comprising:
a test device (88) comprising a nanosheet structure ([0016], 22B-I, [0038], 70) comprising: a plurality of gate structures (plurality of 70) alternately stacked with a plurality of dielectric layers (plurality of 22B-I) with each dielectric layer (22B-I) in direct contact with at least one gate structure (70) of the plurality of gate structures (plurality of 70); and
a plurality of spacers ([0027], plurality of 44) disposed on sides of the plurality of gate structures (plurality of 70) at least one of over and under respective ones of the plurality of dielectric layers (plurality of 22B-I);
a first source/drain region ([0043], right 82) disposed on a first side of the nanosheet structure (22B-I, 70); and
a second source/drain region (middle 82) disposed on second side of the nanosheet structure (22B-I, 70); wherein
sides each dielectric layer of the plurality of dielectric layers (plurality of 22B-I) has a first end in contact with a side of the first source/drain region (right 82), and
a second end in contact with a side of the second source/drain region (middle 82); wherein
each gate structure (70) comprises a gate metal layer ([0035], 68) and a gate dielectric layer ([0035], 64) with the gate dielectric layer (64) in direct contact with one or more of the dielectric layers (22B-I); and wherein
the test device is configured for gate to source/drain qualification testing.
Cheng doesn’t teach a semiconductor device is a test device and the test device is configured for gate to source/drain qualification testing.
However, Yassine (fig. 2A) teaches a semiconductor device is a test device (Col. 4, Lines 1-13; device) and the test device is configured for gate to source/drain qualification testing (Col. 4, Lines 1-34; device may be testing source/drain/gate for leakage currents and oxide defects). Yassine also teaches this determines causes for possible electrical shorts (Col. 5, Lines 65-67).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Cheng to include the testing configuration of Yassine to detect electrical short causes.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Naylor et al. (2023/0420511 A1) teaches a transistor device with stacked channel layers and insulating layers.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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