DETAILED ACTION
Response to Amendment/Arguments
The amendment filed on 05/28/2026 has been entered.
Claims 1-14, 29-30 and 33-34 are cancelled.
Claims 15-17, 20, 27-28 and 31-32 are amended.
Claims 35-38 are new.
Claims 15-28, 31-32 and 35-38 are pending.
Claims 17-19, 23 and 26 are withdrawn from consideration.
Claims 15-16, 20-22, 24-25, 27-28, 31-32 and 35-38 are examined herein.
Applicant’s arguments filed 05/28/2026 have been fully considered. Applicant argues that Miyakoshi and Komorita do not disclose a second electronic component “disposed next to the second line layer on the second insulation layer,” because every component in those references is disposed on a metal layer (Remarks, pp 9-10). The examiner agrees that Miyakoshi and Komorita do not disclose this feature. However, the argument is moot because the new ground of rejection relies on Lee for this limitation. Lee discloses a control part bonded to the insulating ceramic substrate, without a metal layer, beside the metal layer that carries the power devices (Figs. 2 and 4; ¶¶0081-0084, 0092-0094). The new ground of rejection was necessitated by Applicant’s amendment.
To the extent Applicant contents that the claimed component must be disposed on “the insulation board itself,” i.e., in direct contact with it (Remarks, p. 9), the argument is not commensurate with the scope of the claims. As explained in the Claim Interpretation section below, the claims themselves use “on the second insulation layer” to encompass a component separated from the insulation layer by intervening structure, and the claims do not recite direct contact. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993) (limitations not appearing in the claims cannot be relied upon for patentability).
Regarding the dependent claims, Applicant relies on the arguments presented for the independent claims. Those arguments are addressed above. The additional features of claims 20-22, 24-25 and 35-38 are addressed in the rejections below.
Applicant’s request for rejoinder is noted. Withdrawn claims that depend from or otherwise require all the limitations of an allowable claim will be considered for rejoinder upon a finding of allowability. See MPEP 821.04.
Claim Status Identifiers
Claim 26 was withdrawn from consideration in the Office Action mailed on 03/09/2026 but is identified as “(Previously Presented)” in the amendment filed on 05/28/2026. Applicant is advised that the status identifier of each claim must accurately indicate its status. See 37 CFR 1.121(c). In any future amendment, claim 26 should be identified as “(Withdrawn).”
Claim Interpretation
The interpretations of claims 24 and 25 set forth in the previous Office Action mailed on 03/09/2026 are maintained.
“electronic component”: Applicant’s specification states that each of the first and second electronic components “may include one or more active components” and may further include passive components, including but not limited to “a resistor, capacitor, inductor, filter, coupler, and the like” (¶0088). The term is thus not limited to a single bare semiconductor chip. This is consistent with its ordinary usage in the art, for example:
Kanai et al. (US 20220415749 A1), ¶0026, describes an insulated circuit board together with semiconductor elements mounted on it as an “electronic component 30.”
Li et al. (US 20160352247 A1), ¶0038, describes a controlling device that “may be a resistor, a capacitor, a semiconductor device, a chip, etc.”
Accordingly, an assembly such as a control chip mounted on a printed circuit board is interpreted as an “electronic component.”
“disposed ... on the second insulation layer”: Independent claims 15, 27 and 31 recite that one of the second electronic components “is disposed on the second line layer and the second insulation layer.” That component is separated from the second insulation layer by the second line layer. The claims themselves therefore use “on the second insulation layer” to include a component that is over, but not in direct contact with, the insulation layer. See also ¶ 0078 (component 4 “disposed on the second circuit substrate 2” while located on line layer 21).
Consistent with this usage, “disposed next to the second line layer on the second insulation layer” is interpreted as a component located laterally beside the second line layer (i.e., not on the second line layer) and over the second insulation layer. The component may be directly on the insulation layer or separated from it by intervening structure such as a bonding layer. The claims do not recite that the component directly contacts the insulation layer.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 15-16, 20-22, 24-25, 27-28, 31-32 and 35-38 are rejected under 35 U.S.C. 112(a), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Independent claims 15, 27 and 31, as amended, recite “another at least one of the plurality of second electronic components is disposed next to the second line layer on the second insulation layer.” The written description does not describe this arrangement. The specification states that “the second electronic component 4 is located on the second line layer 21 and is electrically connected to the second line layer 21. It may be understood that the first electronic component 3 may alternatively not be electrically connected to the first line layer 11, and the second electronic component 4 may alternatively not be electrically connected to the second line layer 21” (¶ 0079). That alternative addresses only the electrical connection of component 4. It does not alter the stated location of component 4 on the second line layer. A component may be physically located on a line layer yet electrically isolated from it, as is known in the art. See, for example, Tan et al. (US 20110024086 A1), ¶0040 (die 30 having an electrically insulated bottom thermal pad that is soldered to the copper portion 28 in Fig. 1).
Likewise, the specification describes the back surfaces of the electronic components as disposed or mounted on the first and second line layers (¶0088). The generic statement that component 4 “is disposed on the second circuit substrate 2” (¶ 0078) does not describe the specific arrangement now claimed. Every specific placement disclosed is on the line layer, and nothing in the original disclosure directs one skilled in the art to a component located on the insulation layer beside the line layer. Furthermore, Applicant’s remarks do not identify where support for the amendment may be found. See MPEP 2163(II)(A) and 714.02.
It appears that the only possible support is the right-hand element of Figs. 1 and 5 which show a lead line to reference numeral 4. That element:
is drawn as a single outline block, partially cross-hatched in the similar/same manner of line layer 21;
is positioned at the same level as line layer 21;
carries a vertical pin extending through package body 5; and
receives a conducting wire 8.
These features are consistent with a portion of the line layer carrying an external terminal of a conventional power-module construction. See, for example, the following:
Miyakoshi (US 20160365307 A1): Figs. 1A, 1B, ¶¶ 0024-0025 and 47: external terminals 52, 54, and 55 (see Fig. 1B) are soldered to metal layers 12a2, 12b2, 12b3 (see Fig. 1A) and extending out of the sealing resin (see Fig. 1B).
Higashi et al. (US 20230069967 A1): Fig. 4 and ¶ 0030: main terminal 17 bonded to a circuit board island 62 of the insulating substrate and extending out of the package; ¶ 0030 describes the circuit boards as islands that “may also be referred to as circuit layers.”
The specification contains no description of this element as an electronic component disposed on the insulation layer. Given the specification’s statements that component 4 is located on the line layer, the schematic drawings do not clearly convey the claimed arrangement. Dependent claims 16, 20-22, 24-25, 28, 32 and 35-38 are rejected for incorporating this limitation.
Claim 36 is further rejected under 35 U.S.C. 112(a). Claim 36 recites that the component “disposed next to the second line layer on the second insulation layer” has the same thickness as the second line layer. The specification is silent as to the thickness of any electronic component relative to the line layer and the drawings, which are schematics, do not show any specific measurements or dimensions regarding said thickness. Patent drawings do not define the precise proportions of the elements and may not be relied on to show particular sizes where the specification is completely silent on the issue (When the reference does not disclose that the drawings are to scale and is silent as to dimensions, arguments based on measurement of the drawing features are of little value. See Hockerson-Halberstadt, Inc. v. Avia Group Int’l, 222 F.3d 951, 956, 55 USPQ2d 1487, 1491 (Fed. Cir. 2000). "[I]t is well established that patent drawings do not define the precise proportions of the elements and may not be relied on to show particular sizes if the specification is completely silent on the issue."); See MPEP 2125.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-16, 20-22, 24-25, 27-28, 31-32 and 38 are rejected under 35 U.S.C. 103 as being unpatentable over MIYAKOSHI (US 20160365307 A1, cited in previous action), hereinafter “Miyakoshi,” in view of KOMORITA et al. (US 6232657 B1, cited in previous action), hereinafter “Komorita,” and LEE et al. (US 20130069210 A1), hereinafter “Lee.”
Re: Independent Claim 15, Miyakoshi discloses a device (Fig. 6B: semiconductor device 200), comprising:
a first circuit substrate (Fig. 6B: insulated circuit board 10a), comprising a first line layer and a first insulation layer that are sequentially stacked (Fig. 6B: surface metal layer 12a1, i.e., first line layer, and insulation board 11a, i.e., first insulation layer), wherein at least one first electronic component is disposed on the first circuit substrate (Fig. 6B: transistor 1a, i.e., first electronic component disposed on insulated circuit board 10a; see ¶¶0039 and 0041); and
a second circuit substrate (Fig. 6B: insulated circuit board 10b), comprising a second line layer and a second insulation layer that are sequentially stacked (Fig. 6B: surface metal layer 12b1, i.e., second line layer, and insulation board 11b, i.e., second insulation layer; Fig. 6A also shows additional components which are not obvious in Fig. 6B);
a plurality of second electronic components (Fig. 6A shows electronic components 1b; ¶0023: As shown in the plan view of FIG. 6A and the cross-sectional diagram FIG. 6B, the semiconductor device 200 has an... insulated circuit board 10b to which are bonded three diodes 1b), wherein at least one of the plurality of second electronic components is disposed on the second line layer and the second insulation layer (¶¶0039 and 0041: diodes 1b bonded to metal layer 12b1),
...
While Miyakoshi discloses that the insulation boards may be made of ceramics such as alumina, aluminum nitride or silicon nitride (See ¶0045), Miyakoshi does not specifically disclose the following features:
and another at least one of the plurality of second electronic components is disposed next to the second line layer on the second insulation layer;
wherein a thermal conductivity of the first insulation layer is higher than a thermal conductivity of the second insulation layer.
In a similar field of endeavor, Komorita discloses wherein a thermal conductivity of the first insulation layer is higher than a thermal conductivity of the second insulation layer (Fig. 9: substrate 302 shows an insulation layer Si3N4 and an insulation layer 302a Al2O3; col. 11, lns. 31-36: In the present invention, the two kinds of substrates i.e., the high thermal conductive silicon nitride substrate having a thermal conductivity of 60 w/m·k or more and the cheap substrate for general use having a thermal conductivity of less than 60 w/m·k are selectively used according to the required properties for the circuit board.; col. 29, lns. 13-17: alumina (Al2O3) substrates for Examples 7 to 9, having a thermal conductivity k of 20 w/m·k).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, to have modified the circuit board disclosed by Miyakoshi to include materials having different thermal conductivities, as disclosed by Komorita. One would do so in order to selectively use a material with a high thermal conductivity material for the part of the substrate where structural strength and heat releasing properties are required, and a cheap, easily produced material for other parts (See Komorita, col. 11, lns. 31-43 and col. 12, lns. 4-10).
Miyakoshi as modified by Komorita does not specifically disclose and another at least one of the plurality of second electronic components is disposed next to the second line layer on the second insulation layer
In a similar field of endeavor, Lee discloses and another at least one of the plurality of second electronic components is disposed next to the second line layer on the second insulation layer (Fig. 2 shows metal layer 201 is formed on the substrate 110 with chips 161 and lead frame 151, see ¶0081. In an adjacent region, a control part is bonded to upper surface of substrate 110 by bonding layer 133, without a metal layer. The control part comprises control chip 163 mounted on PCB 140 and is an electronic component. It is disposed next to metal layer 201 on the insulation layer, see ¶¶0063, 0068, 0081-0082; See also ¶¶0092-0094 and Fig. 4; ¶¶0082-0083: bonding layer 133 may be a non-conductive epoxy of low thermal conductivity, which thermally separates the control device from the power devices; See ¶0084 and ¶0094: metal layer is reduced, thereby making it possible to reduce a manufacturing cost of a product);
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have further modified the second circuit substrate of Miyakoshi as modified by Komorita. The modification would dispose an additional electronic component, namely a control part such as Lee’s control chip 163 on printed circuit board 140 (Lee, Fig. 2), on a region of the second insulation layer next to the second line layer, without an intervening metal layer, as taught by Lee. One would do so to integrate control circuitry for the power devices into the module (see Lee, ¶¶0014, 0065 and 0106) and additionally to thermally separate the heat-vulnerable control device from the power devices, thus protecting the control device (Lee, ¶¶0013, 0064, 0083, and 0105). Furthermore, it would be possible to reduce metal layer usage and manufacturing costs (see Lee ¶¶0084 and 0094).
Re: Claim 16, the combination of Miyakoshi, Komorita and Lee discloses the device according to claim 15.
Miyakoshi further discloses wherein: the second line layer is electrically connected to the first line layer through a conducting ... (Fig. 6B shows a first line layer 12a1 electrically connected to a second line layer 12b1; ¶0005: bonding wires for electrical connection),
Miyakoshi connects its semiconductor elements through conductive pins and a printed wiring board (See Figs. 6A and 6B). Miyakoshi also acknowledges that power semiconductor devices often use bonding wires for the electrical connection between semiconductor elements (See ¶0005: bonding wires for electrical connection).
However, Miyakoshi does not specifically disclose ... wire, wherein a first end of the first conducting wire is physically attached to the at least one first electronic component, and a second end of the first conducting wire is physically attached to the at least one of the plurality of second electronic components that is disposed on the second line layer and the second insulation layer, and the first conducting wire is continuous between the first end and the second end.
Lee further discloses ... wire (¶0075: wires 170 each electrically connecting between...), wherein a first end of the first conducting wire is physically attached to the at least one first electronic component (See Figs. 1 and 2 which show wires attached to components, e.g., a first end of wire 170 is physically attached to a first electronic component 163 or 170; ¶0103: power module package is divided into a power part A and a control part B and the second substrate 140 of the control part B and the first lead frame 151 of the power part A are connected to each other using the wire 170; also see Figs. 3 and 4; ), and
a second end of the first conducting wire is physically attached to the at least one of the plurality of second electronic components that is disposed on the second line layer and the second insulation layer (See Figs. 1 and 2 which show wires attached to components, e.g., wire 170 connects from 163 to 161; also see ¶0075, ¶0103 and Figs. 3/4), and
the first conducting wire is continuous between the first end and the second end (See Figs. 1 and 2 which show a continuous connection using wire 170; also see Figs. 3 and 4).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have connected the first electronic component directly to the second electronic component of the combination by a continuous bonding wire, as taught by Lee. This is the simple substitution of one known interconnection for another with predictable results: a bonding wire, which Miyakoshi acknowledges as conventional (see Miyakoshi, ¶0005) and which Lee uses to connect components directly, including components on separate mounting bases. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007); MPEP 2143(I)(B).
Re: Claim 20, the combination of Miyakoshi in view of Komorita and Lee discloses the device according to claim 15.
Lee further discloses wherein a material of the first insulation layer comprises AIN (¶0050: ceramic substrate may be AlN, SiN and Al2O3), and
a material of the second insulation layer comprises Al203 (¶0050: ceramic substrate may be AlN, SiN and Al2O3).
Furthermore, Miyakoshi discloses insulation boards of aluminum nitride or alumina (¶0043: ceramics such as alumina, aluminum nitride or silicon nitride). Komorita discloses a lower thermal-conductivity Al2O3 substrate 302a (Fig. 9; col. 11, lns. 27-30) and recognizes that AlN has a high thermal conductivity compared with other ceramic substrates (col. 2, lns. 6-8; col. 3, lns 36-38).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to have selected AlN for the first, higher thermal-conductivity insulation layer and Al2O3 for the second insulation layer. This is the selection of known materials based on their recognized suitability for the intended use (see MPEP 2144.07). A high thermal-conductivity ceramic where heat release is required and a cheap ceramic elsewhere (see Komorita, col. 11, lns. 31-43).
Re: Claim 21, the combination of Miyakoshi in view of Komorita and Lee discloses the device according to claim 15.
Miyakoshi further discloses wherein the first circuit substrate comprises a first thermally conductive layer (Fig. 6B: metal layer 13a, i.e., first thermally conductive layer) located on a surface of the first insulation layer that faces away from the first line layer (Fig. 6B: metal layer 13a is located on a surface of the first thermally conductive layer 11a, i.e., bottom surface of 11a, that faces away from the first line layer 12a1), and
the second circuit substrate comprises a second thermally conductive layer (Fig. 6B: metal layer 13b, i.e., second thermally conductive layer) located on a surface of the second insulation layer that faces away from the second line layer (Fig. 6B: metal layer 13b is located on a surface of the second thermally conductive layer 11b, i.e., bottom surface of 11b, that faces away from the second line layer 12b1).
Re: Claim 22, the combination of Miyakoshi in view of Komorita and Lee discloses the device according to claim 21.
Miyakoshi further discloses wherein a surface of the first thermally conductive layer that faces away from the first insulation layer (Fig. 6B: first thermally conductive layer 13a that faces away from the first insulation layer 11a, i.e., 13a is located and facing away from a bottom surface of first insulation layer 11a) is coplanar with a surface of the second thermally conductive layer that faces away from the second insulation layer (Fig. 6B: 13a and 13b are coplanar, i.e., on the same plane; second thermally conductive layer 13b is located and facing away from a bottom surface of the second thermally conductive layer 13b.),
However, Miyakoshi does not disclose and the first thermally conductive layer and the second thermally conductive layer are of an integrated structure.
In a similar field of endeavor, Komorita discloses and the first thermally conductive layer and the second thermally conductive layer are of an integrated structure (Figs. 9 and 10 show a metal plate 305, i.e., thermally conductive layer, which is an integrated structure; col. 31, lns. 11-16: … the metal plate 305 are bonded to both surfaces of the complex substrate 310, the metal plate 305 as the backing copper plate is effective since it contributes to heat releasing acceleration and bending prevention).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, to have modified the circuit board disclosed by Miyakoshi to include an integrated thermally conductive layer in order to contribute to heat releasing acceleration and bending prevention (See Komorita, col. 12, lns. 4-10; col. 31, lns. 11-16).
Re: Claim 24, the combination of Miyakoshi in view of Komorita and Lee discloses the device according to claim 21.
Miyakoshi also discloses further comprising a package body (Fig. 6B: device 200),
wherein the package body packages the first circuit substrate and the second circuit substrate (Fig. 6B: device 200 packages 10a and 10b), and
both the surface of the first thermally conductive layer that faces away from the first insulation layer and the surface of the second thermally conductive layer that faces away from the second insulation layer are exposed from the package body (Fig. 6B shows a first and second thermally conductive layer (13a/13b) which are flush with a package body 200, i.e., exposed from the package body; Please see claim interpretation discussed above.).
Re: Claim 25, the combination of Miyakoshi in view of Komorita and Lee discloses the device according to claim 21.
Komorita further discloses wherein a first thermally conductive component is disposed on the surface of the first thermally conductive layer that faces away from the first insulation layer (Figs. 9 and 10 show a thermally conductive component, i.e., a heat sink 309, disposed on the surface of the first thermally conductive layer 305 which faces away from the first insulation layer 302 and 302a), and
a second thermally conductive component is disposed on the surface of the second thermally conductive layer that faces away from the second insulation layer (Figs. 9 and 10 show a thermally conductive component, i.e., a heat sink 309, disposed on the surface of the second thermally conductive layer 305 which faces away from the first insulation layer 302 and 302a).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, to have modified the circuit board disclosed by Miyakoshi to include an integrated thermally conductive layer in order to contribute to heat releasing acceleration and bending prevention (See Komorita, col. 31, lns. 11-16).
Re: Independent Claim 27, Miyakoshi as modified by Komorita and Lee discloses the recited packaging device, for reasons set forth for claim 15.
Miyakoshi discloses that metal layers 13a and 13b can be connected to a cooler (¶¶0041-0042: can be connected to a cooler), but does not specifically disclose at least one heat dissipation apparatus, wherein the at least one heat dissipation apparatus is located on a side of the first insulation layer that faces away from the first line layer or on a side of the second insulation layer that faces away from the second line layer.
Komorita further discloses at least one heat dissipation apparatus (Figs. 9 and 10: heat sink 309), wherein the at least one heat dissipation apparatus is located on a side of the first insulation layer that faces away from the first line layer or on a side of the second insulation layer that faces away from the second line layer (Figs. 9 and 10 show a heat sink 309 located on the bottom side surface of the metal plate 305 which faces away from the first and second line layers.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have included a heat dissipation apparatus on the cooling side of Miyakoshi’s device, as taught by Komorita, because a heat sink improves the heat releasing property of the module (See Komorita, col. 2, lns. 40-46 and col. 11, lns. 31-43 and col. 12, lns. 4-10).
Re: Claim 28, the combination of Miyakoshi in view of Komorita and Lee discloses the module according to claim 27. The limitations of claim 28 are met for reasons set forth in claim 16.
Re: Independent Claim 31, Miyakoshi as modified by Komorita and Lee discloses the recited electronic device, for reasons set forth for claims 15 and 27.
Miyakoshi further discloses
a housing (Fig. 6B shows device 200 which is encapsulated by a sealing resin 70); and
a device located in the housing (Fig. 6B shows devices 10a and 10b within the device 200 encapsulated by a sealing resin 70)
Re: Claim 32, the combination of Miyakoshi in view of Komorita and Lee discloses the electronic device according to claim 31. The limitations of claim 32 are met for reasons set forth in claim 16.
Re: Claim 38, the combination of Miyakoshi in view of Komorita and Lee discloses the device according to claim 16.
Lee further discloses wherein a first end of a second conducting wire is physically attached to the at least one of the plurality of second electronic components that is disposed on the second line layer and the second insulation layer (See Figs. 1-4: wire 170; Fig. 2: upper surface of power semiconductor chip 161, mounted over metal layer 121/201),
a second end of the second conducting wire is physically attached to the another at least one of the plurality of second electronic components that is disposed next to the second line layer on the second insulation layer (See Figs. 1-4: PCB 140 carrying control chip 163), and
the second conducting wire is continuous between the first end and the second end of the second conducting wire (Figs. 1-2; ¶0075: power module package 100 according to the present embodiment may further include wires 170 each electrically connecting between the second lead frame 153 and the second substrate 140, between the second semiconductor chip 163 and the second substrate 140, between the second substrate 140 and the first semiconductor chip 161, and between the first semiconductor chip 161 and the first lead frame 151.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have connected the second electronic component on the second line layer of the combination to the control part next to the second line layer by a continuous second conducting wire, as taught by Lee, in order to transmit control signals between the control device and the power device (see Lee, ¶¶ 0068 and 0101-0102).
Claims 35-37 are rejected under 35 U.S.C. 103 as being unpatentable over MIYAKOSHI (US 20160365307 A1) in view of KOMORITA et al. (US 6232657 B1), LEE et al. (US 20130069210 A1) and HATANO et al. (US 20180145007 A1), hereinafter “Hatano.”
Re: Claim 35, the combination of Miyakoshi in view of Komorita and Lee discloses the electronic device according to claim 31.
However, the combination of Miyakoshi in view of Komorita and Lee does not clearly/specifically disclose wherein a thickness of the first insulation layer is less than a thickness of the first line layer, and a thickness of the second insulation layer is less than a thickness of the second line layer.
In a similar field of endeavor, Hatano discloses wherein a thickness of the first insulation layer is less than a thickness of the first line layer, and a thickness of the second insulation layer is less than a thickness of the second line layer (¶0259: insulating substrate 20 having an SiN-based ceramics substrate 21 of 0.25 mm thickness, with drain and source electrode patters 23U1, 23U2 formed of Cu foil of 1.0 mm thickness, i.e., an insulation layer thinner than the line layer; ¶0009: Thick copper substrates etc. have been developed for further reducing thermal resistances).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have formed the first and second line layers of the combination thicker than the respective insulation layers, as taught by Hatano, in order to reduce the thermal resistance of the circuit substrates (Hatano, ¶0009).
Re: Claim 36, the combination of Miyakoshi in view of Komorita and Lee discloses the electronic device according to claim 31, including the another at least one of the plurality of second electronic components disposed next to the second line layer on the second insulation layer (Lee Fig. 2: control part of printed circuit board 140 carrying control chip 163; ¶¶0081-0082). The combination does not expressly disclose wherein a thickness of the another at least one of the plurality of second electronic components that is disposed next to the second line layer on the second insulation layer is the same as a thickness of the second line layer.
Hatano discloses a thickness of the second line layer (¶0259: electrode patterns 23U1, 23U2 of Cu foil of 1.0 mm thickness) as a design parameter selected to reduce thermal resistance (¶0009). The remaining limitation, wherein a thickness of the another at least one of the plurality of second electronic components that is disposed next to the second line layer on the second insulation layer is the same as a thickness of the second line layer (see rationale below; MPEP 2144.04(IV)(A); MPEP 2144.05(II)), differs from the combination only in relative dimension.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have made the thickness of the control part equal to the thickness of the second line layer. The claim differs from the combination only in the relative dimensions of two elements. Applicant’s specification discloses no function, purpose or criticality for the claimed thickness relationship, and a device having the claimed relative dimensions would not perform differently from the prior art device. The change is therefore an obvious matter of design choice (See MPEP 2144.04(IV)(A); In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984); In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955)). Furthermore, Hatano recognizes line-layer thickness as affecting thermal resistance (¶0009). Selecting that thickness, including relative to adjacent components, would have been routine optimization of a result-effective variable (See MPEP 2144.05(II); In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955))
Re: Claim 37, the combination of Miyakoshi in view of Komorita and Lee discloses the device according to claim 21.
However, the combination of Miyakoshi in view of Komorita and Lee does not clearly/specifically disclose wherein a thickness of the first insulation layer is less than a thickness of the first thermally conductive layer.
In a similar field of endeavor, Hatano discloses wherein a thickness of the first insulation layer is less than a thickness of the first thermally conductive layer (¶¶0259-0260: back electrode pattern 23D formed of Cu foil of 1.0 mm thickness beneath the SiN-based ceramics substrate 21 of 0.25 mm thickness.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have formed the first and second line layers of the combination thicker than the respective insulation layers, as taught by Hatano, in order to reduce the thermal resistance of the circuit substrates (Hatano, ¶0009).
Conclusion
Kanai et al. (US 20220415749 A1), Li et al. (US 20160352247 A1), Higashi et al. (US 20230069967 A1) and Tan et al. (US 20110024086 A1) are cited above as evidence of the ordinary meaning of terms and of conventional constructions in the art. Rhodes (US 20210391311 A1) also discloses a decoupling capacitor 375 positioned directly over the trench between isolated plates of a DBC substrate (see Fig. 3A: 375 and ¶0058).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
OI et al. (US 20170053852 A1): circuit layers thicker than the ceramic substrate (¶¶0039-0041), and multiple power-module substrates on a common heat sink.
OSHIMA (US 5521437 A): a metal-based insulating board for power elements and a separate insulating board for control elements, arranged side by side to avoid wasteful use of the expensive board.
WU et al. (US 20240105566 A1): a temperature-sensing thermistor mounted on a separate DBC signal substrate insulated from the power path.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ADROVEL whose telephone number is (571)272-3048. The examiner can normally be reached 7:30 AM - 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LEONARD CHANG can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WILLIAM ADROVEL/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
