DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of claims 15-16, 20-22, 24-25, 27-28, 31-32 in the reply filed on 02/06/2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 04/11/2024 and 11/08/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Interpretation
Claim 24 states the following: “and both the surface of the first thermally conductive layer that faces away from the first insulation layer and the surface of the second thermally conductive layer that faces away from the second insulation layer are exposed from the package body.” (Emphasis added).
Figures 8 and 10 seem to best exemplify the feature underlined above with Fig. 10 being the figure Examiner is using to interpret the claim. Fig. 10 shows the outer surfaces of the integrated thermally conductive layers (13a/23a) aligned flush with the lower boundary of the package body (5), this flush alignment seems to be consistent with the specification’s intent--to mean that these surfaces are not covered by the encapsulant material of the package body. Instead, they remain exposed to enable direct thermal contact with an external heat dissipation apparatus (e.g., a heat sink).
Applicant’s specification discloses the following:
¶ 0083: “In some embodiments, a surface that is of the first thermally conductive layer 13 and that is away from the first insulation layer 12 is coplanar with a surface that is of the second thermally conductive layer 23 and that is away from the second insulation layer 22, so that flatness of a connection interface when the packaging device 100 is subsequently connected to a heat dissipation apparatus can be improved, and a risk that a gap occurs on the connection interface because the first circuit substrate 1 and the second circuit substrate 2 are disposed separately is reduced, so as to further improve the heat dissipation effect of the packaging device 100.” (Emphasis added).
¶ 0094: “The surface that is of the first thermally conductive layer 13 and that is away from the first insulation layer 12 and the surface that is of the second thermally conductive layer 23 and that is away from the second insulation layer 22 are exposed from the shell 20, so as to facilitate subsequent assembly with the heat dissipation apparatus.” (Emphasis added).
Therefore, the claim is interpreted in the following way: the integrated thermally conductive layers (13a/23a) are aligned flush with the lower boundary of the package body (5).
Claim 25 states the following: “a first thermally conductive component is disposed on the surface of the first thermally conductive layer that faces away from the first insulation layer
a second thermally conductive component is disposed on the surface of the second thermally conductive layer that faces away from the second insulation layer.” (Emphasis added).
Figures 5, 6, 7 and 13 seem to best exemplify the feature underlined above (i.e., first and second thermally conductive components 6 and 7) with Fig. 5 being the figure Examiner is using to interpret the claim. Fig. 5 shows the outer surfaces of the integrated thermally conductive layers (13a/23a) attached to a thermally conductive component 6(7), i.e., a heat sink.
Therefore, the claim is interpreted in the following way: the integrated thermally conductive layers (13a/23a) are aligned flush with the lower boundary of the package body (5) with a heat sink attached thereto.
If the applicant disagrees with the interpretations discussed above then they may amend the claims or provide citations from the specification which specify how the applicant intends the claims to be interpreted. However, no correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-16, 20-22, 24-25, 27-28, and 31-32 are rejected under 35 U.S.C. 103 as being unpatentable over Miyakoshi (US 20160365307 A1), hereinafter “Miyakoshi,” in view of Komorita et al. (US 6232657 B1), hereinafter “Komorita.”
Re: Independent Claim 15, Miyakoshi discloses a device (Fig. 6B: semiconductor device 200), comprising:
a first circuit substrate (Fig. 6B: insulated circuit board 10a), comprising a first line layer and a first insulation layer that are sequentially stacked (Fig. 6B: surface metal layer 12a1, i.e., first line layer, and insulation board 11a, i.e., first insulation layer), wherein at least one first electronic component is disposed on the first circuit substrate (Fig. 6B: transistor 1a, i.e., first electronic component disposed on insulated circuit board 10a); and
a second circuit substrate (Fig. 6B: insulated circuit board 10b), comprising a second line layer and a second insulation layer that are sequentially stacked (Fig. 6B: surface metal layer 12b1, i.e., second line layer, and insulation board 11b, i.e., second insulation layer), wherein at least one second electronic component is disposed on the second circuit substrate (Fig. 6B: diode 1b, i.e., second electronic component disposed on insulated circuit board 10b), and
However, although Miyakoshi discloses that the insulation boards may be made of ceramics such as alumina, aluminum nitride or silicon nitride (See ¶ 0045), Miyakoshi does not specifically disclose wherein a thermal conductivity of the first insulation layer is higher than a thermal conductivity of the second insulation layer.
In a similar field of endeavor, Komorita discloses wherein a thermal conductivity of the first insulation layer is higher than a thermal conductivity of the second insulation layer (Fig. 9: substrate 302 shows an insulation layer Si3N4 and an insulation layer 302a Al2O3; col. 11, lns. 31-36: In the present invention, the two kinds of substrates i.e., the high thermal conductive silicon nitride substrate having a thermal conductivity of 60 w/m·k or more and the cheap substrate for general use having a thermal conductivity of less than 60 w/m·k are selectively used according to the required properties for the circuit board.; col. 29, lns. 13-17: alumina (Al2O3) substrates for Examples 7 to 9, having a thermal conductivity k of 20 w/m·k).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, to have modified the circuit board disclosed by Miyakoshi to include materials having different thermal conductivities, as disclosed by Komorita. One would do so in order to selectively use a material with a high thermal conductivity, such as silicon nitride (Si3N4), for a part of the substrate in which structural strength and heat releasing properties are required. On the other hand, one would also selectively include a cheap material, for cost saving benefits, as a substrate for general use which does not require a high thermal conductivity, that can be easily produced and placed on other parts of the same plane (See Komorita, col. 11, lns. 31-43 and col. 12, lns. 4-10).
Re: Claim 16, the combination of Miyakoshi and Komorita discloses the device according to claim 15.
Miyakoshi further discloses wherein:
the second line layer is electrically connected to the first line layer through a conducting wire (Fig. 6B shows a first line layer 12a1 electrically connected to a second line layer 12b1); or
the first line layer is electrically connected to the second line layer using an electrical connection layer (Fig. 6B shows a first line layer 12a1 electrically connected to a second line layer 12b1), and the first line layer, the second line layer, and the electrical connection layer are of an integrated structure (Fig. 6B shows an integrated structure such as conductive pins 32a and 31b which provide an electrical connection between 12a1 and 12b1).
Re: Claim 20, the combination of Miyakoshi and Komorita discloses the device according to claim 15.
Komorita further discloses wherein a material of the first insulation layer comprises AIN or Si3N4 (Fig. 9: substrate 302 composed of Si3N4), and
a material of the second insulation layer comprises Al203 (Fig. 9: alumina substrate 302a; col. 11, lns. 27-30: aluminum substrate Al2O3).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, to have modified the circuit board disclosed by Miyakoshi to include materials having different thermal conductivities, as disclosed by Komorita. One would do so in order to selectively use a material with a high thermal conductivity, such as silicon nitride (Si3N4), for a part of the substrate in which structural strength and heat releasing properties are required. On the other hand, one would also selectively include a cheap material, for cost saving benefits, as a substrate for general use which does not require a high thermal conductivity, that can be easily produced and placed on other parts of the same plane (See Komorita, col. 11, lns. 31-43 and col. 12, lns. 4-10).
Re: Claim 21, the combination of Miyakoshi and Komorita discloses the device according to claim 15.
Miyakoshi further discloses wherein the first circuit substrate comprises a first thermally conductive layer (Fig. 6B: metal layer 13a, i.e., first thermally conductive layer) located on a surface of the first insulation layer that faces away from the first line layer (Fig. 6B: metal layer 13a is located on a surface of the first thermally conductive layer 11a, i.e., bottom surface of 11a, that faces away from the first line layer 12a1), and
the second circuit substrate comprises a second thermally conductive layer (Fig. 6B: metal layer 13b, i.e., second thermally conductive layer) located on a surface of the second insulation layer that faces away from the second line layer (Fig. 6B: metal layer 13b is located on a surface of the second thermally conductive layer 11b, i.e., bottom surface of 11b, that faces away from the second line layer 12b1).
Re: Claim 22, the combination of Miyakoshi and Komorita discloses the device according to claim 21.
Miyakoshi further discloses wherein a surface of the first thermally conductive layer that faces away from the first insulation layer (Fig. 6B: first thermally conductive layer 13a that faces away from the first insulation layer 11a, i.e., 13a is located and facing away from a bottom surface of first insulation layer 11a) is coplanar with a surface of the second thermally conductive layer that faces away from the second insulation layer (Fig. 6B: 13a and 13b are coplanar, i.e., on the same plane; second thermally conductive layer 13b is located and facing away from a bottom surface of the second thermally conductive layer 13b.),
However, Miyakoshi does not disclose and the first thermally conductive layer and the second thermally conductive layer are of an integrated structure.
In a similar field of endeavor, Komorita discloses and the first thermally conductive layer and the second thermally conductive layer are of an integrated structure (Figs. 9 and 10 show a metal plate 305, i.e., thermally conductive layer, which is an integrated structure; col. 31, lns. 11-16: … the metal plate 305 are bonded to both surfaces of the complex substrate 310, the metal plate 305 as the backing copper plate is effective since it contributes to heat releasing acceleration and bending prevention).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, to have modified the circuit board disclosed by Miyakoshi to include an integrated thermally conductive layer in order to contribute to heat releasing acceleration and bending prevention (See Komorita, col. 31, lns. 11-16).
Re: Claim 24, the combination of Miyakoshi and Komorita discloses the device according to claim 21.
Miyakoshi also discloses further comprising a package body (Fig. 6B: device 200),
wherein the package body packages the first circuit substrate and the second circuit substrate (Fig. 6B: device 200 packages 10a and 10b), and
both the surface of the first thermally conductive layer that faces away from the first insulation layer and the surface of the second thermally conductive layer that faces away from the second insulation layer are exposed from the package body (Fig. 6B shows a first and second thermally conductive layer (13a/13b) which are flush with a package body 200, i.e., exposed from the package body; Please see claim interpretation discussed above.).
Re: Claim 25, the combination of Miyakoshi and Komorita discloses the device according to claim 21.
Komorita further discloses wherein a first thermally conductive component is disposed on the surface of the first thermally conductive layer that faces away from the first insulation layer (Figs. 9 and 10 show a thermally conductive component, i.e., a heat sink 309, disposed on the surface of the first thermally conductive layer 305 which faces away from the first insulation layer 302 and 302a), and
a second thermally conductive component is disposed on the surface of the second thermally conductive layer that faces away from the second insulation layer (Figs. 9 and 10 show a thermally conductive component, i.e., a heat sink 309, disposed on the surface of the second thermally conductive layer 305 which faces away from the first insulation layer 302 and 302a).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, to have modified the circuit board disclosed by Miyakoshi to include an integrated thermally conductive layer in order to contribute to heat releasing acceleration and bending prevention (See Komorita, col. 31, lns. 11-16).
Re: Independent Claim 27, Miyakoshi discloses a module (Fig. 6B: device 200), comprising:
a packaging device (Fig. 6B: device 200), comprising:
a first circuit substrate (Fig. 6B: insulated circuit board 10a), comprising a first line layer and a first insulation layer that are sequentially stacked (Fig. 6B: surface metal layer 12a1, i.e., first line layer, and insulation board 11a, i.e., first insulation layer), wherein at least one first electronic component is disposed on the first circuit substrate (Fig. 6B: transistor 1a, i.e., first electronic component disposed on insulated circuit board 10a); and
a second circuit substrate (Fig. 6B: insulated circuit board 10b), comprising a second line layer and a second insulation layer that are sequentially stacked (Fig. 6B: surface metal layer 12b1, i.e., second line layer, and insulation board 11b, i.e., second insulation layer), wherein at least one second electronic component is disposed on the second circuit substrate (Fig. 6B: diode 1b, i.e., second electronic component disposed on insulated circuit board 10b), and
However, although Miyakoshi discloses that the insulation boards may be made of ceramics such as alumina, aluminum nitride or silicon nitride (See ¶ 0045), Miyakoshi does not specifically disclose wherein a thermal conductivity of the first insulation layer is higher than a thermal conductivity of the second insulation layer; and at least one heat dissipation apparatus, wherein the at least one heat dissipation apparatus is located on a side of the first insulation layer that faces away from the first line layer or on a side of the second insulation layer that faces away from the second line layer.
In a similar field of endeavor, Komorita discloses wherein a thermal conductivity of the first insulation layer is higher than a thermal conductivity of the second insulation layer (Fig. 9: substrate 302 shows an insulation layer Si3N4 and an insulation layer 302a Al2O3; col. 11, lns. 31-36: In the present invention, the two kinds of substrates i.e., the high thermal conductive silicon nitride substrate having a thermal conductivity of 60 w/m·k or more and the cheap substrate for general use having a thermal conductivity of less than 60 w/m·k are selectively used according to the required properties for the circuit board.; col. 29, lns. 13-17: alumina (Al2O3) substrates for Examples 7 to 9, having a thermal conductivity k of 20 w/m·k); and
at least one heat dissipation apparatus (Figs. 9 and 10: heat sink 309), wherein the at least one heat dissipation apparatus is located on a side of the first insulation layer that faces away from the first line layer or on a side of the second insulation layer that faces away from the second line layer (Figs. 9 and 10 show a heat sink 309 located on the bottom side surface of the metal plate 305 which faces away from the first and second line layers.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, to have modified the circuit board disclosed by Miyakoshi to include materials having different thermal conductivities, as disclosed by Komorita. One would do so in order to selectively use a material with a high thermal conductivity, such as silicon nitride (Si3N4), for a part of the substrate in which structural strength and heat releasing properties are required. On the other hand, one would also selectively include a cheap material, for cost saving benefits, as a substrate for general use which does not require a high thermal conductivity, that can be easily produced and placed on other parts of the same plane (See Komorita, col. 11, lns. 31-43 and col. 12, lns. 4-10). Furthermore, the addition of the heat sink plate improves the heat releasing property and prevents cracking of the substrate (See Komorita, col. 2, lns. 40-46).
Re: Claim 28, the combination of Miyakoshi and Komorita discloses the module according to claim 27.
Miyakoshi further discloses wherein:
the second line layer is electrically connected to the first line layer through a conducting wire (Fig. 6B shows a first line layer 12a1 electrically connected to a second line layer 12b1); or
the first line layer is electrically connected to the second line layer using an electrical connection layer (Fig. 6B shows a first line layer 12a1 electrically connected to a second line layer 12b1), and the first line layer, the second line layer, and the electrical connection layer are of an integrated structure (Fig. 6B shows an integrated structure such as conductive pins 32a and 31b which provide an electrical connection between 12a1 and 12b1).
Re: Independent Claim 31, Miyakoshi discloses an electronic device (Fig. 6B: device 200), comprising:
a housing (Fig. 6B shows device 200 which is encapsulated by a sealing resin 70); and
a device located in the housing (Fig. 6B shows devices 10a and 10b within the device 200 encapsulated by a sealing resin 70), wherein the device comprises:
a first circuit substrate (Fig. 6B: insulated circuit board 10a), comprising a first line layer and a first insulation layer that are sequentially stacked (Fig. 6B: surface metal layer 12a1, i.e., first line layer, and insulation board 11a, i.e., first insulation layer), wherein at least one first electronic component is disposed on the first circuit substrate (Fig. 6B: transistor 1a, i.e., first electronic component disposed on insulated circuit board 10a); and
a second circuit substrate (Fig. 6B: insulated circuit board 10b), comprising a second line layer and a second insulation layer that are sequentially stacked (Fig. 6B: surface metal layer 12b1, i.e., second line layer, and insulation board 11b, i.e., second insulation layer), wherein at least one second electronic component is disposed on the second circuit substrate (Fig. 6B: diode 1b, i.e., second electronic component disposed on insulated circuit board 10b), and
However, although Miyakoshi discloses that the insulation boards may be made of ceramics such as alumina, aluminum nitride or silicon nitride (See ¶ 0045), Miyakoshi does not specifically disclose wherein a thermal conductivity of the first insulation layer is higher than a thermal conductivity of the second insulation layer.
In a similar field of endeavor, Komorita discloses wherein a thermal conductivity of the first insulation layer is higher than a thermal conductivity of the second insulation layer (Fig. 9: substrate 302 shows an insulation layer Si3N4 and an insulation layer 302a Al2O3; col. 11, lns. 31-36: In the present invention, the two kinds of substrates i.e., the high thermal conductive silicon nitride substrate having a thermal conductivity of 60 w/m·k or more and the cheap substrate for general use having a thermal conductivity of less than 60 w/m·k are selectively used according to the required properties for the circuit board.; col. 29, lns. 13-17: alumina (Al2O3) substrates for Examples 7 to 9, having a thermal conductivity k of 20 w/m·k).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, to have modified the circuit board disclosed by Miyakoshi to include materials having different thermal conductivities, as disclosed by Komorita. One would do so in order to selectively use a material with a high thermal conductivity, such as silicon nitride (Si3N4), for a part of the substrate in which structural strength and heat releasing properties are required. On the other hand, one would also selectively include a cheap material, for cost saving benefits, as a substrate for general use which does not require a high thermal conductivity, that can be easily produced and placed on other parts of the same plane (See Komorita, col. 11, lns. 31-43 and col. 12, lns. 4-10).
Re: Claim 32, the combination of Miyakoshi and Komorita discloses the electronic device according to claim 31.
Miyakoshi further discloses wherein:
the second line layer is electrically connected to the first line layer through a conducting wire (Fig. 6B shows a first line layer 12a1 electrically connected to a second line layer 12b1); or
the first line layer is electrically connected to the second line layer using an electrical connection layer (Fig. 6B shows a first line layer 12a1 electrically connected to a second line layer 12b1), and the first line layer, the second line layer, and the electrical connection layer are of an integrated structure (Fig. 6B shows an integrated structure such as conductive pins 32a and 31b which provide an electrical connection between 12a1 and 12b1).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Bisi et al. (US 20240421139 A1) – Fig. 2A shows a device 200 which is relevant to the current claims.
Meyer et al. (US 20230094926 A1) – Figs. 2-5 shows a device 100 which is relevant to the current claims.
Oya et al. (US 20160113112 A1) – Figs. 5 and 6 show a device with similar structures as the current claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ADROVEL whose telephone number is (571)272-3048. The examiner can normally be reached 7:30 AM - 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LEONARD CHANG can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM ADROVEL/ Examiner, Art Unit 2898
/Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898