DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (encompassing claims 1-18 and 26-29) in the reply filed on 2/2/26 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 2/4/25. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 11, 15-17, and 26 is/are rejected under 35 U.S.C. 102(a)(1), or alternatively under 35 U.S.C. 102(a)(2), as being anticipated by Li et al. (U.S. 2023/0061693 A1; “Li”).
Regarding claim 1, Li discloses a device comprising:
A substrate (portion under 108A-H, Fig. 1) ([0029], [0002]);
A semiconductor circuit (108A-H, Fig. 1) on a frontside of the substrate ([0029]);
One or more frontside metal layers (M0, M1, Fig. 1) on the semiconductor circuit on the frontside of the substrate ([0029]); and
One or more frontside signal layers (M2, M3, M4, Fig. 1) on the one or more frontside metal layers on the frontside of the substrate, the one or more frontside signal layers being configured carry one or more signals to and/or from the semiconductor circuit and comprising a first frontside signal layer (M4, Fig. 1) ([0029]-[0033]),
Wherein the first frontside signal layer (M4, Fig. 1) comprises one or more top signal metals including a first top signal metal ([0029]), and
Wherein a frontside airgap is formed on a side surface of the first top signal metal (M4, Fig. 1) ([0029], [0049], [0059, [0070]]).
Regarding claim 2, Li discloses the first top signal metal (M4, Fig. 1) has a larger cross section than any metal of the frontside metal layers (M0, M1, Fig. 1).
Regarding claim 11, Li discloses the frontside airgap is a first frontside airgap, wherein the one or more frontside signal layers also includes a second frontside signal layer (M3, Fig. 1) immediately below or immediately above the first frontside signal layer (M4, Fig. 1), and wherein a second frontside airgap is formed on a side surface at least one signal metal of the second frontside signal layer ([0029], [0049], [0059, [0070]).
Regarding claim 15, Li discloses the device is incorporated into an apparatus selected from the group consisting of an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a tablet computer, a computer, a wearable device, a server, and a device in an automotive vehicle ([0090]).
Regarding claim 16, Li discloses a method of fabricating a device, the method comprising:
Providing a substrate (portion under 108A-H, Fig. 1) ([0029], [0002]);
Providing a semiconductor circuit (108A-H, Fig. 1) on a frontside of the substrate ([0029]);
Forming one or more frontside metal layers (M0, M1, Fig. 1) on the semiconductor circuit on the frontside of the substrate ([0029]); and
Forming one or more frontside signal layers (M2, M3, M4, Fig. 1) on the one or more frontside metal layers on the frontside of the substrate, the one or more frontside signal layers being configured carry one or more signals to and/or from the semiconductor circuit and comprising a first frontside signal layer (M4, Fig. 1) ([0029]-[0033]),
Wherein the first frontside signal layer (M4, Fig. 1) comprises one or more top signal metals including a first top signal metal (M4, Fig. 1) ([0029]), and
Wherein a frontside airgap is formed on a side surface of the first top signal metal (M4, Fig. 1) ([0029], [0049], [0059, [0070]]).
Regarding claim 17, Li discloses the first top signal metal (M4, Fig. 1) has a larger cross section than any metal of the frontside metal layers (M0, M1, Fig. 1).
Regarding claim 26, Li discloses the frontside airgap is a first frontside airgap, wherein the one or more frontside signal layers also includes a second frontside signal layer (M3, Fig. 1) immediately below or immediately above the first frontside signal layer (M4, Fig. 1), and wherein a second frontside airgap is formed on a side surface at least one signal metal of the second frontside signal layer ([0029], [0049], [0059, [0070]).
Claim(s) 1, 3, 15-16 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dutta et al. (U.S. 8,643,187 B1; “Dutta”).
Regarding claim 1, Dutta discloses a device comprising:
A substrate (col 10, lines 63-65);
A semiconductor circuit (216, 218, Fig. 2) on a frontside of the substrate (col 10, lines 63-65);
One or more frontside metal layers (210, Fig. 2) on the semiconductor circuit on the frontside of the substrate (col 10, lines 63-65); and
One or more frontside signal layers (207, Fig. 2) on the one or more frontside metal layers on the frontside of the substrate, the one or more frontside signal layers being configured carry one or more signals to and/or from the semiconductor circuit and comprising a first frontside signal layer (207, Fig. 2) (col 10, lines 53-58),
Wherein the first frontside signal layer (207, Fig. 2) comprises one or more top signal metals including a first top signal metal (207, Fig. 2), and
Wherein a frontside airgap (208, Fig. 2) is formed on a side surface of the first top signal metal (207, Fig. 2) (col 10, lines 58-59).
Regarding claim 3, Dutta discloses another frontside airgap (208, Fig. 2) is formed on another side surface of the first top signal metal (207, Fig. 2) (col 10, lines 58-59).
Regarding claim 15, Dutta discloses the device is incorporated into a computer (col 1, lines 39-41).
Regarding claim 16, Dutta discloses a method of fabricating a device, the method comprising:
Providing a substrate (col 10, lines 63-65);
Providing a semiconductor circuit (216, 218, Fig. 2) on a frontside of the substrate (col 10, lines 63-65);
Forming one or more frontside metal layers (210, Fig. 2) on the semiconductor circuit on the frontside of the substrate (col 10, lines 63-65); and
Forming one or more frontside signal layers (207, Fig. 2) on the one or more frontside metal layers on the frontside of the substrate, the one or more frontside signal layers being configured carry one or more signals to and/or from the semiconductor circuit and comprising a first frontside signal layer (207, Fig. 2) (col 10, lines 53-58),
Wherein the first frontside signal layer (207, Fig. 2) comprises one or more top signal metals including a first top signal metal (207, Fig. 2), and
Wherein a frontside airgap (208, Fig. 2) is formed on a side surface of the first top signal metal (207, Fig. 2) (col 10, lines 58-59).
Regarding claim 18, Dutta discloses another frontside airgap (208, Fig. 2) is formed on another side surface of the first top signal metal (207, Fig. 2) (col 10, lines 58-59).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (U.S. 2023/0061693 A1; “Li”) as applied to claim 1 above, and further in view of Domae (U.S. 2002/0005584 A1).
Regarding claims 4-5, Li discloses a frontside airgap is formed on a side surface of the first top signal metal (M4, Fig. 1) ([0029], [0049], [0059, [0070]]) but does not disclose it is an augmented airgap comprising at least one side portion and an upper lateral portion, the at least one side portion being formed on the side surface of the first top signal metal and the upper lateral portion being formed an upper surface of the first top signal metal. However, Domae discloses an airgap is an augmented airgap (113, Fig. 9B-9C) comprising at least one side portion and an upper lateral portion, the at least one side portion being formed on the side surface of a first top signal metal (103, Fig. 9B-9C), the upper lateral portion being formed an upper surface of the first top signal metal and another side surface formed on another side of the first top signal metal ([0163]-[0164]). This has the advantage of reducing capacitance of the first top signal metal within the device to improve device performance. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Li with an augmented airgap, as taught by Domae, so as to reduce capacitance and improve device performance.
Regarding claim 6, Li discloses the one or more top signal metals (M4, Fig. 1) also includes a second top signal metal adjacent to the first top signal metal. Domae discloses the augmented airgap (113, Fig. 9B-9C) is formed on an upper surface of additional top signal metal layers (103, Fig. 9B-9C), wherein the upper lateral portion of the augmented airgap (113, Fig. 9B-9C) is formed, at least partially, on an upper surface of the second top signal metal (103, Fig. 9B-9C).
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (U.S. 2023/0061693 A1; “Li”) as modified by Domae (U.S. 2002/0005584 A1) as applied to claim 1 above, and further in view of Lin et al. (U.S. 2021/0375723 A1; “Lin”) and Schultz (U.S. 2020/0328155 A1).
Regarding claim 8, Li as modified by Domae disclose one or more frontside signal layers (Li: 207, Fig. 2) (Li: col 10, lines 53-58) but does not disclose one or more backside signal layers. However, Lin discloses one or more backside signal layers (metal layers within BM1-4, Fig. 8) comprising a first backside signal layer (124V and 124L within BM3, Fig. 8) being configured to carry one or more signals to or from a semiconductor circuit and comprising a first backside metal (124V and 124L within BM3, Fig. 8) ([0042]). This has the advantage of allowing for increased circuit density. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Li as modified by Domae with one or more backside signal layers, as taught by Lin, so as to increase circuit density.
Yet, Lin as modified by Domae and Lin do not disclose an airgap formed on a side surface of the first backside metal. However, Schultz discloses an airgap formed on a side surface of a metal layer ([0066]). This has the advantage of reducing parasitic capacitance between adjacent metal layers which improves device performance. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Lin as modified by Domae and Lin, with an airgap formed on a side surface of the first backside metal, as taught by Schultz, so as to reduce capacitance and improve device performance.
Regarding claim 9, Lin as modified by Domae, Lin, and Schultz disclose a second backside signal layer (Lin: metallization within BM2, Fig. 8) immediately below or immediately above the first backside signal layer. Schultz discloses an airgap formed on a side surface of a metal layer ([0066]). This has the advantage of reducing parasitic capacitance between adjacent metal layers which improves device performance.
Allowable Subject Matter
Claims 7, 10, 12-14, and 27-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/REEMA PATEL/Primary Examiner, Art Unit 2812 2/20/2026