Attorney’s Docket Number: 0941-5011PUS1
Filing Date: 9/15/2023
Claimed Priority Date: N/A
Applicant(s): Chang et al.
Examiner: Rianna B. Greer
DETAILED ACTION
This Office Action respond to the application filed on 9/15/2023.
Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The application serial no. 18/468,435 filed on 9/15/2023 has been entered. Pending in this Office Action are claims 1-20.
Specification
2. The disclosure is objected to because of the following informalities:
- In Par. [0016], “In other embodiment, the doped region 114 covers more well regions.” should read --In other embodiments, the doped region 114 covers more well regions.--
- In Par. [0020], the specification reads “The deep-well region 102 is formed on a substrate 101.” However, there is lack of antecedent basis for deep-well region 102. The specification should read --A deep-well region 102 is formed on a substrate 101.--
- In Par. [0021], the specification reads “The well region 131 is formed on the deep-well region 102 and has a second conductivity type.” However, the second conductivity type was defined in Par. [0020]. The specification should read --The well region 131 is formed on the deep-well region 102 and has the second conductivity type.--
- In Par. [0024], “In some embodiment, the gate structure 113 further comprises spacers SP1 and SP2.” should read --In some embodiments, the gate structure 113 further comprises spacers SP1 and SP2.--
- In Par. [0027], “In some embodiment, when the first conductivity type is a P-type and the second conductivity type is a N-type, the ESD protection device 100A is served as a PMOS transistor.” should read --In some embodiments, when the first conductivity type is a P-type and the second conductivity type is a N-type, the ESD protection device 100A serves as a PMOS transistor.--
- In Par. [0028], “Assuming the first conductivity type is a P-type and the second conductivity type is a N-type. In this case, the ESD protection device 100A is served as a NMOS transistor.” should read --Assuming the first conductivity type is a P-type and the second conductivity type is a N-typeserves as a NMOS transistor.--
- Both Par. [0027] and Par. [0028] define the first conductivity type as P-type and the second conductivity type as N-type, but Par. [0027] reads that the ESD protection device 100A serves as a PMOS transistor while Par. [0028] reads that the ESD protection device 100A serves as a NMOS transistor. Given the context of Par. [0028], the specification should read that the first conductivity type is a N-type and the second conductivity type is a P-type.
- In Par. [0032], “In one embodiment, the contact structure are electrically connected to the ground. The number of the contact structures is not limited in the present disclosure. In other embodiments, the doped region 114 may be electrically to the more or the fewer contact structures. In some embodiment, the contact structure 311~313 are electrically connected to the contact structure 154 of FIG. 2.” should read --In one embodiment, the contact structures are electrically connected to the ground. The number of the contact structures is not limited in the present disclosure. In other embodiments, the doped region 114 may be electrically connected to s, the contact structures 311~313 are electrically connected to the contact structure 154 of FIG. 2.--
- In Par. [0034], “The size of the doped regions 114_1~114_3 are not limited in the present disclosure.” should read --The sizes of the doped regions 114_1~114_3 are not limited in the present disclosure.--
- In Par. [0036], “Since the ESD currents in the doped regions 114_1~114_3 are low, the current tolerances of doped regions 114_1~114_3 are improve.” should read --Since the ESD currents in the doped regions 114_1~114_3 are low, the current tolerances of doped regions 114_1~114_3 are improved.--
- In Par. [0038], “When an ESD event occurs, there is a large voltage difference between the well region s 134 and 135. Therefore, a vertical electric field is formed to cause a fully depletion effect.” should read --When an ESD event occurs, there is a large voltage difference between the well region
Appropriate corrections are required.
Claim Objections
3. Claim 3 is objected to because of the following informalities:
In Claim 3, “The ESD protection device as claimed in claim 2, wherein the third doped region coverts the fifth well region and the sixth well region.” should read --The ESD protection device as claimed in claim 2, wherein the third doped region covers the fifth well region and the sixth well region.--
Appropriate correction is required.
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1-2 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US9608109) in view of Lin et al. (US2018/0114787).
7. Regarding Claim 1, Tsai (see, e.g., Fig. 2B) shows most aspects of the instant invention including an electrostatic discharge (ESD) protection device comprising:
- a substrate (e.g., substrate 105 or deep n-buried layer (DNBL) 109) having a first conductivity type (see, e.g., Col. 3, Lns. 25-26: the substrate 105 can be n-type; or see, e.g., Col. 4, Lns. 59-60: deep n-buried layer (DNBL))
- a deep-well region (e.g., deep p-buried layer (DPBL) 108) formed on the substrate and having a second conductivity type (e.g., p-type)
- a first well region (e.g., pwell fingers 1203/1204) formed on the deep-well region and having the second conductivity type (e.g., p-type)
- a second well region (e.g., first nwell 125a) formed on the deep-well region and having the first conductivity type (e.g., n-type)
- a third well region (e.g., pwell finger 1201) formed on the deep-well region and having the second conductivity type (e.g., p-type)
- a fourth well region (e.g., second nwell 125b) formed on the deep-well region and having the first conductivity type (e.g., n-type)
- a first doped region (see, e.g., unnumbered p+ regions above pwell fingers 1203/1204) formed in the first well region and having the second conductivity type (e.g., p-type)
- a second doped region (e.g., n+ source 126) formed in the second well region and having the first conductivity type (e.g., n-type)
- a third doped region (e.g., n+ drain 136) formed in the fourth well region and having the first conductivity type (e.g., n-type)
- a gate structure (e.g., gate electrode 130 and gate dielectric layer 131) covering the third well region
8. Furthermore, Tsai (see, e.g., Col. 3, Lns. 9-12) discloses that while the ESD protection device is shown having a symmetrical structure with respect to source and drain, disclosed embodiments also apply to asymmetric drain designs.
9. However, Tsai is silent about a fifth well region formed in the fourth well region and having the second conductivity type (e.g., p-type). Lin, (see, e.g., Figs. 3-4 and Par. [0056], [0064]-[0065]), on the other hand and in the same field of endeavor, teaches that an inserted doped region 106 can be disposed in a drain region 104 to create another ESD path that reduces current concentration in the drain region, thereby strengthening efficiency of ESD protection and reducing damage to ESD protection device.
10. Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a fifth well region formed in the fourth well region and having the second conductivity type in the structure of Tsai, as taught by Lin, to reduce current concentration in the drain region, thereby strengthening efficiency of ESD protection and reducing damage to ESD protection device.
11. Regarding Claim 2, Lin (see, e.g., Fig. 2) shows a sixth well region (e.g., inserted doped region 106) formed in the fourth well region (e.g., first inter doped region 102) and having the second conductivity type (p-type).
12. Regarding Claim 15, Tsai (see, e.g., Fig. 2B) shows most aspects of the instant invention including a transistor structure comprising:
- a bulk doped region (see, e.g., unnumbered p+ regions above pwell fingers 1203/1204) formed in a first well region (e.g., pwell fingers 1203/1204)
- a source doped region (e.g., n+ source 126) formed in a second well region (e.g., first nwell 125a)
- a gate structure (e.g., gate electrode 130 and gate dielectric layer 131) covering a third well region (e.g., pwell finger 1201)
- a first drain doped region (e.g., n+ drain 136) formed in a fourth well region (e.g., second nwell 125b
- wherein the bulk doped region, the first well region, the third well region, the fifth well region, and the sixth well region have the same conductivity type (e.g., p-type)
- and the source doped region, the second well region, the first drain doped region, and the fourth well region have the same conductivity type (e.g., n-type)
13. Furthermore, Tsai (see, e.g., Col. 3, Lns. 9-12) discloses that while the ESD protection device is shown having a symmetrical structure with respect to source and drain, disclosed embodiments also apply to asymmetric drain designs.
14. However, Tsai is silent about a fifth well region and a sixth well region formed in the fourth well region with the corresponding conductivity type (e.g., p-type). Lin, (see, e.g., Figs. 2-4 and Par. [0056], [0064]-[0065]), on the other hand and in the same field of endeavor, teaches that inserted doped regions 106 can be disposed in a drain region 104 to create another ESD path that reduces current concentration in the drain region, thereby strengthening efficiency of ESD protection and reducing damage to ESD protection device.
15. Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a fifth well region and a sixth well region formed in the fourth well region with the corresponding conductivity type (e.g., p-type) in the structure of Tsai, as taught by Lin, to reduce current concentration in the drain region, thereby strengthening efficiency of ESD protection and reducing damage to ESD protection device.
16. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US9608109) in view of Lin et al. (US2018/0114787), and in further view of Leung et al. (Chapter 5 - Silicon-based dielectrics, Interlayer Dielectrics for Semiconductor Technologies, 2003, Academic Press, pg.121-156).
17. Regarding Claim 13, while Tsai (see, e.g., Fig. 2B) shows an interlevel dielectric (ILD) 165 covering a portion of the gate structure 130 and a portion of the third doped region 136, they are silent about the composition of ILD 165. Therefore, Tsai in view of Lin does not explicitly show a resist protective oxide arranged as claimed. Leung (see, e.g., pg. 125-126), on the other hand and in the same field of endeavor teaches that oxides (e.g., silicon dioxide, organosilicate glass, fluorosilicate glass) are materials suitable for implementing the ILD of an ESD protection device.
18. Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have an oxide as the ILD material in the structure of Tsai in view of Lin, because oxides are materials known for suitably implementing an ILD in semiconductor technologies, as suggested by Leung, and selecting a known material based on its suitability for its intended use would have been obvious to the skilled artisan. See Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
19. Furthermore, with regard to the oxide being a “resist protective” oxide, note that a limitation in a claim with respect to a material property in a claimed device does not differentiate the claimed device from prior art device if the prior art device teaches all the structural limitations in the claims. As stated in Best,
Where the claimed and prior art products are identical or substantially identical in structure or composition, a prima facie case of either anticipation or obviousness has been established. See In re Best, 562 F. 2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
20. Note that the applicant has a burden of proof once the examiner establishes a sound basis for believing that the products of the applicant and the prior art are the same. See In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed, Cir. 1990).
21. In the instant case, Tsai in view of Lin and in further view of Leung teaches all structural aspects of the electrostatic discharge (ESD) protection device according to the claimed invention, and the structure of Tsai in view of Lin and in further view of Leung is capable of performing the claimed function, at least because ILD 165 has both an arrangement and a composition similar to the corresponding resist protective oxide, as recited in the body of the claim.
22. Accordingly, Tsai in view of Lin and in further view of Leung also teaches a resist protective oxide covering a portion of the gate structure and a portion of the third doped region.
23. Claims 1-3 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US9608109) in view of Chen et al. (US2025/0072042).
24. Regarding Claim 1, Tsai (see, e.g., Fig. 2B) shows most aspects of the instant invention including an electrostatic discharge (ESD) protection device comprising:
- a substrate (e.g., substrate 105 or deep n-buried layer (DNBL) 109) having a first conductivity type (see, e.g., Col. 3, Lns. 25-26: the substrate 105 can be n-type; or see, e.g., Col. 4, Lns. 59-60: deep n-buried layer (DNBL))
- a deep-well region (e.g., deep p-buried layer (DPBL) 108) formed on the substrate and having a second conductivity type (e.g., p-type)
- a first well region (e.g., pwell fingers 1203/1204) formed on the deep-well region and having the second conductivity type (e.g., p-type)
- a second well region (e.g., first nwell 125a) formed on the deep-well region and having the first conductivity type (e.g., n-type)
- a third well region (e.g., pwell finger 1201) formed on the deep-well region and having the second conductivity type (e.g., p-type)
- a fourth well region (e.g., second nwell 125b) formed on the deep-well region and having the first conductivity type (e.g., n-type)
- a first doped region (see, e.g., unnumbered p+ regions above pwell fingers 1203/1204) formed in the first well region and having the second conductivity type (e.g., p-type)
- a second doped region (e.g., n+ source 126) formed in the second well region and having the first conductivity type (e.g., n-type)
- a third doped region (e.g., n+ drain 136) formed in the fourth well region and having the first conductivity type (e.g., n-type)
- a gate structure (e.g., gate electrode 130 and gate dielectric layer 131) covering the third well region
25. Furthermore, Tsai (see, e.g., Col. 3, Lns. 9-12) discloses that while the ESD protection device is shown having a symmetrical structure with respect to source and drain, disclosed embodiments also apply to asymmetric drain designs.
26. However, Tsai is silent about a fifth well region formed in the fourth well region and having the second conductivity type (e.g., p-type). Chen, (see, e.g., Figs. 1-2 and Par. [0028], on the other hand and in the same field of endeavor, teaches that a drain doped region 42 can be disposed in a drain field region 24 to provide ESD paths that can handle both positive and negative ESD voltages, thereby strengthening efficiency of ESD protection and reducing damage to internal circuits.
27. Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a fifth well region formed in the fourth well region and having the second conductivity type in the structure of Tsai, as taught by Chen, to provide ESD paths that can handle both positive and negative ESD voltages, thereby strengthening efficiency of ESD protection and reducing damage to internal circuits.
28. Regarding Claim 2, Chen (see, e.g., Fig. 3) shows a sixth well region (e.g., inserted elongated portions 42a) formed in the fourth well region (e.g., drain field region 24) and having the second conductivity type (p-type).
29. Regarding Claim 3, Chen (see, e.g., Fig. 3) shows that the third doped region (e.g., drain contact region 34) coverts the fifth well region and the sixth well region (e.g., inserted elongated portions 42a).
30. Regarding Claim 15, Tsai (see, e.g., Fig. 2B) shows most aspects of the instant invention including a transistor structure comprising:
- a bulk doped region (see, e.g., unnumbered p+ regions above pwell fingers 1203/1204) formed in a first well region (e.g., pwell fingers 1203/1204)
- a source doped region (e.g., n+ source 126) formed in a second well region (e.g., first nwell 125a)
- a gate structure (e.g., gate electrode 130 and gate dielectric layer 131) covering a third well region (e.g., pwell finger 1201)
- a first drain doped region (e.g., n+ drain 136) formed in a fourth well region (e.g., second nwell 125b
- wherein the bulk doped region, the first well region, the third well region, the fifth well region, and the sixth well region have the same conductivity type (e.g., p-type)
- and the source doped region, the second well region, the first drain doped region, and the fourth well region have the same conductivity type (e.g., n-type)
24. Furthermore, Tsai (see, e.g., Col. 3, Lns. 9-12) discloses that while the ESD protection device is shown having a symmetrical structure with respect to source and drain, disclosed embodiments also apply to asymmetric drain designs.
25. However, Tsai is silent about a fifth well region and a sixth well region formed in the fourth well region with the corresponding conductivity type (e.g., p-type). Chen, (see, e.g., Figs. 1-2 and Par. [0028], on the other hand and in the same field of endeavor, teaches that elongated portions of drain doped regions 42a can be disposed in a drain field region 24 to provide ESD paths that can handle both positive and negative ESD voltages, thereby strengthening efficiency of ESD protection and reducing damage to internal circuits.
31. Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a fifth well region and a sixth well region formed in the fourth well region with the corresponding conductivity type (e.g., p-type) in the structure of Tsai, as taught by Chen, to provide ESD paths that can handle both positive and negative ESD voltages, thereby strengthening efficiency of ESD protection and reducing damage to internal circuits.
Allowable Subject Matter
32. Claims 4-12, 14, and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
33. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. The additional references cited disclose ESD protection devices having arrangements of features similar to the instant inventions.
34. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Rianna B. Greer whose telephone number is (571) 272-7985. The examiner can normally be reached Monday - Friday, 8 AM - 6 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.B.G./Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814