DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 04/13/2026 have been fully considered but they are not persuasive.
Regarding applicant’s argument on pgs. 13-17 about Mohammed failing to teach “the porous portion comprises a porosified portion” and “the porosified portion comprises a plurality of voids.” Examiner notes that as this is a product claim, the determination of patentability is based on the product itself and the patentability of a product does not depend on its method of production, see MPEP 2113.I. Therefore, “a porosified portion” is interpreted to mean any substrate that has a porous portion, regardless of the method of porosifying.
Mohammed et al. (US20150140807A1, hereinafter Mohammed) discloses
a die substrate comprising a porous portion,
wherein the porous portion comprises a porosified portion (Fig. 1A, par. 106 “the substrate 320 includes a porous silicon region R similar to that of the substrate 20”),
wherein the porosified portion comprises a plurality of voids (Fig. 1A voids 71 are within porous silicon region R and so Mohammed’s porosified portion comprises a plurality of voids).
Regarding applicant’s argument on pg. 18 that Mohammed is not combinable with Howard as they have different approaches to definitions and the formation of porous regions, as this is a product claim, the determination of patentability is based on the product itself and the patentability of a product does not depend on its method of production. Art is analogous to the claimed invention if the reference is from the same field of endeavor or if the reference is reasonably pertinent to the problem faced by the inventor (even if it is not in the same field of endeavor as the claimed invention) (see MPEP 2141.01(a)). In this case, the references are analogous arts because they both involve devices containing vias that extend through a porous semiconductor substrate.
Therefore, Mohammed still discloses the claim, see below for full claims mapping.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mohammed et al. (US20150140807A1).
Regarding claim 1, Mohammed discloses an integrated device comprising:
a die substrate comprising a porous portion (Fig. 1A, par. 106 “the substrate 320 includes a porous silicon region R similar to that of the substrate 20”),
wherein the porous portion comprises a porosified portion (Fig. 1A, par. 106 “the substrate 320 includes a porous silicon region R similar to that of the substrate 20.” Examiner notes that as this is a product claim, “a porosified portion” is interpreted to means any substrate that has a porous portion, regardless of the method of porosifying),
wherein the porosified portion comprises a plurality of voids (Fig. 1A voids 71 are within porous silicon region R);
a plurality of through substrate vias extending through the porosified portion of the die substrate (Fig. 1A first and second TSVs 30a/30b), wherein the side surfaces of the plurality of through substrate vias directly touch the porosified portion (As first and second TSVs 30a/30b are formed within the porous section, their side surfaces also directly tough the porous region R);
a die interconnection portion coupled to the die substrate (See below annotated fig. 1A, the portion of substrate 20 extending approximately the length H1 is a die interconnection portion that is coupled to the die substrate),
wherein the die interconnection portion is a back end of line portion that includes:
one or more dielectric layers (Fig. 1A dielectric layer 75); and
a plurality of die interconnects comprising a plurality of trace die interconnects, wherein the plurality of trace die interconnects are located at least partially in the one or more dielectric layers of the back end of line portion (Fig. 1A plurality of conductive vias 50 are located on the bottom surface of unit 10 and the vias 50 extend through dielectric layer 75);
a passivation layer coupled to the one or more dielectric layers (Fig. 1A dielectric layer 25 par. 52 teaches that dielectric layer 25 “can be referred to as a ‘passivation layer’ of the microelectronic unit 10” and is electrically coupled to dielectric layer 75);
a plurality of pad interconnects coupled to the plurality of die interconnects (Fig. 1A plurality of conductive pads 24); and
a metallization portion coupled to a back side of the die substrate (Fig. 1A portion of substrate with conductive contacts 60 coupled to back side of first/second TSVs 30a/30b), wherein the metallization portion comprises:
one or more back side dielectric layers (Par. 52 teaches that “[t]he substrate 20 can further include another dielectric layer (not shown) overlying the rear surface 21”); and
a plurality of metallization interconnects coupled to and directly touching the plurality of through substrate vias (Fig. 1A conductive contacts 60 coupled to first/second TSVs 30a/30b).
Regarding claim 2, Mohammed discloses the integrated device of wherein the die substrate includes silicon (Fig. 1A silicon substrate 20 includes silicon),
wherein a portion of the silicon is porosified silicon that includes the plurality of voids (Fig. 1A voids 71 are within porous silicon region R, see above response to arguments regarding porosified),
wherein the plurality of through substrate vias comprise a first through substrate via that includes a side surface (Fig. 1A rightmost TSV 30 has a right side surface),
wherein a first portion of the side surface of the first through substrate via directly touches the porosified silicon (Fig. 1A the middle portion of the right side surface of rightmost TSV directly touches porosified region R and is directly adjacent to voids 71), and
wherein a second portion of the side surface of the first through substrate via directly touches the one or more dielectric layers of the back end of line portion (Fig. 1A the bottom portion of the right side surface of rightmost TSV directly touches dielectric layer 75).
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Regarding claim 3, Mohammed discloses the integrated device of claim 2,
wherein the die substrate includes an unporosified portion (Par. 106 “the substrate 320 includes a porous silicon region R similar to that of the substrate 20” and while it isn’t explicitly shown, this teaches that not all of the substrate is to be made porous), and
wherein the porous portion of the die substrate includes a lower density than the unporosified portion of the die substrate (While Mohammed doesn’t explicitly teach about the relative densities of the regions, par. 80 teaches that “the region R of porous silicon can be formed by electrochemical dissolution of the silicon substrate 20 in a solution based on hydrofluoric acid.” Therefore, as the porous section is made porous by electrochemical dissolution, there would necessarily be less matter in the porous sections and so the density would be lower).
Regarding claim 4, Mohammed discloses the integrated device of claim 1,
wherein the porosified portion includes a coefficient of thermal expansion (CTE) in a range of about 5-8 parts per million per Celsius degree (ppm / C) (Par. 53 “the substrate 20 can have an effective CTE less than 8*10-6/° C,” see MPEP 2144.05(I)).
Regarding claim 5, Mohammed discloses the integrated device of claim 1, wherein the porosified portion comprises:
a first porosified portion comprising a first density (Fig. 2D first region A has a first density. Examiner notes this is a plan view to better illustrate the regions); and
a second porous porosified comprising a second density (Fig. 2D second region B has a second density. Examiner notes this is a plan view to better illustrate the regions).
Regarding claim 6, Mohammed discloses the integrated device of claim 5,
wherein the first porosified portion comprises a first coefficient of thermal expansion (CTE) (Fig. 2D first region A has a first CTE. Examiner notes this is a plan view to better illustrate the regions), and
wherein the second porosified portion comprises a second coefficient of thermal expansion (CTE) (Fig. 2D second region B has a second CTE. Examiner notes this is a plan view to better illustrate the regions).
Regarding claim 14, Mohammed discloses the integrated device of claim 1, further comprising
an active region (Fig. 1A active semiconductor region 23),
wherein the plurality of through substrate vias are configured to be electrically coupled to the active region through the die interconnection portion (Par. 50 “the active semiconductor devices in the active semiconductor region 23 typically are conductively connected to the conductive pads 24”).
Regarding claim 15, Mohammed discloses the integrated device of claim 14,
wherein the active region includes any one or more of (i) a plurality of logic cells, ii) a plurality of transistors, and/or (iii a plurality of filters (Par. 48 “a plurality of active semiconductor devices (e.g., transistors, diodes, etc.) can be disposed in an active semiconductor region 23”).
Regarding claim 16, Mohammed discloses the integrated device of claim 1,
wherein the integrated device is part of a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle (Par. 8 discusses the current inventions place within chip design and therefore use in “devices commonly referred to as “smart phones” [which] integrate the functions of a cellular telephone with powerful data processors, memory and ancillary devices such as global positioning system receivers, electronic cameras, and local area network connections along with high-resolution displays and associated image processing chips”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Mohammed (US20150140807A1)
Regarding claim 9, Mohammed teaches the integrated device of claim 1,
wherein the plurality of metallization interconnects include a plurality of trace metallization interconnects and a plurality of via metallization interconnects (While Mohammed only explicitly teaches a plurality of via metallization interconnects with conductive contacts 60, the primary function of conductive contacts is to facilitate electrical interconnections. A duplication of the conductive contacts to form a plurality of trace metallization interconnects would not provide any new or unexpected results as the primary function of facilitating electrical interconnections is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore duplicate conductive contacts 60 to form a plurality of trace metallization interconnects, see MPEP 2144.04(VI)(B)).
Regarding claim 10, Mohammed teaches the integrated device of claim 1,
wherein the metallization portion comprises two or more metal layers (While Mohammed only explicitly teaches a single metal layer in conductive contacts 60, the primary function of conductive contacts is to facilitate electrical interconnections. A duplication of the conductive contacts to form two or more metal layers would not provide any new or unexpected results as the primary function of facilitating electrical interconnections is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore duplicate conductive contacts 60 to form two or more metal layers, see MPEP 2144.04(VI)(B)).
Regarding claim 11, Mohammed teaches the integrated device of claim 10,
wherein the plurality of metallization interconnects include a plurality of redistribution interconnects (Fig. 1A conductive contacts 60 constitute a plurality of redistribution interconnects. A duplication of a conductive contacts 60 to form redistribution interconnects would not provide any new or unexpected results as the primary function of providing a conducting path is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore duplicate conductive contacts 60 to form redistribution interconnects, see MPEP 2144.04(VI)(B))).
Regarding claim 12, Mohammed teaches the integrated device of claim 1, further comprising;
an active region (Fig. 1A active semiconductor region 23); and
one or more cavities in the die substrate (Fig. 2I apertures 14 in substrate 20),
wherein the one or more cavities open through the back side of the die substrate (Fig. 2I apertures 14 in substrate 20 open through the back side of substrate 20),
wherein the one or more cavities extend through only part of the die substrate (Fig. 2I apertures 14 in substrate 20 don’t extend through the whole substrate 20), and
wherein the one or more cavities vertically overlaps with the active region (While Mohammed does not explicitly disclose aperture 14 vertically overlapping active region 23, the primary function of aperture 14 is to contain conductive vias. A rearrangement of aperture 14 to vertically overlap with the active region would not provide any new or unexpected results as the primary function of containing conductive vias is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore rearrange aperture 14 to vertically overlap with the active region, see MPEP 2144.04(VI)(B)).
Regarding claim 13, Mohammed teaches the integrated device of claim 1,
wherein a total surface area of all of the plurality of through substrate vias is at least 2 percent of a total surface area of the die substrate (While Mohammed does not explicitly disclose a total surface area of all of the plurality of through substrate vias is at least 2 percent of a total surface area of the die substrate, as the only difference between Mohammed and the claimed invention is a relative recitation of dimensions and nothing within the disclosure indicates that a device having the claimed dimensions would perform differently than Mohammed, such a recitation of relative dimensions is not enough to be patentably distinct, see MPEP 2144.04(IV)(A)).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Mohammed (US20150140807A1) in view of Howard (US20210111101A1).
Regarding claim 7, Mohammed teaches the integrated device of claim 6,
wherein the die substrate includes an unporosified portion comprising a third coefficient of thermal expansion (CTE) (Par. 106 “the substrate 320 includes a porous silicon region R similar to that of the substrate 20” and while it isn’t explicitly shown, this teaches that not all of the substrate is to be made porous).
Mohammed does not appear to teach
a third CTE that is different from the first coefficient of thermal expansion (CTE) and the second coefficient of thermal expansion (CTE).
Howard teaches in par. 48 that “porous silicon region 222 has a coefficient of thermal expansion (CTE) that more closely matches a CTE of TSV 232, compared to a CTE of bulk silicon substrate 220.” Therefore, as porosity treatment affects CTE, the third unporosified region would have a different CTE than the porosified portions and as first and second regions A/B have different densities, they too would have a different CTE from each other.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Mohammed (US20150140807A1) in view of Faneli et al. (US10134837B1, hereinafter Faneli).
Regarding claim 8, Mohammed teaches the integrated device of claim 1.
Mohammed does not appear to teach
wherein the porosified portion comprises a porosity in a range of about 30-70 percent, wherein the porosity of the porosified portion represents the volume of voids in the porosified portion over the total volume of the porosified portion.
Faneli teaches
wherein the porosified portion comprises a porosity in a range of about 30-70 percent, wherein the porosity of the porosified portion represents the volume of voids in the porosified portion over the total volume of the porosified portion (Col. 8 “the porous silicon layer 360 may be 20%-60% porous.” In col. 9 Faneli further teaches that “[a]s the porosity increases, so does the variation in sizes of pores” and so it appears that Faneli’s porosity represents the volume of voids in the porosified portion over the total volume of the porosified portion due to the fact that the larger porosity means larger variation, and therefore larger pores).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mohammed with the teachings of Faneli because, as Mohammed is silent as to the specific level of porosification, this would motivate a person of ordinary skill to seek out references such as Faneli who explicitly discloses the degree of porosification.
Claims 17-19, 21-30, and 32-33 are rejected under 35 U.S.C. 103 as being unpatentable over Mohammed (US20150140807A1) in view of Kim et al. (US20150108643A1, hereinafter Kim).
Regarding claim 17, Mohammed teaches a first integrated device, wherein the first integrated device comprises:
a die substrate comprising a porous portion (Fig. 1A, par. 106 “the substrate 320 includes a porous silicon region R similar to that of the substrate 20”),
wherein the porous portion comprises a porosified portion (Fig. 1A, par. 106 “the substrate 320 includes a porous silicon region R similar to that of the substrate 20.” Examiner notes that as this is a product claim, “a porosified portion” is interpreted to means any substrate that has a porous portion, regardless of the method of porosifying), and
wherein the porosified portion comprises a plurality of voids (Fig. 1A voids 71 are within porous silicon region R);
a plurality of through substrate vias extending through the porosified portion of the die substrate (Fig. 1A first and second TSVs 30a/30b), wherein the side surfaces of the plurality of through substrate vias directly touch the porosified portion (As first and second TSVs 30a/30b are formed within the porous section, their side surfaces also directly tough the porous region R); and
a die interconnection portion coupled to the die substrate (See above annotated fig. 1A, the portion of substrate 20 extending approximately the length H1 is a die interconnection portion that is coupled to the die substrate),
wherein the die interconnection portion is a back end of line portion that includes:
one or more dielectric layers (Fig. 1A dielectric layer 75); and
a plurality of die interconnects comprising a plurality of trace die interconnects, wherein the plurality of trace die interconnects are located at least partially in the one or more dielectric layers of the back end of line portion (Fig. 1A plurality of conductive vias 50 are located on the bottom surface of unit 10 and the vias 50 extend through dielectric layer 75);
a passivation layer coupled to the one or more dielectric layers (Fig. 1A dielectric layer 25 par. 52 teaches that dielectric layer 25 “can be referred to as a ‘passivation layer’ of the microelectronic unit 10” and is electrically coupled to dielectric layer 75);
a plurality of pad interconnects coupled to the plurality of die interconnects (Fig. 1A plurality of conductive pads 24); and
a metallization portion coupled to a back side of the die substrate (Fig. 1A portion of substrate with conductive contacts 60 coupled to back side of first/second TSVs 30a/30b), wherein the metallization portion comprises:
one or more back side dielectric layers (Par. 52 teaches that “[t]he substrate 20 can further include another dielectric layer (not shown) overlying the rear surface 21”); and
a plurality of metallization interconnects coupled to and directly touching the plurality of through substrate vias (Fig. 1A conductive contacts 60 coupled to first/second TSVs 30a/30b).
Mohammed does not appear to teach
a package comprising:
an interposer;
a first integrated device coupled to the interposer through at least a plurality of solder interconnects.
Kim teaches
a package comprising:
an interposer (Par. 32 “the extended substrate 222 may comprise, for example, an interposer”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mohammed with the teachings of Kim because Mohammed teaches in par. 58 that the “plurality of conductive contacts 60 exposed at the rear surface 22 [are] for interconnection with an external element” such as an interposer. Additionally, in par. 62 Mohammed teaches for bonding that “conductive masses can include…solder-filled paste.”
Regarding claim 18, the combination of Mohammed and Kim teaches the package of claim 17,
wherein the die substrate includes silicon (Mohammed fig. 1A silicon substrate 20 includes silicon),
wherein a portion of the silicon is porosified silicon that includes the plurality of voids (Mohammed fig. 1A voids 71 are within porous silicon region R, see above response to arguments regarding porosified),
wherein the plurality of through substrate vias comprise a first through substrate via that includes a side surface (Mohammed fig. 1A rightmost TSV 30 has a right side surface),
wherein a first portion of the side surface of the first through substrate via directly touches the porosified silicon (Mohammed fig. 1A the middle portion of the right side surface of rightmost TSV directly touches porosified region R and is directly adjacent to voids 71), and
wherein a second portion of the side surface of the first through substrate via directly touches the one or more dielectric layers of the back end of line portion (Mohammed fig. 1A the bottom portion of the right side surface of rightmost TSV directly touches dielectric layer 75).
Regarding claim 19, the combination of Mohammed and Kim teaches the package of claim 18,
wherein the die substrate includes an unporosified portion (Mohammed par. 106 “the substrate 320 includes a porous silicon region R similar to that of the substrate 20” and while it isn’t explicitly shown, this teaches that not all of the substrate is to be made porous), and
wherein the porosified portion of the die substrate includes a lower density than the unporosified portion of the die substrate (While Mohammed doesn’t explicitly teach about the relative densities of the regions, par. 80 teaches that “the region R of porous silicon can be formed by electrochemical dissolution of the silicon substrate 20 in a solution based on hydrofluoric acid.” Therefore, as the porous section is made porous by electrochemical dissolution, there would necessarily be less matter in the porous sections and so the density would be lower).
Regarding claim 21, the combination of Mohammed and Kim teaches the package of claim 17,
wherein the plurality of metallization interconnects include a plurality of trace metallization interconnects and a plurality of via metallization interconnects (While Mohammed only explicitly teaches a plurality of via metallization interconnects with conductive contacts 60, the primary function of conductive contacts is to facilitate electrical interconnections. A duplication of the conductive contacts to form a plurality of trace metallization interconnects would not provide any new or unexpected results as the primary function of facilitating electrical interconnections is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore duplicate conductive contacts 60 to form a plurality of trace metallization interconnects, see MPEP 2144.04(VI)(B)).
Regarding claim 22, the combination of Mohammed and Kim teaches the package of claim 21,
wherein the metallization portion comprises two or more metal layers (While Mohammed only explicitly teaches a single metal layer in conductive contacts 60, the primary function of conductive contacts is to facilitate electrical interconnections. A duplication of the conductive contacts to form two or more metal layers would not provide any new or unexpected results as the primary function of facilitating electrical interconnections is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore duplicate conductive contacts 60 to form two or more metal layers, see MPEP 2144.04(VI)(B)).
Regarding claim 23, the combination of Mohammed and Kim teaches the package of claim 21, further comprising
a second integrated device coupled to the metallization portion of the first integrated device through a second plurality of solder interconnects (While the combination of Mohammed and Kim does not explicitly disclose a second integrated device coupled to the metallization portion of the first integrated device through a second plurality of solder interconnects, the primary function of the first integrated device as taught above in claim 17 is to provide interconnections for semiconductor devices. A duplication of the first integrated device as taught above in claim 17 to form a second integrated device coupled to the metallization portion of the first integrated device through a second plurality of solder interconnects would not provide any new or unexpected results as the primary function of providing interconnections for semiconductor devices is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore duplicate the first integrated device as taught above in claim 17 to form a second integrated device coupled to the metallization portion of the first integrated device through a second plurality of solder interconnects, see MPEP 2144.04(VI)(B)).
Regarding claim 24, the combination of Mohammed and Kim teaches the package of claim 17, further comprising
a second integrated device coupled to the interposer through a second plurality of solder interconnects (While the combination of Mohammed and Kim does not explicitly disclose a second integrated device coupled to the metallization portion of the first integrated device through a second plurality of solder interconnects, the primary function of the first integrated device as taught above in claim 17 is to provide interconnections for semiconductor devices. A duplication of the first integrated device as taught above in claim 17 to form a second integrated device coupled to the metallization portion of the first integrated device through a second plurality of solder interconnects would not provide any new or unexpected results as the primary function of providing interconnections for semiconductor devices is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore duplicate the first integrated device as taught above in claim 17 to form a second integrated device coupled to the metallization portion of the first integrated device through a second plurality of solder interconnects, see MPEP 2144.04(VI)(B)).
Regarding claim 25, the combination of Mohammed and Kim teaches the package of claim 17, further comprising
at least one cavity in the die substrate (Mohammed fig. 1A voids 71 in substrate 20).
Regarding claim 26, the combination of Mohammed and Kim teaches the package of claim 17,
wherein the interposer includes a silicon substrate and a plurality of interposer interconnects (Kim teaches the use of their extended substrate 916 as an interposer and further teaches in par. 60 that “[t]he extended substrate 520 may comprise an interposer, for example, and a plurality of the bottom bumps 518 formed on the bottom of the extended substrate 520 may comprise one or more of solder balls or conductive pillars.” As Kim teaches the interposer, they also teach the specific materials/conductive pillars and as it is called a substrate, examiner notes that silicon is a common substrate material).
Regarding claim 27, the combination of Mohammed and Kim teaches the package of claim 26.
The combination of Mohammed and Kim as applied to claim 26 does not appear to teach
a substrate coupled to the interposer through a second plurality of solder interconnects.
Kim further teaches
a substrate coupled to the interposer through a second plurality of solder interconnects (Fig. 9E extended substrate 916 is connected to substrate 902 which has further solder bumps 918 disposed below it).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mohammed with the teachings of Kim because Mohammed teaches in par. 58 that the “plurality of conductive contacts 60 exposed at the rear surface 22 [are] for interconnection with an external element” such as an interposer and an additional substrate as taught by Kim.
Regarding claim 28, Mohammed teaches a first integrated device comprises:
a die substrate comprising a porous portion (Fig. 1A, par. 106 “the substrate 320 includes a porous silicon region R similar to that of the substrate 20”),
wherein the porous portion comprises a porosified portion (Fig. 1A, par. 106 “the substrate 320 includes a porous silicon region R similar to that of the substrate 20.” Examiner notes that as this is a product claim, “a porosified portion” is interpreted to means any substrate that has a porous portion, regardless of the method of porosifying), and
wherein the porosified portion comprises a plurality of voids (Fig. 1A voids 71 are within porous silicon region R);
a plurality of through substrate vias extending through the porosified portion of the die substrate (Fig. 1A first and second TSVs 30a/30b), wherein the side surfaces of the plurality of through substrate vias directly touch the porosified portion (As first and second TSVs 30a/30b are formed within the porous section, their side surfaces also directly tough the porous region R); and
a die interconnection portion coupled to the die substrate (See above annotated fig. 1A, the portion of substrate 20 extending approximately the length H1 is a die interconnection portion that is coupled to the die substrate),
wherein the die interconnection portion is a back end of line portion that includes:
one or more dielectric layers (Fig. 1A dielectric layer 75); and
a plurality of die interconnects comprising a plurality of trace die interconnects, wherein the plurality of trace die interconnects are located at least partially in the one or more dielectric layers of the back end of line portion (Fig. 1A plurality of conductive vias 50 are located on the bottom surface of unit 10 and the vias 50 extend through dielectric layer 75);
a passivation layer coupled to the one or more dielectric layers (Fig. 1A dielectric layer 25 par. 52 teaches that dielectric layer 25 “can be referred to as a ‘passivation layer’ of the microelectronic unit 10” and is electrically coupled to dielectric layer 75);
a plurality of pad interconnects coupled to the plurality of die interconnects (Fig. 1 plurality of conductive pads 24); and
a metallization portion coupled to a back side of the die substrate (Fig. 1A portion of substrate with conductive contacts 60 coupled to back side of first/second TSVs 30a/30b), wherein the metallization portion comprises:
one or more back side dielectric layers (Par. 52 teaches that “[t]he substrate 20 can further include another dielectric layer (not shown) overlying the rear surface 21”); and
a plurality of metallization interconnects coupled to and directly touching the plurality of through substrate vias (Fig. 1A conductive contacts 60 coupled to first/second TSVs 30a/30b).
Mohammed does not appear to teach
a package comprising:
a substrate; and
a first integrated device coupled to the substrate through at least a plurality of solder interconnects
Kim teaches
a package comprising:
a substrate (Par. 32 “the extended substrate 222 may comprise, for example, an interposer”); and
a first integrated device coupled to the substrate through at least a plurality of solder interconnects.
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mohammed with the teachings of Kim because Mohammed teaches in par. 58 that the “plurality of conductive contacts 60 exposed at the rear surface 22 [are] for interconnection with an external element” such as an interposer. Additionally, in par. 62 Mohammed teaches for bonding that “conductive masses can include…solder-filled paste.”
Regarding claim 29, the combination of Mohammed and Kim teaches the package of claim 28
wherein the die substrate includes silicon (Mohammed fig. 1A silicon substrate 20 includes silicon),
wherein a portion of the silicon is porosified silicon that includes the plurality of voids (Mohammed fig. 1A voids 71 are within porous silicon region R, see above response to arguments regarding porosified),
wherein the plurality of through substrate vias comprise a first through substrate via that includes a side surface (Mohammed fig. 1A rightmost TSV 30 has a right side surface),
wherein a first portion of the side surface of the first through substrate via directly touches the porosified silicon (Mohammed fig. 1A the middle portion of the right side surface of rightmost TSV directly touches porosified region R and is directly adjacent to voids 71), and
wherein a second portion of the side surface of the first through substrate via directly touches the one or more dielectric layers of the back end of line portion (Mohammed fig. 1A the bottom portion of the right side surface of rightmost TSV directly touches dielectric layer 75).
Regarding claim 30, the combination of Mohammed and Kim teaches the package of claim 29,
wherein the die substrate includes an unporosified portion (Mohammed par. 106 “the substrate 320 includes a porous silicon region R similar to that of the substrate 20” and while it isn’t explicitly shown, this teaches that not all of the substrate is to be made porous), and
wherein the porosified portion of the die substrate includes a lower density than the unporosified portion of the die substrate (While Mohammed doesn’t explicitly teach about the relative densities of the regions, par. 80 teaches that “the region R of porous silicon can be formed by electrochemical dissolution of the silicon substrate 20 in a solution based on hydrofluoric acid.” Therefore, as the porous section is made porous by electrochemical dissolution, there would necessarily be less matter in the porous sections and so the density would be lower).
Regarding claim 32, the combination of Mohammed and Kim teaches the package of claim 28, further comprising
a second integrated device coupled to the first integrated device through a second plurality of solder interconnects (While the combination of Mohammed and Kim does not explicitly disclose a second integrated device coupled to the first integrated device through a second plurality of solder interconnects, the primary function of the first integrated device as taught above in claim 28 is to provide interconnections for semiconductor devices. A duplication of the first integrated device as taught above in claim 28 to form a second integrated device coupled to the first integrated device through a second plurality of solder interconnects would not provide any new or unexpected results as the primary function of providing interconnections for semiconductor devices is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore duplicate the first integrated device as taught above in claim 28 to form a second integrated device coupled to the first integrated device through a second plurality of solder interconnects, see MPEP 2144.04(VI)(B)).
Regarding claim 33, the combination of Mohammed and Kim teaches the package of claim 28, further comprising
a second integrated device coupled to the substrate through a second plurality of solder interconnects a second integrated device coupled to the first integrated device through a second plurality of solder interconnects (While the combination of Mohammed and Kim does not explicitly disclose a second integrated device coupled to the first integrated device through a second plurality of solder interconnects, the primary function of the first integrated device as taught above in claim 28 is to provide interconnections for semiconductor devices. A duplication of the first integrated device as taught above in claim 28 to form a second integrated device coupled to the first integrated device through a second plurality of solder interconnects would not provide any new or unexpected results as the primary function of providing interconnections for semiconductor devices is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore duplicate the first integrated device as taught above in claim 28 to form a second integrated device coupled to the first integrated device through a second plurality of solder interconnects, see MPEP 2144.04(VI)(B)).
Claims 20 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Mohammed in view of Kim as applied to claim 17 and 28 above, and further in view of Howard (US20210111101A1).
Regarding claim 20, the combination of Mohammed and Kim teaches the package of claim 17,
wherein the porous porosified portion comprises:
a first porosified portion comprising a first coefficient of thermal expansion (CTE) (Mohammed fig. 2D first region A has a first CTE), and
a second porosified portion comprising a second coefficient of thermal expansion (CTE) (Mohammed fig. 2D second region B has a second CTE),
wherein the die substrate includes an unporosified portion comprising a third coefficient of thermal expansion (CTE) (Mohammed par. 106 “the substrate 320 includes a porous silicon region R similar to that of the substrate 20” and while it isn’t explicitly shown, this teaches that not all of the substrate is to be made porous and this unporosified portion has a third CTE).
The combination of Mohammed and Kim does not appear to teach
a third coefficient of thermal expansion (CTE) that is different from the first coefficient of thermal expansion (CTE) and the second coefficient of thermal expansion (CTE).
Howard teaches in par. 48 that “porous silicon region 222 has a coefficient of thermal expansion (CTE) that more closely matches a CTE of TSV 232, compared to a CTE of bulk silicon substrate 220.” Therefore, as porosity treatment affects CTE, the third unporosified region would have a different CTE than the porosified portions and as first and second regions A/B have different densities, they too would have a different CTE from each other.
Regarding claim 31, the combination of Mohammed and Kim teaches the package of claim 28,
wherein the porosified portion comprises:
a first porosified portion comprising a first coefficient of thermal expansion (CTE) (Mohammed fig. 2D first region A has a first CTE), and
a second porosified portion comprising a second coefficient of thermal expansion (CTE) (Mohammed fig. 2D second region B has a second CTE),
wherein the die substrate includes an unporosified portion comprising a third coefficient of thermal expansion (CTE) (Mohammed par. 106 “the substrate 320 includes a porous silicon region R similar to that of the substrate 20” and while it isn’t explicitly shown, this teaches that not all of the substrate is to be made porous and this unporosified portion has a third CTE).
The combination of Mohammed and Kim does not appear to teach
a third coefficient of thermal expansion (CTE) that is different from the first coefficient of thermal expansion (CTE) and the second coefficient of thermal expansion (CTE).
Howard teaches in par. 48 that “porous silicon region 222 has a coefficient of thermal expansion (CTE) that more closely matches a CTE of TSV 232, compared to a CTE of bulk silicon substrate 220.” Therefore, as porosity treatment affects CTE, the third unporosified region would have a different CTE than the porosified portions and as first and second regions A/B have different densities, they too would have a different CTE from each other.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COLE LEON LINDSEY/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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