Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 15 recites the limitation “wherein the active region includes a plurality of logic cells, a plurality of transistors, and/or a plurality of filters,” with emphasis examiner’s. The phrase “and/or” renders the claim indefinite as it is not immediately clear to a person of ordinary skill in the art which elements are required by the claim and which are optional. It is unclear if the first two are required, with the last being optional, or if only one of the three claimed elements need to be present. For the purposes of compact prosecution, examiner will interpret the claim as “wherein the active region includes a plurality of logic cells, a plurality of transistors, or a plurality of filters” such that only one of the claimed elements needs to be present.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 9, 12, and 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mohammed et al. (US20150140807A1, hereinafter Mohammed).
Regarding claim 1, Mohammed discloses an integrated device comprising:
a die substrate comprising a porous portion (Fig. 1A, par. 106 “the substrate 320 includes a porous silicon region R”);
a plurality of through substrate vias extending through the porous portion of the die substrate (Fig. 3A first and second TSVs 330a/330b); and
a die interconnection portion coupled to the die substrate (See below annotated fig. 1A, the portion of substrate 20 extending approximately the length H1 is a die interconnection portion that is coupled to the die substrate).
Regarding claim 2, Mohammed discloses the integrated device of claim 1,
wherein the die substrate includes silicon (Fig. 1A silicon substrate 20 includes silicon).
Regarding claim 3, Mohammed discloses the integrated device of claim 2,
wherein the die substrate includes an unporosified portion (Par. 106 “the substrate 320 includes a porous silicon region R” and while it isn’t explicitly shown, this teaches that not all of the substrate is to be made porous), and
wherein the porous portion of the die substrate includes a lower density than the unporosified portion of the die substrate (While Mohammed doesn’t explicitly teach about the relative densities of the regions, par. 80 teaches that “the region R of porous silicon can be formed by electrochemical dissolution of the silicon substrate 20 in a solution based on hydrofluoric acid.” Therefore, as the porous section is made porous by electrochemical dissolution, there would necessarily be less matter in the porous sections and so the density would be lower).
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Regarding claim 4, Mohammed discloses the integrated device of claim 1,
wherein the porous portion includes a coefficient of thermal expansion (CTE) in a range of about 5-8 parts per million per Celsius degree (ppm / C) (Par. 53 “the substrate 20 can have an effective CTE less than 8*10-6/° C,” see MPEP 2144.05(I)).
Regarding claim 5, Mohammed discloses the integrated device of claim 1, wherein the porous portion comprises:
a first porous portion comprising a first density (Fig. 2D first region A has a first density); and
a second porous portion comprising a second density (Fig. 2D second region B has a second density).
Regarding claim 6, Mohammed discloses the integrated device of claim 5,
wherein the first porous portion comprises a first coefficient of thermal expansion (CTE) (Fig. 2A first region A has a first CTE), and
wherein the second porous portion comprises a second coefficient of thermal expansion (CTE) (Fig. 2A second region B has a second CTE).
Regarding claim 9, Mohammed discloses the integrated device of claim 1, further comprising
a metallization portion coupled to a back side of the die substrate (Fig. 1A portion of substrate with conductive contacts 60 coupled to back side of first/second TSVs 30a/30b).
Regarding claim 12, Mohammed discloses the integrated device of claim 1, further comprising
at least one cavity in the die substrate (Fig. 1A voids 71 in substrate 20).
Regarding claim 14, Mohammed discloses the integrated device of claim 1, further comprising
an active region (Fig. 1A active semiconductor region 1A).
Regarding claim 15, Mohammed discloses the integrated device of claim 14,
wherein the active region includes a plurality of logic cells, a plurality of transistors, and/or a plurality of filters (Par. 48 “a plurality of active semiconductor devices (e.g., transistors, diodes, etc.) can be disposed in an active semiconductor region 23,” see above rejection of claim 15 under 35 U.S.C. 112(b)).
Regarding claim 16, Mohammed discloses the integrated device of claim 1,
wherein the integrated device is part of a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle (Par. 8 discusses the current inventions place within chip design and therefore use in “devices commonly referred to as “smart phones” [which] integrate the functions of a cellular telephone with powerful data processors, memory and ancillary devices such as global positioning system receivers, electronic cameras, and local area network connections along with high-resolution displays and associated image processing chips”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Mohammed (US20150140807A1) in view of Howard (US20210111101A1).
Regarding claim 7, Mohammed teaches the integrated device of claim 6,
wherein the die substrate includes an unporosified portion comprising a third coefficient of thermal expansion (CTE) (Par. 106 “the substrate 320 includes a porous silicon region R” and while it isn’t explicitly shown, this teaches that not all of the substrate is to be made porous).
Mohammed does not appear to teach
a third CTE that is different from the first coefficient of thermal expansion (CTE) and the second coefficient of thermal expansion (CTE).
Howard teaches in par. 48 that “porous silicon region 222 has a coefficient of thermal expansion (CTE) that more closely matches a CTE of TSV 232, compared to a CTE of bulk silicon substrate 220.” Therefore, as porosity treatment affects CTE, the third unporosified region would have a different CTE than the porosified portions and as first and second regions A/B have different densities, they too would have a different CTE from each other.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Mohammed (US20150140807A1) in view of Faneli et al. (US10134837B1, hereinafter Faneli).
Regarding claim 8, Mohammed discloses the integrated device of claim 1.
Mohammed does not appear to teach
wherein the porous portion comprises a porosity in a range of about 30–70 percent.
Faneli teaches
wherein the porous portion comprises a porosity in a range of about 30–70 percent (Col. 8 “the porous silicon layer 360 may be 20%-60% porous”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mohammed with the teachings of Faneli because, as Mohammed is silent as to the specific level of porosification, this would motivate a person of ordinary skill to seek out references such as Faneli who explicitly discloses the degree of porosification.
Claims 10-11 and 13 is rejected under 35 U.S.C. 103 as being unpatentable over Mohammed (US20150140807A1).
Regarding claim 10, Mohammed teaches the integrated device of claim 9, wherein the metallization portion comprises:
at least one dielectric layer (While Mohammed does not explicitly disclose a dielectric layer disposed adjacent to conductive contacts 60, one of the primary function of an ILD is to provide electrical isolation. A rearrangement of dielectric materials 70 or another dielectric layer to extend adjacent to conductive contacts 60 would not provide any new or unexpected results as the primary function of providing electrical isolation is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore rearrange dielectric materials 70 or another dielectric layer to extend adjacent to conductive contacts 60, see MPEP 2144.04(VI)(B))); and
a plurality of metallization interconnects coupled to the plurality of through substrate vias (Fig. 1A conductive contacts 60 coupled to first/second TSVs 30a/30b).
Regarding claim 11, Mohammed teaches the integrated device of claim 10,
wherein the plurality of metallization interconnects include a plurality of redistribution interconnects (Fig. 1A conductive contacts 60 constitute a plurality of redistribution interconnects. A duplication of a conductive contacts 60 to form redistribution interconnects would not provide any new or unexpected results as the primary function of providing a conducting path is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore duplicate conductive contacts 60 to form redistribution interconnects, see MPEP 2144.04(VI)(B))).
Regarding claim 13, Mohammed teaches the integrated device of claim 1,
wherein a total surface area of all of the plurality of through substrate vias is at least 2 percent of a total surface area of the die substrate (While Mohammed does not explicitly disclose a total surface area of all of the plurality of through substrate vias is at least 2 percent of a total surface area of the die substrate, as the only difference between Mohammed and the claimed invention is a relative recitation of dimensions and nothing within the disclosure indicates that a device having the claimed dimensions would perform differently than Mohammed, such a recitation of relative dimensions is not enough to be patentably distinct, see MPEP 2144.04(IV)(A)).
Claims 17-19, 21-30, and 32-33 are rejected under 35 U.S.C. 103 as being unpatentable over Mohammed (US20150140807A1) in view of Kim et al. (US20150108643A1, hereinafter Kim).
Regarding claim 17, Mohammed teaches
a first integrated device, wherein the first integrated device comprises:
a die substrate comprising a porous portion (Fig. 1A, par. 106 “the substrate 320 includes a porous silicon region R”);
a plurality of through substrate vias extending through the porous portion of the die substrate (Fig. 3A first and second TSVs 330a/330b); and
a die interconnection portion coupled to the die substrate (See above annotated fig. 1A, the portion of substrate 20 extending approximately the length H1 is a die interconnection portion that is coupled to the die substrate).
Mohammed does not appear to teach
a package comprising:
an interposer;
a first integrated device coupled to the interposer through at least a plurality of solder interconnects.
Kim teaches
a package comprising:
an interposer (Par. 32 “the extended substrate 222 may comprise, for example, an interposer”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mohammed with the teachings of Kim because Mohammed teaches in par. 58 that the “plurality of conductive contacts 60 exposed at the rear surface 22 [are] for interconnection with an external element” such as an interposer. Additionally, in par. 62 Mohammed teaches for bonding that “conductive masses can include…solder-filled paste.”
Regarding claim 18, the combination of Mohammed and Kim teaches the package of claim 17,
wherein the die substrate includes silicon (Mohammed fig. 1A silicon substrate 20 includes silicon).
Regarding claim 19, the combination of Mohammed and Kim teaches the package of claim 18,
wherein the die substrate includes an unporosified portion (Mohammed par. 106 “the substrate 320 includes a porous silicon region R” and while it isn’t explicitly shown, this teaches that not all of the substrate is to be made porous), and
wherein the porous portion of the die substrate includes a lower density than the unporosified portion of the die substrate (While Mohammed doesn’t explicitly teach about the relative densities of the regions, par. 80 teaches that “the region R of porous silicon can be formed by electrochemical dissolution of the silicon substrate 20 in a solution based on hydrofluoric acid.” Therefore, as the porous section is made porous by electrochemical dissolution, there would necessarily be less matter in the porous sections and so the density would be lower).
Regarding claim 21, the combination of Mohammed and Kim teaches the package of claim 17,
wherein the first integrated device further comprises a metallization portion coupled to a back side of the die substrate (Mohammed fig. 1A portion of substrate with conductive contacts 60 coupled to back side of first/second TSVs 30a/30b).
Regarding claim 22, the combination of Mohammed and Kim teaches the package of claim 21,
wherein the metallization portion comprises:
at least one dielectric layer (While Mohammed does not explicitly disclose a dielectric layer disposed adjacent to conductive contacts 60, one of the primary function of an ILD is to provide electrical isolation. A rearrangement of dielectric materials 70 or another dielectric layer to extend adjacent to conductive contacts 60 would not provide any new or unexpected results as the primary function of providing electrical isolation is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore rearrange dielectric materials 70 or another dielectric layer to extend adjacent to conductive contacts 60, see MPEP 2144.04(VI)(B))); and
a plurality of metallization interconnects coupled to the plurality of through substrate vias (Fig. 1A conductive contacts 60 coupled to first/second TSVs 30a/30b).
Regarding claim 23, the combination of Mohammed and Kim teaches the package of claim 21, further comprising
a second integrated device coupled to the metallization portion of the first integrated device through a second plurality of solder interconnects (While the combination of Mohammed and Kim does not explicitly disclose a second integrated device coupled to the metallization portion of the first integrated device through a second plurality of solder interconnects, the primary function of the first integrated device as taught above in claim 17 is to provide interconnections for semiconductor devices. A duplication of the first integrated device as taught above in claim 17 to form a second integrated device coupled to the metallization portion of the first integrated device through a second plurality of solder interconnects would not provide any new or unexpected results as the primary function of providing interconnections for semiconductor devices is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore duplicate the first integrated device as taught above in claim 17 to form a second integrated device coupled to the metallization portion of the first integrated device through a second plurality of solder interconnects, see MPEP 2144.04(VI)(B)).
Regarding claim 24, the combination of Mohammed and Kim teaches the package of claim 17, further comprising
a second integrated device coupled to the interposer through a second plurality of solder interconnects (While the combination of Mohammed and Kim does not explicitly disclose a second integrated device coupled to the metallization portion of the first integrated device through a second plurality of solder interconnects, the primary function of the first integrated device as taught above in claim 17 is to provide interconnections for semiconductor devices. A duplication of the first integrated device as taught above in claim 17 to form a second integrated device coupled to the metallization portion of the first integrated device through a second plurality of solder interconnects would not provide any new or unexpected results as the primary function of providing interconnections for semiconductor devices is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore duplicate the first integrated device as taught above in claim 17 to form a second integrated device coupled to the metallization portion of the first integrated device through a second plurality of solder interconnects, see MPEP 2144.04(VI)(B)).
Regarding claim 25, the combination of Mohammed and Kim teaches the package of claim 17, further comprising
at least one cavity in the die substrate (Mohammed fig. 1A voids 71 in substrate 20).
Regarding claim 26, the combination of Mohammed and Kim teaches the package of claim 17,
wherein the interposer includes a silicon substrate and a plurality of interposer interconnects (Kim teaches the use of their extended substrate 916 as an interposer and further teaches in par. 60 that “[t]he extended substrate 520 may comprise an interposer, for example, and a plurality of the bottom bumps 518 formed on the bottom of the extended substrate 520 may comprise one or more of solder balls or conductive pillars.” As Kim teaches the interposer, they also teach the specific materials/conductive pillars and as it is called a substrate, examiner notes that silicon is a common substrate material).
Regarding claim 27, the combination of Mohammed and Kim teaches the package of claim 26.
The combination of Mohammed and Kim as applied to claim 26 does not appear to teach
a substrate coupled to the interposer through a second plurality of solder interconnects.
Kim further teaches
a substrate coupled to the interposer through a second plurality of solder interconnects (Fig. 9E extended substrate 916 is connected to substrate 902 which has further solder bumps 918 disposed below it).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mohammed with the teachings of Kim because Mohammed teaches in par. 58 that the “plurality of conductive contacts 60 exposed at the rear surface 22 [are] for interconnection with an external element” such as an interposer and an additional substrate as taught by Kim.
Regarding claim 28, Mohammed teaches
a first integrated device, wherein the first integrated device comprises:
a die substrate comprising a porous portion (Fig. 1A, par. 106 “the substrate 320 includes a porous silicon region R”);
a plurality of through substrate vias extending through the porous portion of the die substrate (Fig. 3A first and second TSVs 330a/330b); and
a die interconnection portion coupled to the die substrate (See above annotated fig. 1A, the portion of substrate 20 extending approximately the length H1 is a die interconnection portion that is coupled to the die substrate).
Mohammed does not appear to teach
a package comprising:
a substrate;
a first integrated device coupled to the substrate through at least a plurality of solder interconnects.
Kim teaches
a package comprising:
a substrate (Par. 32 “the extended substrate 222 may comprise, for example, an interposer”).;
a first integrated device coupled to the substrate through at least a plurality of solder interconnects.
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mohammed with the teachings of Kim because Mohammed teaches in par. 58 that the “plurality of conductive contacts 60 exposed at the rear surface 22 [are] for interconnection with an external element” such as an interposer. Additionally, in par. 62 Mohammed teaches for bonding that “conductive masses can include…solder-filled paste.”
Regarding claim 29, the combination of Mohammed and Kim teaches the package of claim 28,
wherein the die substrate includes silicon (Mohammed fig. 1A silicon substrate 20 includes silicon).
Regarding claim 30, the combination of Mohammed and Kim teaches the package of claim 29,
wherein the die substrate includes an unporosified portion (Mohammed par. 106 “the substrate 320 includes a porous silicon region R” and while it isn’t explicitly shown, this teaches that not all of the substrate is to be made porous), and
wherein the porous portion of the die substrate includes a lower density than the unporosified portion of the die substrate (While Mohammed doesn’t explicitly teach about the relative densities of the regions, par. 80 teaches that “the region R of porous silicon can be formed by electrochemical dissolution of the silicon substrate 20 in a solution based on hydrofluoric acid.” Therefore, as the porous section is made porous by electrochemical dissolution, there would necessarily be less matter in the porous sections and so the density would be lower).
Regarding claim 32, the combination of Mohammed and Kim teaches the package of claim 28, further comprising
a second integrated device coupled to the first integrated device through a second plurality of solder interconnects (While the combination of Mohammed and Kim does not explicitly disclose a second integrated device coupled to the first integrated device through a second plurality of solder interconnects, the primary function of the first integrated device as taught above in claim 28 is to provide interconnections for semiconductor devices. A duplication of the first integrated device as taught above in claim 28 to form a second integrated device coupled to the first integrated device through a second plurality of solder interconnects would not provide any new or unexpected results as the primary function of providing interconnections for semiconductor devices is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore duplicate the first integrated device as taught above in claim 28 to form a second integrated device coupled to the first integrated device through a second plurality of solder interconnects, see MPEP 2144.04(VI)(B)).
Regarding claim 33, the combination of Mohammed and Kim teaches the package of claim 28, further comprising
a second integrated device coupled to the substrate through a second plurality of solder interconnects a second integrated device coupled to the first integrated device through a second plurality of solder interconnects (While the combination of Mohammed and Kim does not explicitly disclose a second integrated device coupled to the first integrated device through a second plurality of solder interconnects, the primary function of the first integrated device as taught above in claim 28 is to provide interconnections for semiconductor devices. A duplication of the first integrated device as taught above in claim 28 to form a second integrated device coupled to the first integrated device through a second plurality of solder interconnects would not provide any new or unexpected results as the primary function of providing interconnections for semiconductor devices is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore duplicate the first integrated device as taught above in claim 28 to form a second integrated device coupled to the first integrated device through a second plurality of solder interconnects, see MPEP 2144.04(VI)(B)).
Claims 20 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Mohammed in view of Kim as applied to claim 17 and 28 above, and further in view of Howard (US20210111101A1).
Regarding claim 20, the combination of Mohammed and Kim teaches the package of claim 17,
wherein the porous portion comprises:
a first porous portion comprising a first coefficient of thermal expansion (CTE) (Mohammed fig. 2A first region A has a first CTE), and
a second porous portion comprising a second coefficient of thermal expansion (CTE) (Mohammed fig. 2A second region B has a second CTE),
wherein the die substrate includes an unporosified portion comprising a third coefficient of thermal expansion (CTE) (Mohammed par. 106 “the substrate 320 includes a porous silicon region R” and while it isn’t explicitly shown, this teaches that not all of the substrate is to be made porous and this unporosified portion has a third CTE).
The combination of Mohammed and Kim does not appear to teach
a third coefficient of thermal expansion (CTE) that is different from the first coefficient of thermal expansion (CTE) and the second coefficient of thermal expansion (CTE).
Howard teaches in par. 48 that “porous silicon region 222 has a coefficient of thermal expansion (CTE) that more closely matches a CTE of TSV 232, compared to a CTE of bulk silicon substrate 220.” Therefore, as porosity treatment affects CTE, the third unporosified region would have a different CTE than the porosified portions and as first and second regions A/B have different densities, they too would have a different CTE from each other.
Regarding claim 31, the combination of Mohammed and Kim teaches the package of claim 28, wherein the porous portion comprises:
a first porous portion comprising a first coefficient of thermal expansion (CTE) (Mohammed fig. 2A first region A has a first CTE), and
a second porous portion comprising a second coefficient of thermal expansion (CTE) (Mohammed fig. 2A second region B has a second CTE),
wherein the die substrate includes an unporosified portion comprising a third coefficient of thermal expansion (CTE) (Mohammed par. 106 “the substrate 320 includes a porous silicon region R” and while it isn’t explicitly shown, this teaches that not all of the substrate is to be made porous and this unporosified portion has a third CTE).
The combination of Mohammed and Kim does not appear to teach
a third coefficient of thermal expansion (CTE) that is different from the first coefficient of thermal expansion (CTE) and the second coefficient of thermal expansion (CTE).
Howard teaches in par. 48 that “porous silicon region 222 has a coefficient of thermal expansion (CTE) that more closely matches a CTE of TSV 232, compared to a CTE of bulk silicon substrate 220.” Therefore, as porosity treatment affects CTE, the third unporosified region would have a different CTE than the porosified portions and as first and second regions A/B have different densities, they too would have a different CTE from each other.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m..
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/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812