DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 14-20 in the reply filed on 09/15/2023 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 14-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chong et al. (US 11164749 B1, hereinafter Chong)
With regards to claim 14, Chong discloses a method for manufacturing a semiconductor device (FIGS. 1 and 4A-4L) comprising:
forming a first stacked structure (substrate t1) in which a first interconnect layer (through substrate via 108 on T1) having a first bonding pad (bonding pad of through via 108) is formed over a first front surface of a first substrate, a second stacked structure (substrate T2) in which a second interconnect layer (through substrate via 108 on T2) having a second bonding pad (top bonding pad of through via 108) and an electrode pad (bottom bonding pad of through via 108) is formed over a second front surface of a second substrate, and a third stacked structure (substrate T3) in which a third interconnect layer having a third bonding pad is formed over a third front surface of a third substrate; (see FIGS. 1-4F)
disposing the first stacked structure over the second stacked structure such that the first bonding pad and the second bonding pad are directly bonded to each other; (See FIGS. 4A-4C, showing the bonding)
forming an interconnection via structure that penetrates the second substrate and contacts the electrode pad by etching the second substrate and the second interconnect layer; (see FIGS 1 and 4C-4D, showing the etching and formation of the interconnect of the through via 108) and
disposing the third stacked structure (substrate T3) over the second stacked structure such that the interconnection via structure and the third bonding pad are directly bonded to each other. (see FIG. 4E, showing the bonding of the two different portions of the through via 108)
With regards to claim 15, Chong discloses the method according to claim 14, wherein the forming of the interconnection via structure includes:
forming a first through-hole having a first width by etching the second substrate;
forming a second through-hole having a second width smaller than the first width by etching the second interconnect layer to expose the electrode pad; and
forming a conductive material to fill the first through-hole and the second through-hole. (See FIGS. 4C-4D, showing the two holes which are filled to form the through via 108)
With regards to claim 16, Chong discloses the method according to claim 14, further comprising:
after disposing the first stacked structure over the second stacked structure and prior to the forming of the interconnection via structure, etching the second substrate to reduce a thickness of the second substrate to a predetermined thickness. (see FIG. 4B, showing the etching of the second substrate T2 to form two different hole widths)
With regards to claim 17, Chong discloses the method according to claim 16, further comprising:
after the etching of the second substrate, forming a bonding insulation layer over a back surface of the second substrate that is located opposite to a top surface of the second substrate on which the second interconnect layer is formed. (see FIG. 4D, where the dielectric 112 is formed after etching the substrate T2)
With regards to claim 18, Chong discloses the method according to claim 17, wherein the forming the interconnection via structure includes:
forming a first through-hole having a first width by sequentially etching the bonding insulation layer and the second substrate;
forming a second through-hole having a second width smaller than the first width by etching the second interconnect layer to expose the electrode pad; and
forming a conductive material to fill the first through-hole and the second through-hole. (see FIG. 4B, showing the etching of the second substrate T2 to form two different hole widths)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over in view of Hara (US 20230187466 A1)
With regards to claim 19, Chong discloses the method according to claim 14, further comprising:
after the disposing of the third stacked structure on the second stacked structure, etching the first substrate to reduce a thickness of the first substrate to a predetermined thickness; (see FIG. 4P, showing the reduction in thickness).
However, Chong does not explicitly teach forming photoelectric conversion elements and a pixel isolation structure that isolates the photoelectric conversion elements from each other in the first substrate; and
forming color filters and microlenses over the first substrate.
Hara teaches forming photoelectric conversion elements (photoelectric conversion elements 222) and a pixel isolation structure (dielectric 513) that isolates the photoelectric conversion elements from each other in the first substrate; and
forming color filters (color filter 514) and microlenses (microlenses 515) over the first substrate.
It would have been obvious to one of ordinary skill in the art to modify the device of Chong to have the photelectric devices of Hara, as both references are in the same field of endeavor.
One of ordinary skill would appreciate that the device of Hara allows for a reduction in Dark current (see paragraph [0048])
With regards to claim 20, Chong discloses the method according to claim 14.
However, Chong does not explicitly teach wherein:
forming a pad open region exposing the electrode pad by etching the first substrate, the first interconnect layer, and the second interconnect layer.
Hara teaches forming a pad open region (trench 600) exposing the electrode pad (pad 211) by etching the first substrate, the first interconnect layer, and the second interconnect layer. (see FIG. 1)
It would have been obvious to one of ordinary skill in the art to modify the device of Chong to have the photelectric devices/interconnects of Hara, as both references are in the same field of endeavor.
One of ordinary skill would appreciate that the device of Hara allows for a reduction in Dark current (see paragraph [0048])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ishino et al. US 20200343280 A1 – photelectric device with pad open region 264
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812