Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Specification
Amendment to the Specification filed on 04/09/2026 has been reviewed and entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 and 12-21 are rejected under 35 U.S.C. 103 as being unpatentable over Applicant Admitted Prior Art, Figs.1A-1C (U.S. 2025/0098286 A1, hereinafter refer to AAPA) in view of Kitagawa et al. (U.S. 2006/0231894 A1, hereinafter refer to Kitagawa) and Ebina (U.S. 2001/0015461 A1, hereinafter refer to Ebina).
Regarding Claim 1: AAPA discloses an integrated circuit fabricated on a substrate (see AAPA, Figs.1A-1C as shown below and ¶ [0001]) and including:
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(a) a source region (S) (see AAPA, Figs.1A and 1B as shown above)
(b) at least one end-cap body contact region (142) doped to have a first semiconductor characteristic (see AAPA, Figs.1B and 1C as shown above);
(c) a drift region doped to have a second semiconductor characteristic (see AAPA, Figs.1A- 1C as shown above); and
(d) a gate structure (G) partially overlying the at least one end-cap body contact regions region (142), the gate structure (G) including a conductive layer (108) having a third semiconductor characteristic (see AAPA, Figs.1B and 1C as shown above),
AAPA is silent upon explicitly disclosing
(b) at least one end-cap body contact region doped to have a first semiconductor characteristic and positioned outside of the source region;
wherein (d) a gate structure partially overlying the at least one end-cap body contact regions region and the drift region.
For support see Kitagawa, which teaches wherein (b) at least one end-cap body contact region (6) doped to have a first semiconductor characteristic and positioned outside of the source region (5) (see Kitagawa, Figs.14A-14B as shown below and ¶ [0102]- ¶ [0109]);
(c) a gate structure (15) partially overlying the at least one end-cap body contact regions region (6) and the drift region (18) (see Kitagawa, Figs.14A-14B as shown below and ¶ [0102]- ¶ [0109]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of AAPA and Kitagawa to enable the AAPA’s at least one end-cap body contact region doped to be positioned outside of the source region and the gate structure partially overlying the at least one end-cap body contact regions region and the drift region as taught by Kitagawa in order to improve the avalanche withstand value and switching withstand value.
The combination of AAPA and Kitagawa is silent upon explicitly disclosing wherein the conductive layer including a first side oriented towards the at least one end-cap body contact region and doped to have the first semiconductor characteristic.
For support see Ebina, which teaches wherein the conductive layer (24/76/78) including a first side oriented towards the at least one end-cap body contact region (16) and doped to have the first semiconductor characteristic (see Ebina, Figs1-2 as shown below and ¶ [0009]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of AAPA, Kitagawa, and Ebina to enable the conductive layer of the combination of AAPA and Kitagawa to include a first side oriented towards the at least one end-cap body contact region and doped to have the first semiconductor characteristic as taught by Ebina in order to achieve a lower power consumption, even during use under conditions of a comparatively high gate voltage.
Regarding Claim 2: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 1 as above. The combination of AAPA, Kitagawa, and Ebina further teaches wherein the second semiconductor characteristic is an N− type (see AAPA, Fig.1C as shown above).
Regarding Claim 3: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 1 as above. The combination of AAPA, Kitagawa, and Ebina further teaches wherein the conductive layer (50) is polysilicon, the third semiconductor characteristic is an N+ type, and the first semiconductor characteristic is a P+ type (see Ebina, Figs1-2 as shown above and ¶ [0126]).
Regarding Claim 4: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 1 as above. The combination of AAPA, Kitagawa, and Ebina further teaches wherein the conductive layer (G) further includes a second side near the drift region (141), wherein the second side is doped to have a fourth semiconductor characteristic (see AAPA, Figs.1A-1C as shown above).
Regarding Claim 5: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 4 as above. The combination of AAPA, Kitagawa, and Ebina further teaches wherein the conductive layer (24/76/78) is polysilicon (see Ebina, Figs1-2 as shown above and ¶ [0126]),
the third semiconductor characteristic is an N+ type, the first semiconductor characteristic is a P+ type, and the fourth semiconductor characteristic is an N type (see combination of AAPA, Fig.1A as shown above, Kitagawa, Figs.14A-14B as shown above, and Ebina, Figs1-2 as shown above and ¶ [0126]).
Regarding Claim 6: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 1 as above. The combination of AAPA, Kitagawa, and Ebina further teaches wherein the integrated circuit further includes a field-effect transistor region between the end-cap body contact regions (see Kitagawa, Figs.14A-14B as shown above).
Regarding Claim 7: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 6 as above. The combination of AAPA, Kitagawa, and Ebina further teaches wherein the integrated circuit includes an active layer having a thin region and a thick region, wherein the field-effect transistor region is fabricated in and on the thin region and the end-cap body contact regions are fabricated on the thick region (see Kitagawa, Figs.14A-14B as shown above).
Regarding Claim 8: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 1 as above. The combination of AAPA, Kitagawa, and Ebina further teaches wherein the conductive layer of the gate structure is fabricated to have at least two levels in series between the first side of the conductive layer and an opposing second side of the conductive layer (see AAPA, Fig.1C as shown above).
Regarding Claim 9: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 1 as above. The combination of AAPA, Kitagawa, and Ebina further teaches wherein a portion of the drift region near the gate structure is doped to have a fifth semiconductor characteristic (see AAPA, Figs.1A-1C as shown above).
Regarding Claim 10: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 9 as above. The combination of AAPA, Kitagawa, and Ebina further teaches wherein the fifth semiconductor characteristic is a P-type (see AAPA, Figs.1A-1C as shown above).
Regarding Claim 12: AAPA discloses an integrated circuit fabricated on a substrate (see AAPA, Figs.1A-1C as shown above and ¶ [0001]) and including:
(a) a source region (S) (see AAPA, Fig.1A as shown above);
(b) a drift region (141) (see AAPA, Fig.1A as shown above);
(c) a gate structure (G) including a first side adjacent the source region, a second side adjacent the drift region, and first and second edges perpendicular to the first and second sides (see AAPA, Figs.1A and 1C as shown above);
(d) a drain region (D) adjacent the drift region (see AAPA, Figs.1A-1B as shown above);
the gate structure (G) including a conductive layer having a second semiconductor characteristic (see AAPA, Figs.1A-1C as shown above).
AAPA is silent upon explicitly disclosing wherein (e) first and second body contact regions positioned outside of the source region and partially underlying respective ones of the first and second edges of the gate structure and doped to have a first semiconductor characteristic;
wherein the first and second edges of the gate structure partially overlay respective ones of the first and second body contact regions and the drift region.
For support see Kitagawa, which teaches wherein (e) first and second body contact regions (6) positioned outside of the source region (5) and partially underlying respective ones of the first and second edges of the gate structure (15) and doped to have a first semiconductor characteristic (see Kitagawa, Figs.14A-14B as shown above and ¶ [0102]- ¶ [0109]);
wherein the first and second edges of the gate structure (15) partially overlay respective ones of the first and second body contact regions (6) and the drift region (18) (see Kitagawa, Figs.14A-14B as shown above and ¶ [0102]- ¶ [0109]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of AAPA and Kitagawa to enable the first and second body contact regions to be positioned outside of the source region and partially underlying respective ones of the first and second edges of the gate structure and doped to have a first semiconductor characteristic and the first and second edges of the gate structure to partially overlay respective ones of the first and second body contact regions and the drift region as taught by Kitagawa in order to improve the avalanche withstand value and switching withstand value.
The combination of AAPA and Kitagawa is silent upon explicitly disclosing wherein the conductive layer including a first side doped near the first and second body contact regions to have the first semiconductor characteristic.
For support see, Ebina, which teaches wherein the conductive layer (24/76/78) including a side doped near the body contact regions (16) to have the first semiconductor characteristic (see Ebina, Figs1-2 as shown above and ¶ [0009]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of AAPA, Kitagawa, and Ebina to enable the conductive layer of the combination of AAPA and Kitagawa to include a side doped near the body contact regions to have the first semiconductor characteristic as taught by Ebina in order to achieve a lower power consumption, even during use under conditions of a comparatively high gate voltage.
Hence, practicing the combination of AAPA, Kitagawa, and Ebina to modify the combination of AAPA and Kitagawa to include a side doped near the body contact regions to have the first semiconductor characteristic as taught by Ebina necessarily results the combination of AAPA and Kitagawa conductive layer to include “a first side doped near the first and second body contact regions to have the first semiconductor characteristic” as now specified in claim 12.
Regarding Claim 13: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 12 as above. The combination of AAPA, Kitagawa, and Ebina further teaches wherein the drift region has an N− type characteristic (see AAPA, Fig.1A as shown above).
Regarding Claim 14: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 12 as above. The combination of AAPA, Kitagawa, and Ebina further teaches wherein the conductive layer (24/76/78) is polysilicon, the second semiconductor characteristic is an N+ type, and the first semiconductor characteristic is a P+ type (see Ebina, Figs1-2 as shown above and ¶ [0126]).
Regarding Claim 15: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 12 as above. The combination of AAPA, Kitagawa, and Ebina further teaches wherein the conductive layer further includes a second side near the drift region (see Kitagawa, Figs.14A-14B as shown above and ¶ [0102]- ¶ [0109]),
wherein the second side is doped to have a third semiconductor characteristic (see Ebina, Figs1-2 as shown above and ¶ [0126]).
Regarding Claim 16: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 15 as above. The combination of AAPA, Kitagawa, and Ebina further teaches wherein the conductive layer (24/79/78) is polysilicon (see Ebina, Figs1-2 as shown above and ¶ [0126]),
the second semiconductor characteristic is an N+ type, the first semiconductor characteristic is a P+ type, and the third semiconductor characteristic is an N type (see combination of AAPA, Fig.1A as shown above, Kitagawa, Figs.14A-14B as shown above, and Ebina, Figs1-2 as shown above and ¶ [0126]).
Regarding Claim 17: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 12 as above. The combination of AAPA, Kitagawa, and Ebina further teaches wherein the integrated circuit further includes a field-effect transistor region between the first and second end-cap body contact regions (6) (see Kitagawa, Figs.14A-14B as shown above).
Regarding Claim 18: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 17 as above. The combination of AAPA, Kitagawa, and Ebina further teaches wherein the integrated circuit includes an active layer having a thin region and a thick region, wherein the field-effect transistor region is fabricated in and on the thin region and the first and second end-cap body contact regions (6) are fabricated on respective portions of the thick region (see Kitagawa, Figs.14A-14B as shown above).
Regarding Claim 19: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 12 as above. The combination of AAPA, Kitagawa, and Ebina further teaches wherein the conductive layer of the gate structure is fabricated to have at least two levels in series between the first side and the second side of the conductive layer (see AAPA, Fig.1A as shown above).
Regarding Claim 20: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 12 as above. The combination of AAPA, Kitagawa, and Ebina further teaches wherein a portion of the drift region near the gate structure is doped to have a fourth semiconductor characteristic (see AAPA, Fig.1A as shown above and/or see Kitagawa, Figs.14A-14B as shown above).
Regarding Claim 21: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 20 as above. The combination of AAPA, Kitagawa, and Ebina further teaches wherein the fourth semiconductor characteristic is a P-type (see AAPA, Fig.1A as shown above and/or see Kitagawa, Figs.14A-14B as shown above).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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