Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/23/2026 has been entered.
Response to Arguments
Applicant's arguments filed on 07/16/2026 have been fully considered but after further consideration, they are not persuasive.
The Applicant argues that in regard to claims 1 and 12 that the combination of Kitagawa, AAPA, and Ebina prior art, ***Inventor of prior art, does not teach the limitation of the “a source region having no embedded body contact region;
the gate structure including a conductive layer having a third semiconductor characteristic, the conductive layer including a first side oriented towards the source region and the at least one end-cap body contact region and doped to have the first semiconductor characteristic.”
In response to this argument, the Examiner directs the applicant’s attention to the combination of Kitagawa, AAPA, and Ebina prior art, which teaches the recited limitation as follows:
Kitagawa teaches a source region (5) having no embedded body contact region (6) (see Kitagawa, Figs.14A-14B as shown below);
In addition, Ebina teaches wherein the gate structure (24) including a conductive layer (24) having a third semiconductor characteristic, the conductive layer (24) including a first side oriented towards the source region (40) and the at least one end-cap body contact region (16) and doped to have the first semiconductor characteristic (see Ebina, Figs. 1 and 14-15 as shown below and ¶ [0009]).
Hence, practicing the combination of Kitagawa and Ebina to modify the Kitagawa gate structure conductive layer to have the third semiconductor characteristic necessary results the claimed the conductive layer of Kitagawa to include a first side oriented towards the source region and the at least one end-cap body contact region and doped to have the first semiconductor characteristic as now specified in claim 1.
In addition, during patent examination, the pending claims must be "given their broadest reasonable interpretation consistent with the specification." In re Hyatt, 211 F.3d 1367, 1372, 54 USPQ2d 1664, 1667 (Fed. Cir. 2000). While the claims of issued patents are interpreted in light of the specification, prosecution history, prior art and other claims, this is not the mode of claim interpretation to be applied during examination. During examination, the claims must be interpreted as broadly as their terms reasonably allow. In re American Academy of Science Tech Center, F.3d, 2004 WL 1067528 (Fed. Cir. May 13, 2004) (The USPTO uses a different standard for construing claims than that used by district courts; during examination the USPTO must give claims their broadest reasonable interpretation.) This means that the words of the claim must be given their plain meaning unless applicant has provided a clear definition in the specification. In re Zletz, 893 F.2d 319, 321, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989) >; Chef America, Inc. v. Lamb-Weston, Inc., 358 F.3d 1371, 1372, 69 USPQ2d 1857 (Fed. Cir. 2004).
The Examiner would further point out that “The use of patents as references is not limited to what the patentees describe as their own inventions or to the problems with which they are concerned. They are part of the literature of the art, relevant for all they contain.” In re Heck, 699 F.2d 1331, 1332-33, 216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). Therefore, the combination of Kitagawa, AAPA, and Ebina prior art reference does meet all the limitation in claims 1 and 12.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “body contact region" in line 2. Claim 1 further recites the limitation “end-cap body contact region" in line 3. It is unclear whether the limitation of “end-cap body contact region” was intended to relate back to “body contact region.”
For purpose of compact prosecution, “end-cap body contact region” will be treated as if it were “body contact region.”
Claims 2-10 are rejected as depending on rejected claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kitagawa et al. (U.S. 2006/0231894 A1, hereinafter refer to Kitagawa) in view of Applicant Admitted Prior Art, Figs.1A-1C (U.S. 2025/0098286 A1, hereinafter refer to AAPA) and Ebina (U.S. 2001/0015461 A1, hereinafter refer to Ebina).
Regarding Claim 1: Kitagawa discloses an integrated circuit fabricated on a substrate (see Kitagawa, Figs.14A-14B as shown below and ¶ [0005]) and including:
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(a) a source region (5) having no embedded body contact region (6) (see Kitagawa, Figs.14A-14B as shown above);
(b) at least one end-cap body contact region (6) doped to have a first semiconductor characteristic and positioned outside of the source region (5) (see Kitagawa, Figs.14A-14B as shown above);
(c) a drift region (18) doped to have a second semiconductor characteristic (note: Kitagawa teaches n-type or p-type drift region; hence, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to select the desired conductivity type of drift region for obtaining the desired metal-oxide-semiconductor field-effect transistors (MOSFETs). For support see, AAPA, Figs.1A-1C, which teaches an n-type drift region obtaining a metal-oxide-semiconductor field-effect transistors (MOSFETs)) (see Kitagawa, Figs.14A-14B as shown above); and
(d) a gate structure (15/14/16) partially overlying the at least one end-cap body contact region (6) and the drift region (18), the gate structure (14/15/16) including a conductive layer (15) (see Kitagawa, Figs.14A-14B as shown above and ¶ [0102]- ¶ [0109]).
Kitagawa is silent upon explicitly disclosing wherein the gate structure including a conductive layer having a third semiconductor characteristic, the conductive layer including a first side oriented towards the source region and the at least one end-cap body contact region and doped to have the first semiconductor characteristic.
For support see Ebina, which teaches wherein the gate structure (24) including a conductive layer (24) having a third semiconductor characteristic, the conductive layer (24) including a first side oriented towards the source region (40) and the at least one end-cap body contact region (16) and doped to have the first semiconductor characteristic (see Ebina, Figs. 1 and 14-15 as shown below and ¶ [0009]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kitagawa, AAPA, and Ebina to enable the gate structure including a conductive layer of Kitagawa to have a third semiconductor characteristic, the conductive layer including a first side oriented towards the source region and the at least one end-cap body contact region and doped to have the first semiconductor characteristic as taught by Ebina in order to achieve a lower power consumption, even during use under conditions of a comparatively high gate voltage.
Hence, practicing the combination of Kitagawa and Ebina to modify the Kitagawa gate structure conductive layer to have the third semiconductor characteristic necessary results the claimed the conductive layer of Kitagawa to include a first side oriented towards the source region and the at least one end-cap body contact region and doped to have the first semiconductor characteristic as now specified in claim 1.
Regarding Claim 2: Kitagawa as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 1 as above. The combination of Kitagawa, AAPA, and Ebina further teaches wherein the second semiconductor characteristic is an N− type (see AAPA, Fig.1C as shown above).
Regarding Claim 3: Kitagawa as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 1 as above. The combination of Kitagawa, AAPA, and Ebina further teaches wherein the conductive layer (50) is polysilicon, the third semiconductor characteristic is an N+ type, and the first semiconductor characteristic is a P+ type (see Ebina, Figs.1 and 14-15 as shown above and ¶ [0126]).
Regarding Claim 4: Kitagawa as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 1 as above. The combination of Kitagawa, AAPA, and Ebina further teaches wherein the conductive layer (G) further includes a second side near the drift region (141), wherein the second side is doped to have a fourth semiconductor characteristic (see AAPA, Figs.1A-1C as shown above).
Regarding Claim 5: Kitagawa as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 4 as above. The combination of Kitagawa, AAPA, and Ebina further teaches wherein the conductive layer (24/76/78) is polysilicon (see Ebina, Figs.1 and 14-15 as shown above and ¶ [0126]),
the third semiconductor characteristic is an N+ type, the first semiconductor characteristic is a P+ type, and the fourth semiconductor characteristic is an N type (see combination of AAPA, Fig.1A as shown above, Kitagawa, Figs.14A-14B as shown above, and Ebina, Figs.1 and 14-15 as shown above and ¶ [0126]).
Regarding Claim 6: Kitagawa as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 1 as above. The combination of Kitagawa, AAPA, and Ebina further teaches wherein the integrated circuit further includes a field-effect transistor region between the end-cap body contact regions (6) (see Kitagawa, Figs.14A-14B as shown above).
Regarding Claim 7: Kitagawa as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 6 as above. The combination of Kitagawa, AAPA, and Ebina further teaches wherein the integrated circuit includes an active layer having a thin region and a thick region, wherein the field-effect transistor region is fabricated in and on the thin region and the end-cap body contact regions (6) are fabricated on the thick region (see Kitagawa, Figs.14A-14B as shown above).
Regarding Claim 8: Kitagawa as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 1 as above. The combination of Kitagawa, AAPA, and Ebina further teaches wherein the conductive layer (24) of the gate structure is fabricated to have at least two levels in series between the first side of the conductive layer (24) and an opposing second side of the conductive layer (24) (see Ebina, Figs.1 and 14-15 as shown above).
Regarding Claim 9: Kitagawa as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 1 as above. The combination of Kitagawa, AAPA, and Ebina further teaches wherein a portion of the drift region near the gate structure is doped to have a fifth semiconductor characteristic (see AAPA, Figs.1A-1C as shown above).
Regarding Claim 10: Kitagawa as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 9 as above. The combination of Kitagawa, AAPA, and Ebina further teaches wherein the fifth semiconductor characteristic is a P-type (see AAPA, Figs.1A-1C as shown above).
Claim(s) 12-21 are rejected under 35 U.S.C. 103 as being unpatentable over Kitagawa et al. (U.S. 2006/0231894 A1, hereinafter refer to Kitagawa) in view of Ebina (U.S. 2001/0015461 A1, hereinafter refer to Ebina).
Regarding Claim 12: Kitagawa discloses an integrated circuit fabricated on a substrate (see Kitagawa, Figs.14A-14B as shown above and ¶ [0005]) and including:
(a) a source region (5) having no embedded body contact region (6) (see Kitagawa, Figs.14A-14B as shown above);
(b) a drift region (18) (see Kitagawa, Figs.14A-14B as shown above);
(c) a gate structure (14/15/16) including a first side adjacent the source region (5), a second side adjacent the drift region (18), and first and second edges perpendicular to the first and second sides (see Kitagawa, Figs.14A-14B as shown above);
(d) a drain region (7) adjacent the drift region (18) (see Kitagawa, Figs.14A-14B as shown above);
(e) first and second body contact regions (6) positioned outside of the source region (5) and partially underlying respective ones of the first and second edges of the gate structure (14/15/16) and doped to have a first semiconductor characteristic (see Kitagawa, Figs.14A-14B as shown above);
wherein the first and second edges of the gate structure (14/15/16) partially overlay respective ones of the first and second body contact regions (6) and the drift region (18), the gate structure (14/15/16) including a conductive layer (15) (see Kitagawa, Figs.14A-14B as shown above).
Kitagawa is silent upon explicitly disclosing wherein the gate structure including a conductive layer having a second semiconductor characteristic, the conductive layer including a first side oriented towards the source region and doped near the first and second body contact regions to have the first semiconductor characteristic.
For support see Ebina, which teaches wherein the gate structure (24) including a conductive layer (24) having a second semiconductor characteristic, the conductive layer (24) including a first side oriented towards the source region (40) and doped near the first and second body contact regions (16) to have the first semiconductor characteristic (see Ebina, Figs. 1 and 14-15 as shown above and ¶ [0009]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kitagawa and Ebina to enable the gate structure including a conductive layer of Kitagawa to have a second semiconductor characteristic, the conductive layer including a first side oriented towards the source region and doped near the first and second body contact regions to have the first semiconductor characteristic as taught by Ebina in order to achieve a lower power consumption, even during use under conditions of a comparatively high gate voltage.
Hence, practicing the combination of Kitagawa and Ebina to modify the Kitagawa gate structure conductive layer to have the second semiconductor characteristic necessary results the claimed the conductive layer of Kitagawa to include a first side oriented towards the source region and doped near the first and second body contact regions to have the first semiconductor characteristic as now specified in claim 1.
Regarding Claim 13: Kitagawa as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 12 as above. The combination of Kitagawa and Ebina further teaches wherein the drift region (18) has an N− type characteristic (see Kitagawa, Figs.14A-14B as shown above).
Regarding Claim 14: Kitagawa as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 12 as above. The combination of Kitagawa and Ebina further teaches wherein the conductive layer (24/76/78) is polysilicon, the second semiconductor characteristic is an N+ type, and the first semiconductor characteristic is a P+ type (see Ebina, Figs.1 and 14-15 as shown above and ¶ [0126]).
Regarding Claim 15: Kitagawa as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 12 as above. The combination of Kitagawa and Ebina further teaches wherein the conductive layer (15) further includes a second side near the drift region (see Kitagawa, Figs.14A-14B as shown above and ¶ [0102]- ¶ [0109]),
wherein the second side is doped to have a third semiconductor characteristic (see Ebina, Figs.1 and 14-15 as shown above and ¶ [0126]).
Regarding Claim 16: Kitagawa as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 15 as above. The combination of Kitagawa and Ebina further teaches wherein the conductive layer (24/79/78) is polysilicon (see Ebina, Figs.1 and 14-15 as shown above and ¶ [0126]),
the second semiconductor characteristic is an N+ type, the first semiconductor characteristic is a P+ type, and the third semiconductor characteristic is an N type (see combination of Kitagawa, Figs.14A-14B as shown above and Ebina, Figs.1 and 14-15 as shown above and ¶ [0126]).
Regarding Claim 17: Kitagawa as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 12 as above. The combination of Kitagawa and Ebina further teaches wherein the integrated circuit further includes a field-effect transistor region between the first and second end-cap body contact regions (6) (see Kitagawa, Figs.14A-14B as shown above).
Regarding Claim 18: Kitagawa as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 17 as above. The combination of Kitagawa and Ebina further teaches wherein the integrated circuit includes an active layer having a thin region and a thick region, wherein the field-effect transistor region is fabricated in and on the thin region and the first and second end-cap body contact regions (6) are fabricated on respective portions of the thick region (see Kitagawa, Figs.14A-14B as shown above).
Regarding Claim 19: Kitagawa as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 12 as above. The combination of Kitagawa and Ebina further teaches wherein the conductive layer (24) of the gate structure (24) is fabricated to have at least two levels in series between the first side and the second side of the conductive layer (see Ebina, Figs.1 and 14-15 as shown above).
Regarding Claim 20: Kitagawa as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 12 as above. The combination of Kitagawa and Ebina further teaches wherein a portion of the drift region (18) near the gate structure (14/15/16) is doped to have a fourth semiconductor characteristic (see Kitagawa, Figs.14A-14B as shown above).
Regarding Claim 21: Kitagawa as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 20 as above. The combination of Kitagawa and Ebina further teaches wherein the fourth semiconductor characteristic is a P-type (see Kitagawa, Figs.14A-14B as shown above).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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