DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Applicant Admitted Prior Art, Figs.1A-1C (U.S. 2025/0098286 A1, hereinafter refer to AAPA) in view of Mori (U.S. 2015/0325693 A1, hereinafter refer to Mori) and Nakano et al. (JP 2009-212237 A, hereinafter refer to Nakano).
Regarding Claim 1: AAPA discloses an integrated circuit fabricated on a substrate (see AAPA, Figs.1A-1C as shown below and ¶ [0001]) and including:
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(a) end-cap body contact regions (142) doped to have a first semiconductor characteristic (note: before effective filing date of the claimed invention, ordinary skill in the art capable of omitting the region around the outer side of body contact region 142, in order to obtain or demonstrate the body contact region as end-cap body contact region, if the function or demonstrating the outer region of body contact region 142 not needed) (see AAPA, Fig.1C as shown above);
(b) a drift region doped to have a second semiconductor characteristic (see AAPA, Fig.1C as shown above).
AAPA is silent upon explicitly disclosing wherein (c) a gate structure partially overlying the end-cap body contact regions and the drift region.
Before effective filing date of the claimed invention the disclosed gate structure were known to partially overlying the end-cap body contact regions and the drift region in order to obtain an LDMOS having a structure that reduces ON-resistance between a source region and a drain region while increasing a breakdown voltage between a gate electrode and the drain region.
For support see Mori, which teaches wherein (c) a gate structure (GE) partially overlying the end-cap body contact regions (PBD) and the drift region (NDR) (see Mori, Figs.1-2 as shown below and ¶ [0005]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of AAPA and Mori to enable the AAPA gate structure to be partially overlying the end-cap body contact regions and the drift region as taught by Mori in order to obtain an LDMOS having a structure that reduces ON-resistance between a source region and a drain region while increasing a breakdown voltage between a gate electrode and the drain region.
The combination of AAPA and Mori is silent upon explicitly disclosing wherein the gate structure including a conductive layer having a third semiconductor characteristic, the conductive layer including a first side doped to have the first semiconductor characteristic.
Before effective filing date of the claimed invention the disclosed gate structure were known to include a conductive layer having a third semiconductor characteristic, the conductive layer including a first side doped to have the first semiconductor characteristic in order to obtain a semiconductor device capable of suppressing the occurrence of radio noise while suppressing an increase in switching loss without increasing the size of the body.
For support see Nakano, which teaches wherein the gate structure (50) including a conductive layer having a third semiconductor characteristic, the conductive layer including a first side doped to have the first semiconductor characteristic (see Nakano, Figs.1-13 and page.2).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of AAPA, Mori, and Nakano to enable the combination of AAPA and Mori gate structure to include a conductive layer having a third semiconductor characteristic, the conductive layer including a first side doped to have the first semiconductor characteristic as taught by Nakano in order to obtain a semiconductor device capable of suppressing the occurrence of radio noise while suppressing an increase in switching loss without increasing the size of the body.
Regarding Claim 2: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 1 as above. The combination of AAPA, Mori, and Nakano further teaches wherein the second semiconductor characteristic is an N− type (see AAPA, Fig.1C as shown above and see Mori, Figs.1-2 as shown above).
Regarding Claim 3: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 1 as above. The combination of AAPA, Mori, and Nakano further teaches wherein the conductive layer (50) is polysilicon, the third semiconductor characteristic is an N+ type, and the first semiconductor characteristic is a P+ type (see Nakano, Figs.1-13).
Regarding Claim 4: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 1 as above. The combination of AAPA, Mori, and Nakano further teaches wherein the conductive layer (50) further includes a second side near the drift region, wherein the second side is doped to have a fourth semiconductor characteristic (see Nakano, Figs.1-13).
Regarding Claim 5: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 4 as above. The combination of AAPA, Mori, and Nakano further teaches wherein the conductive layer (50) is polysilicon, the third semiconductor characteristic is an N+ type, the first semiconductor characteristic is a P+ type, and the fourth semiconductor characteristic is an N type (see Nakano, Figs.1-13).
Note: it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the doping concentration of the conductive layer through routine experimentation and optimization to obtain optimal or desired device performance because the doping concentration of the conductive layer is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Regarding Claim 6: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 1 as above. The combination of AAPA, Mori, and Nakano further teaches wherein the integrated circuit further includes a field-effect transistor region between the end-cap body contact regions (see AAPA, Fig.1C as shown above and see Mori, Figs.1-2 as shown above).
Regarding Claim 7: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 6 as above. The combination of AAPA, Mori, and Nakano further teaches wherein the integrated circuit includes an active layer having a thin region and a thick region, wherein the field-effect transistor region is fabricated in and on the thin region and the end-cap body contact regions are fabricated on the thick region (see AAPA, Fig.1C as shown above and see Mori, Figs.1-2 as shown above).
Regarding Claim 8: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 1 as above. The combination of AAPA, Mori, and Nakano further teaches wherein the conductive layer of the gate structure is fabricated to have at least two levels in series between the first side of the conductive layer and an opposing second side of the conductive layer (see AAPA, Fig.1C as shown above).
Regarding Claim 9: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 1 as above. The combination of AAPA, Mori, and Nakano further teaches wherein a portion of the drift region near the gate structure is doped to have a fifth semiconductor characteristic (see AAPA, Figs.1A-1C as shown above).
Regarding Claim 10: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 9 as above. The combination of AAPA, Mori, and Nakano further teaches wherein the fifth semiconductor characteristic is a P-type (see AAPA, Figs.1A-1C as shown above).
Claim(s) 12-21 are rejected under 35 U.S.C. 103 as being unpatentable over Applicant Admitted Prior Art, Figs.1A-1C (U.S. 2025/0098286 A1, hereinafter refer to AAPA) in view of Nakano et al. (JP 2009-212237 A, hereinafter refer to Nakano).
Regarding Claim 12: AAPA discloses an integrated circuit fabricated on a substrate (see AAPA, Figs.1A-1C as shown above and ¶ [0001]) and including:
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(a) a source region (see AAPA, Fig.1A as shown above);
(b) a drift region (see AAPA, Fig.1A as shown above);
(c) a gate structure (G) including a first side adjacent the source region, a second side adjacent the drift region, and first and second edges perpendicular to the first and second sides (see AAPA, Fig.1C as shown above);
(d) a drain region adjacent the drift region (see AAPA, Fig.1A as shown above);
(e) first and second body contact regions (note: an opposite edge side surface of a portion of P-B region is serve as equivalent to the claimed limitation of “first and second body contact regions”) partially underlying respective ones of the first and second edges of the gate structure and doped to have a first semiconductor characteristic (see AAPA, Fig.1A as shown above);
wherein the first and second edges of the gate structure partially overly respective ones of the first and second body contact regions and the drift region (see AAPA, Fig.1A as shown above).
AAPA is silent upon explicitly disclosing wherein the gate structure including a conductive layer having a second semiconductor characteristic.
Before effective filing date of the claimed invention the disclosed gate structure were known to include a conductive layer having a second semiconductor characteristic in order to obtain a semiconductor device capable of suppressing the occurrence of radio noise while suppressing an increase in switching loss without increasing the size of the body.
For support see Nakano, which teaches wherein the gate structure (50) including a conductive layer having a second semiconductor characteristic (see Nakano, Figs.1-13 and page.2).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of AAPA and Nakano to enable the combination of AAPA and Mori gate structure (50) to include a conductive layer having a second semiconductor characteristic as taught by Nakano in order to obtain a semiconductor device capable of suppressing the occurrence of radio noise while suppressing an increase in switching loss without increasing the size of the body.
The combination of AAPA and Nakano is silent upon explicitly disclosing wherein the conductive layer including a first side doped near the first and second body contact regions to have the first semiconductor characteristic.
However, practicing the combination of AAPA and Nakano to modify the AAPA gate structure to include a conductive layer having a second semiconductor characteristic as taught by Nakano necessarily results the combination of AAPA and Nakano to have “the conductive layer including a first side doped near the first and second body contact regions to have the first semiconductor characteristic” as now specified in claim 12.
Regarding Claim 13: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 12 as above. The combination of AAPA and Nakano further teaches wherein the drift region has an N− type characteristic (see AAPA, Fig.1A as shown above).
Regarding Claim 14: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 12 as above. The combination of AAPA and Nakano further teaches wherein the conductive layer (50) is polysilicon, the second semiconductor characteristic is an N+ type, and the first semiconductor characteristic is a P+ type (see Nakano, Figs.1-13 and page.2).
Regarding Claim 15: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 12 as above. The combination of AAPA and Nakano further teaches wherein the conductive layer further includes a second side near the drift region (see AAPA, Fig.1A as shown above),
wherein the second side is doped to have a third semiconductor characteristic (see Nakano, Figs.1-13 and page.2).
Regarding Claim 16: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 15 as above. The combination of AAPA and Nakano further teaches wherein the conductive layer (50) is polysilicon, the second semiconductor characteristic is an N+ type, the first semiconductor characteristic is a P+ type, and the third semiconductor characteristic is an N type (see Nakano, Figs.1-13 and page.2).
Regarding Claim 17: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 12 as above. The combination of AAPA and Nakano further teaches wherein the integrated circuit further includes a field-effect transistor region between the first and second end-cap body contact regions (see AAPA, Fig.1A as shown above).
Regarding Claim 18: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 17 as above. The combination of AAPA and Nakano further teaches wherein the integrated circuit includes an active layer having a thin region and a thick region, wherein the field-effect transistor region is fabricated in and on the thin region and the first and second end-cap body contact regions are fabricated on respective portions of the thick region (see AAPA, Fig.1A as shown above).
Regarding Claim 19: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 12 as above. The combination of AAPA and Nakano further teaches wherein the conductive layer of the gate structure is fabricated to have at least two levels in series between the first side and the second side of the conductive layer (see AAPA, Fig.1A as shown above).
Regarding Claim 20: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 12 as above. The combination of AAPA and Nakano further teaches wherein a portion of the drift region near the gate structure is doped to have a fourth semiconductor characteristic (see AAPA, Fig.1A as shown above).
Regarding Claim 21: AAPA as modified teaches an integrated circuit fabricated on a substrate as set forth in claim 20 as above. The combination of AAPA and Nakano further teaches wherein the fourth semiconductor characteristic is a P-type (see AAPA, Fig.1A as shown above).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812