Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s election, without traverse, of Group I, claims 1-7 and 14-25 in the reply filed on March 05th, 2026, is acknowledged. Non-elected invention of Group II, claims 8-13 have been withdrawn from consideration. Claims 1-25 are pending.
Action on merits of Group I, claims 1-7 and 14-25 as follows.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on September 17th, 2023 and December 03rd, 2024 have been considered by the examiner.
Drawings
The drawings filed on 09/17/2023 are acceptable.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112(f)/sixth paragraph
CLAIM INTERPRETATION
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a high-κ metal gate (HKMG) configured to activate nanosheet channels …” as recited in claim 21.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
If applicant wishes to provide further explanation or dispute the examiner’s interpretation of the corresponding structure, applicant must identify the corresponding structure with reference to the specification by page and line number, and to the drawing, if any, by reference characters in response to this Office action.
For more information, see MPEP § 2173 et seq. and Supplementary Examination Guidelines for Determining Compliance With 35 U.S.C. 112 and for Treatment of Related Issues in Patent Applications, 76 FR 7162, 7167 (Feb. 9, 2011).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-3, 6, 14-15, 18 and 21-25 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Xie (US 2023/0086033, hereinafter as Xie ‘033).
Regarding Claim 1, Xie ‘033 teaches a semiconductor structure, comprising:
a front-end-of-line (FEOL) comprising a first source/drain (S/D) (Fig. 15A, (122); [0053]) adjacent to a first gate (126; [0057]);
a backside interconnect below the FEOL, comprising a plurality of signal lines (1446; [0063]) and a plurality of power lines (Fig. 15E, (1448); [0063]); and
an offset gate contact (Fig. 15A, (1438); [0063]) electrically connected between the first gate and a first signal line of the plurality of signal lines, wherein the offset gate contact (1438) is located directly below the first S/D (122) (see Fig. 15A).
Regarding Claim 14, Xie ‘033 teaches a semiconductor structure, comprising:
a first gate (Fig. 15A, (126); [0057]);
a first source/drain (S/D) (Fig. 15A, (122); [0053]) adjacent to the first gate (126), and connected to a back-end-of-line (BEOL) through a S/D contact (130; [0057]) directly above the first S/D; and
an offset gate contact (Fig. 15A, (1438); [0063]) electrically connected between the first gate and a first level signal line, wherein the offset gate contact is located directly below the first S/D (see Fig. 15A).
Regarding Claim 21, Xie ‘033 teaches a semiconductor structure, comprising:
a first gate comprising a high-κ metal gate (HKMG) (126; [0065]) configured to activate nanosheet channels (122; [0065]);
a gate extension (1436; [0062]) extending vertically from the (HKMG); and
an offset gate contact (1438; [0062]) laterally adjacent to the gate extension.
Regarding Claim 24, Xie ‘033 teaches a semiconductor structure, comprising:
a first source/drain (S/D) (Fig. 15A, (122); [0053]);
a first gate (Fig. 15A, (126); [0065]) adjacent to the first S/D;
an offset gate contact (1438; [0062]) electrically connected between the first gate and a first signal line of the plurality of signal lines, wherein the offset gate contact is located directly below the first S/D (122) (see Fig. 15A).
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Fig. 15A (Xie ‘033)
Regarding Claim 2, Xie ‘033 teaches a frontside back-end-of-line (BEOL) above the FEOL comprising signal processing layers (see para. [0057]).
Regarding Claims 3, 15 and 25, Xie ‘033 teaches a backside gate extension directly below the first gate (126), and electrically connected between the first gate (126) and the offset gate contact (138) (see Fig. 12A).
Regarding Claims 6 and 18, Xie ‘033 teaches a second S/D (122) adjacent to the first gate (126), wherein the second S/D is electrically connected to the backside interconnect through a S/D contact (130; [0057]) directly below the second S/D.
Regarding Claim 22, Xie ‘033 teaches the offset gate contact (1438) is electrically connected to a first signal line (1446; [0063]) of a backside interconnect.
Regarding Claim 23, Xie ‘033 teaches the backside interconnect comprises a first power line (1448; [0063]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5, 7, 16-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Xie ‘033 as applied to claim 3 above, and further in view of Chen (US 2022/0165733, hereinafter as Chen ‘733).
Regarding Claims 4 and 16, Xie ‘033 is shown to teach all the features of the claim with the exception of explicitly the features: “a backside gate extension cap directly below the backside gate extension”.
Chen ‘733 teaches a backside gate extension cap (Fig. 12B, (243); [0036]) directly below the backside gate extension (204; [0019]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Xie ‘033 by having a backside gate extension cap directly below the backside gate extension in order to provide the needed performance boost as well as reducing power consumption (see para. [0016]) as suggested by Chen ‘733.
Regarding Claims 5 and 17, Chen ‘733 teaches a backside S/D dielectric (Fig. 14F, (274); [0051]) below the first S/D (260; [0038]), wherein the backside S/D dielectric and the backside gate extension cap comprise different dielectric materials (see para. [0036]).
Further, it has been held to be within the general skill of a worker in the art to select the backside S/D dielectric and the backside gate extension cap comprise different dielectric materials on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to select the backside S/D dielectric and the backside gate extension cap comprise different dielectric materials when this allows a good flow with the other steps in the fabrication process.
Regarding Claim 7, Xie ‘033 teaches a spacer (136; [0070]) between the S/D contact and the offset gate contact.
Chen ‘733 teaches a backside gate extension cap (Fig. 12B, (243); [0036]).
Regarding Claim 19, Xie ‘033 teaches a bottom spacer (136; [0070]) between the S/D contact and the offset gate contact.
Chen ‘733 teaches a backside gate extension cap (Fig. 12B, (243); [0036]).
Regarding Claim 20, Xie ‘033 teaches a first level signal line (1446; [0063]); and a first level power line (1448; [0063]).
Xie ‘033 and Chen ‘733 are shown to teach all the features of the claim with the exception of explicitly the features: “a tip-to-tip distance between the first level signal line and the first level power line is greater than a width of the first gate”.
However, it has been held to be within the general skill of a worker in the art to select a tip-to-tip distance between the first level signal line and the first level power line is greater than a width of the first gate on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
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A person of ordinary skills in the art is motivated to select a tip-to-tip distance between the first level signal line and the first level power line is greater than a width of the first gate when this allows a good flow with the other steps in the fabrication process.
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraph numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor devices:
Wei et al. (US 2023/0207465 A1)
Su et al. (US 2022/0310804 A1)
Mishra et al. (US 2021/0398977 A1)
Liang et al. (US 11,081,559 B1)
For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T TRAN whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893
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