DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Claims 10-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group (II), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 22 December 2025. Applicant’s election without traverse of Group I in the reply filed on 22 December 2025 is acknowledged. Claim and Specification Status The Examiner acknowledges the cancellation of claims 10-15 and the addition of new claims 21-26 as presented by the Applicant in the response filed 22 December 2025. Information Disclosure Statement The information disclosure statement (IDS) submitted on 18 September 2023 has been considered by the examiner and made of record in the application file. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3, 6-9, and 16-22 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chih - Hao Chen et al. (2014/0322866 A1; hereinafter “Chen”) . Regarding Claim 1 , Chen teaches an integrated circuit, comprising: a semiconductor die (210, Fig. 3, para [0027] describes a semiconductor die 210) having a first surface (FF, annotated Fig. 3 depicts a first surface FF), a second surface opposite the first surface (SF, annotated Fig. 3 depicts a second surface SF which can be seen opposite the first surface FF), and a third surface disposed between the first surface and the second surface such that the semiconductor die has a stairstep configuration (TF, annotated Fig. 3 depicts a third surface TF disposed between the first surface FF and second surface SF resulting in a staircase configuration of the semiconductor die 210 as described in para [0028]); and a plurality of connection points extending from the first surface of the semiconductor die (112, 114 and 116, Fig. 1, para [0025] describes interconnection bumps 112, 114 and 116 extending from the first surface FF as shown in annotated Fig. 3), the plurality of connection points communicatively coupling the integrated circuit to a substrate of the integrated circuit (302, Fig. 3, para [0029] and para [0030] describes wherein the semiconductor die 210 is mounted to a substrate 310 through interconnection bumps 112, 114 and 116 further coupling them communicatively). Regarding Claim 2 , Chen teaches the integrated circuit of claim 1, further comprising an underfill material provided between the first surface of the semiconductor die and the substrate (402, Fig. 4, para [0030] describes an underfill material 402 formed in the gap between the semiconductor die 210 and substrate 302). Regarding Claim 3 , Chen teaches the integrated circuit of claim 2, wherein the stairstep configuration of the semiconductor die prevents the underfill material from reaching the second surface of the semiconductor die (para [0031] describes wherein the height of the underfill material layer 402 is controlled by the step recess 404 creating a ceiling for the underfill material 402 preventing the underfill material from reaching the second surface SF). Regarding Claim 6 , Chen teaches the integrated circuit of claim 1, wherein the stairstep configuration is formed during a multi-cut wafer dicing process (Fig. 2, para [0028] describes a two-step dicing process) in which: a first cut is made using a first cutting device having a first width (Fig. 2, para [0027] describes a first cut being made using a first dicing saw with a thickness in a range about 40 μm to about 400 μm ); and a second cut is made using a second cutting device having second width (Fig. 2, para [0027] describes a second cut being made using a second dicing saw with a thin blade wherein a resulting thin blade would have a second width). Regarding Claim 7 , Chen teaches the integrated circuit of claim 6, wherein at least one of the first cutting device and the second cutting device is a saw (Fig. 2, para [0027] describes a first cut or a second cut being made using a first dicing saw or a second dicing saw). Regarding Claim 8 , Chen teaches the integrated circuit of claim 6, wherein at least one of the first cutting device and the second cutting device is a laser (Fig. 2, para [0028] describes wherein the step recesses can be created by using other dicing tools such as laser dicing tools). Regarding Claim 9 , Chen teaches the integrated circuit of claim 6, wherein the first cut extends a first depth through a wafer associated with the integrated circuit (a1, Fig. 2, para [0026] describes a first vertical recess depth a1 from the first cut is in a range from about 20 μm to about 300 μm ) and the second cut extents a second depth through the wafer associated with the integrated circuit (210, Fig. 2, para [0027] describes wherein the second cut extends through the thickness of the wafer 102 associated with the semiconductor die 210 wherein the semiconductor die may have a thickness in a range from about 20 μm to about 500 μm as described in para [0033]). Regarding Claim 16 , Chen teaches an integrated circuit, comprising: a semiconductor die (210, Fig. 3, para [0027] describes a semiconductor die 210) having: a first surface (FF, annotated Fig. 3 depicts a first surface FF); a second surface opposite the first surface (SF, annotated Fig. 3 depicts a second surface SF which can be seen opposite the first surface FF); and a third surface disposed between the first surface and the second surface (TF, annotated Fig. 3 depicts a third surface TF disposed between the first surface FF and second surface SF) wherein the third surface is formed from a first cutting means having a first width (Fig. 2, para [0027] describes a first cut being made using a first dicing saw with a thickness in a range about 40 μm to about 400 μm to form a trench 201 from which the third surface TF is formed) and a second cutting means having a second width (Fig. 2, para [0027] describes a second cut being made using a second dicing saw with a thin blade wherein a resulting thin blade would have a second width to form an edge to the third surface TF), wherein the first cutting means forms a first cut partially though a wafer associated with the semiconductor die (a1, Fig. 2, para [0026] describes a first vertical recess depth a1 from the first cut is in a range from about 20 μm to about 300 μm partially through the wafer 102) and wherein the second cutting means forms a second cut within the first cut such that the semiconductor die has a stairstep configuration (210, Fig. 2, para [0027] describes wherein the second cut extends through the thickness of the wafer 102 associated with the semiconductor die 210 wherein the second cut occurs in the trench 201 formed form the first cut resulting in a stairstep configuration as described in para [0028]). Regarding Claim 17 , Chen teaches the integrated circuit of claim 16, further comprising a plurality of connection means extending from the first surface of the semiconductor die (112, 114 and 116, Fig. 1, para [0025] describes interconnection bumps 112, 114 and 116 extending from the first surface FF as shown in annotated Fig. 3), the plurality of connection means communicatively coupling the semiconductor die to a substrate of the integrated circuit (302, Fig. 3, para [0029] and para [0030] describes wherein the semiconductor die 210 is mounted to a substrate 310 through interconnection bumps 112, 114 and 116 further coupling them communicatively). Regarding Claim 18 , Chen teaches the integrated circuit of claim 17, wherein the stairstep configuration of the semiconductor die prevents an underfill material (402, Fig. 4, para [0030] describes an underfill material 402 formed in the gap between the semiconductor die 210 and substrate 302) from reaching the second surface of the semiconductor die when the underfill material is applied to the substrate (para [0031] describes wherein the height of the underfill material layer 402 is controlled by the step recess 404 creating a ceiling for the underfill material 402 preventing the underfill material from reaching the second surface SF). Regarding Claim 19 , Chen teaches the integrated circuit of claim 16, wherein at least one of the first cutting means and the second cutting means is a saw (Fig. 2, para [0027] describes a first cut or a second cut being made using a first dicing saw or a second dicing saw). Regarding Claim 20 , Chen teaches the integrated circuit of claim 16, wherein at least one of the first cutting means and the second cutting means is a laser (Fig. 2, para [0028] describes wherein the step recesses can be created by using other dicing tools such as laser dicing tools). Regarding Claim 21 , Chen teaches a semiconductor die, comprising: a first surface (FF, annotated Fig. 3 depicts a first surface FF); a second surface opposite the first surface (SF, annotated Fig. 3 depicts a second surface SF which can be seen opposite the first surface FF); and a third surface disposed between the first surface and the second surface such that the semiconductor die has a stairstep configuration (TF, annotated Fig. 3 depicts a third surface TF disposed between the first surface FF and second surface SF resulting in a staircase configuration of the semiconductor die 210 as described in para [0028]). Regarding Claim 22 , Chen teaches the semiconductor die of claim 21, wherein the first surface has a first width (FW, annotated Fig. 2 depicts a first width which is a result of reducing a width of the wafer 102 by a width b1 in a range from 20 μm to about 200 μm as described in para [0026]) and the second surface has a second width that is greater than the first width (SW, annotated Fig. 2 depicts wherein a second width is a width of the wafer 102 that has not been reduced by a first cutting step which reduces the width of the wafer 102 by a width b1 in a range from 20 μm to about 200 μm as described in para [0026] such that the second width SW is at least 20 μm to about 200 μm greater than the first width FW). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 4-5 and 23-2 5 are rejected under 35 U.S.C. 103 as being unpatentable over Chih - Hao Chen et al. (2014/0322866 A1; hereinafter “Chen”) in view of Seung Hwan Kim et al. (US 2022/0208648 A1; hereinafter “Kim”) . Regarding Claim 4 , Chen discloses all the limitations of claim 1. Chen discloses the integrated circuit of claim 1, wherein the semiconductor die is a first semiconductor die (210, Fig. 4, para [0027] describes a first semiconductor die 210) and wherein the integrated circuit further comprises a second semiconductor die coupled to first semiconductor die (220, Fig. 4, para [0029] describes a second semiconductor die 220 wherein the first semiconductor die 210 and second semiconductor die 220 are coupled to each other through package substrate 310). Chen fails to explicitly disclose the integrated circuit of claim 1, wherein the semiconductor die is a first semiconductor die and wherein the integrated circuit further comprises a second semiconductor die coupled to the second surface of the first semiconductor die . However, Kim teaches a similar integrated circuit wherein the semiconductor die is a first semiconductor die (100, Fig. 8, para [0097] describes a first semiconductor chip 100) and wherein the integrated circuit further comprises a second semiconductor die coupled to the second surface of the first semiconductor die ( 200, Fig. 8, para [0097] describes a second semiconductor chip 200 which is coupled to a second surface SF2 of the first semiconductor die 100 ). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chen with Kim to further disclose a n integrated circuit device comprising a first semiconductor device and a second semiconductor device coupled to the first semiconductor device through a second surface in order to provide the advantage of increasing a gap between bonding structures in order to reduce or prevent the formation of voids in a gap-fill or underfill material between the bonding structures between chips and preventing procedural defects resulting from the formation of voids (Kim, para [0103]). Regarding Claim 5 , the combination of Chen and Kim discloses the integrated circuit of claim 4, wherein the second semiconductor die is a memory die ( Kim, 200, Fig. 8, para [0046] describes wherein the second semiconductor die may be a same type as the first semiconductor die 100 wherein para [0028] describes the first semiconductor die 100 may be a volatile or non-volatile memory chip ). Regarding Claim 23 , Chen discloses all the limitations of claim 21. Chen fails to explicitly disclose the semiconductor die of claim 21, wherein the semiconductor die is a NAND memory die . However, Kim discloses a similar semiconductor die, wherein the semiconductor die is a NAND memory die ( 100, Fig. 8, para [0028] describes wherein a first semiconductor die 100 may be a volatile or non-volatile memory chip such as NAND flash ). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chen with Kim to further disclose an semiconductor die wherein a semiconductor die is a NAND memory die in order to provide the well-known advantage of enabling a flip-chip semiconductor d ie structure configuration to be used in a plurality of different device types such as a NAND memory structure or an NMOS or PMOS semiconductor device reducing manufacturing cost and simplifying manufacturing steps for multiple different devices. Regarding Claim 24 , Chen discloses all the limitations of claim 21. Chen discloses the semiconductor die of claim 2 1, wherein the stairstep configuration (404, Fig. 4, para [0031] describes a step recess 404 comprising the stairstep configuration) faces a substrate (302, Fig. 4, para [0029] describes a package substrate 310 which faces stairstep configuration 404) on which the semiconductor die is coupled when the semiconductor die is coupled to the substrate ( 210 and 310, Fig. 3 and Fig. 4, para [0029] describes wherein semiconductor die 210 is coupled to the substrate 310 ). Chen fails to explicitly disclose the semiconductor die of claim 2 1, wherein the stairstep configuration faces a printed circuit board on which the semiconductor die is coupled when the semiconductor die is coupled to the printed circuit board . However, Kim teaches a similar semiconductor die, wherein the stairstep configuration faces a printed circuit board (800, Fig. 8, para [0098] describes a base layer 800 that may be a substrate such as a printed circuit board wherein upon combining the printed circuit board of Kim with Chen, the stairstep configuration 404 of Chen would face the printed circuit board 800) on which the semiconductor die is coupled when the semiconductor die is coupled to the printed circuit board ( 100 and 800, Fig. 8, para [009] describes coupling the semiconductor die 100 to the printed circuit board 800 ). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chen with Kim to further disclose an semiconductor die wherein a substrate may be a printed circuit board wherein a semiconductor die may be coupled to the printed circuit board in order to provide the advantage of enabling a semiconductor die to be further connected to external constituent elements so that read and write operations may be performed on the semiconductor die comprising a memory chip (Kim, para [0098]). Regarding Claim 25 , the combination of Chen and Kim discloses the semiconductor die of claim 24, wherein an underfill material contacts one or more of the first surface and the third surface (Chen, 402, Fig. 4, para [0030] describes an underfill material 402 formed in the gap between the semiconductor die 210 and substrate 302 and contacting the first surface FF and third surface TF of annotated Fig. 3) but is prevented from contacting the second surface as a result of the stairstep configuration (Chen, para [0031] describes wherein the height of the underfill material layer 402 is controlled by the step recess 404 creating a ceiling for the underfill material 402 preventing the underfill material from reaching the second surface SF). Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Chih - Hao Chen et al. (2014/0322866 A1; hereinafter “Chen”) in view of the following arguments: Regarding Claim 26 , Chen discloses all the limitations of claim 21. Chen fails to explicitly disclose the semiconductor die of claim 21, wherein the third surface has a third width that is less than the first width and the second width . However, Chen discloses wherein a step recess length which comprises the length of the third surface (TF from annotated Fig. 3) may be in a range from about a range from 20 μm to about 200 μm (Chen, para [0026]). Chen further discloses in para [0027] and Fig. 2 wherein the step recess length comprising the third surface length is a result of a trench cut into the substrate of the semiconductor die. An opposite side of the substrate of the semiconductor die comprising the second surface (SF from annotated Fig. 3) is not subject to the first trench cut process. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different lengths of a third surface from a range of 20 μm to about 200 μm wherein a semiconductor substrate comprising a first and second surface must comprise a first and a second width of at least 200 μm in order to form a trench that may be up to 200 μm in length, therefore in trying a trench within the discloses range of approximately 20 μm in length resulting in a third surface of 20 μm in length would be less than a first surface comprising a first width of at least 200 μm minus 20 μm , or at least 180 μm and a second surface comprising a second width of at least 200 μm would result in a third surface comprising a third width that is less than a first width and a second width in order to provide the advantage of reducing a size of a trench feature to a minimal value needed to prevent an underfill material from reaching a second surface providing for a manufacturing process that may result in a smaller semiconductor die increasing the yield of semiconductor dies cut from a wafer and lowering manufacturing cost (see MPEP 2144.04 (IV)(A) and MPEP 2144.05 (II)(A)(B)). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT ALEXANDER M MILLER whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-6051 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday - Thursday 7:00 am - 5:00 pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Julio Maldonado can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571(272)-1864 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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