DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to claims 1, 5, 6, 9, 16 and 21-26 in the Applicant’s response dated 22 June 2026. The claim amendments have been addressed below.
The Examiner acknowledges the addition of new claims 27-31 in the Applicant’s response dated 22 June 2026. The new claims have been addressed below.
The Examiner acknowledges the cancellation of claims 2-4 and 17-18 in the Applicant’s response dated 22 June 2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “one or more bond wires coupling the second semiconductor die to the substrate”, as described in claim 31, and the “molding compound encapsulating the first semiconductor die and the second semiconductor die”, as described in claim 29, must be shown or the features canceled from the claims. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-9, 16, 19-26 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Chih-Hao Chen et al. (2014/0322866 A1; hereinafter “Chen”) in view of Seung Hwan Kim et al. (US 2022/0208648 A1; hereinafter “Kim”).
Regarding Claim 1, Chen teaches an integrated circuit, comprising:
a first semiconductor die (210, Fig. 3, para [0027] describes a semiconductor die 210) having a first surface (FF, annotated Fig. 3 depicts a first surface FF), a second surface opposite the first surface (SF, annotated Fig. 3 depicts a second surface SF which can be seen opposite the first surface FF), and a third surface disposed between the first surface and the second surface such that the first semiconductor die has a stairstep configuration (TF, annotated Fig. 3 depicts a third surface TF disposed between the first surface FF and second surface SF resulting in a staircase configuration of the semiconductor die 210 as described in para [0028]);
a plurality of connection points extending from the first surface of the first semiconductor die (112, 114 and 116, Fig. 1, para [0025] describes interconnection bumps 112, 114 and 116 extending from the first surface FF as shown in annotated Fig. 3), the plurality of connection points communicatively coupling the first semiconductor die to a substrate of the integrated circuit (302, Fig. 3, para [0029] and para [0030] describes wherein the semiconductor die 210 is mounted to a substrate 310 through interconnection bumps 112, 114 and 116 further coupling them communicatively);
an underfill material provided between the first surface of the first semiconductor die and the substrate (402, Fig. 4, para [0030] describes an underfill material 402 formed in the gap between the semiconductor die 210 and substrate 302), wherein the stairstep configuration of the first semiconductor die prevents the underfill material from reaching the second surface of the first semiconductor die (para [0031] describes wherein the height of the underfill material layer 402 is controlled by the step recess 404 creating a ceiling for the underfill material 402 preventing the underfill material from reaching the second surface SF).
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Chen fails to explicitly disclose a second semiconductor die coupled to the second surface of the first semiconductor die.
However, Kim teaches a similar integrated circuit wherein the semiconductor die is a first semiconductor die (100, Fig. 8, para [0097] describes a first semiconductor chip 100) and wherein the integrated circuit further comprises a second semiconductor die coupled to the second surface of the first semiconductor die (200, Fig. 8, para [0097] describes a second semiconductor chip 200 which is coupled to a second surface SF2 of the first semiconductor die 100).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chen with Kim to further disclose an integrated circuit device comprising a first semiconductor device and a second semiconductor device coupled to the first semiconductor device through a second surface in order to provide the advantage of increasing a gap between bonding structures in order to reduce or prevent the formation of voids in a gap-fill or underfill material between the bonding structures between chips and preventing procedural defects resulting from the formation of voids (Kim, para [0103]) and to further provide the well-known advantage of increasing a density of dies in a vertical direction thus increasing manufacturing throughput and keeping up with Moore’s Law.
Regarding Claim 5, the combination of Chen and Kim discloses the integrated circuit of claim 1, wherein the second semiconductor die is a memory die (Kim, 200, Fig. 8, para [0046] describes wherein the second semiconductor die may be a same type as the first semiconductor die 100 wherein para [0028] describes the first semiconductor die 100 may be a volatile or non-volatile memory chip).
Regarding Claim 6, the combination of Chen and Kim teaches the integrated circuit of claim 1, wherein the stairstep configuration is formed during a multi-cut wafer dicing process (Chen, Fig. 2, para [0028] describes a two-step dicing process) in which:
a first cut is made using a first cutting device having a first width (Chen, Fig. 2, para [0027] describes a first cut being made using a first dicing saw with a thickness in a range about 40 μm to about 400 μm); and
a second cut is made using a second cutting device having second width (Chen, Fig. 2, para [0027] describes a second cut being made using a second dicing saw with a thin blade wherein a resulting thin blade would have a second width).
Regarding Claim 7, the combination of Chen and Kim teaches the integrated circuit of claim 6, wherein at least one of the first cutting device and the second cutting device is a saw (Chen, Fig. 2, para [0027] describes a first cut or a second cut being made using a first dicing saw or a second dicing saw).
Regarding Claim 8, the combination of Chen and Kim teaches the integrated circuit of claim 6, wherein at least one of the first cutting device and the second cutting device is a laser (Chen, Fig. 2, para [0028] describes wherein the step recesses can be created by using other dicing tools such as laser dicing tools).
Regarding Claim 9, the combination of Chen and Kim teaches the integrated circuit of claim 6, wherein the first cut extends a first depth through a wafer associated with the integrated circuit (Chen, a1, Fig. 2, para [0026] describes a first vertical recess depth a1 from the first cut is in a range from about 20 μm to about 300 μm) and the second cut extends a second depth through the wafer associated with the integrated circuit (Chen, 210, Fig. 2, para [0027] describes wherein the second cut extends through the thickness of the wafer 102 associated with the semiconductor die 210 wherein the semiconductor die may have a thickness in a range from about 20 μm to about 500 μm as described in para [0033]).
Regarding Claim 16, Chen teaches an integrated circuit, comprising:
a first semiconductor die (210, Fig. 3, para [0027] describes a semiconductor die 210) having:
a first surface (FF, annotated Fig. 3 depicts a first surface FF);
a second surface opposite the first surface (SF, annotated Fig. 3 depicts a second surface SF which can be seen opposite the first surface FF); and
a third surface disposed between the first surface and the second surface (TF, annotated Fig. 3 depicts a third surface TF disposed between the first surface FF and second surface SF) wherein the third surface is formed from a first cutting means having a first width (Fig. 2, para [0027] describes a first cut being made using a first dicing saw with a thickness in a range about 40 μm to about 400 μm to form a trench 201 from which the third surface TF is formed) and a second cutting means having a second width (Fig. 2, para [0027] describes a second cut being made using a second dicing saw with a thin blade wherein a resulting thin blade would have a second width to form an edge to the third surface TF), wherein the first cutting means forms a first cut partially through a wafer associated with the first semiconductor die (a1, Fig. 2, para [0026] describes a first vertical recess depth a1 from the first cut is in a range from about 20 μm to about 300 μm partially through the wafer 102) and wherein the second cutting means forms a second cut within the first cut such that the first semiconductor die has a stairstep configuration (210, Fig. 2, para [0027] describes wherein the second cut extends through the thickness of the wafer 102 associated with the semiconductor die 210 wherein the second cut occurs in the trench 201 formed form the first cut resulting in a stairstep configuration as described in para [0028]);
a plurality of connection means extending from the first surface of the first semiconductor die (112, 114 and 116, Fig. 1, para [0025] describes interconnection bumps 112, 114 and 116 extending from the first surface FF as shown in annotated Fig. 3) and communicatively coupling the first semiconductor die to a substrate of the integrated circuit (302, Fig. 3, para [0029] and para [0030] describes wherein the semiconductor die 210 is mounted to a substrate 310 through interconnection bumps 112, 114 and 116 further coupling them communicatively);
an underfill material provided between the first surface of the first semiconductor die and the substrate (402, Fig. 4, para [0030] describes an underfill material 402 formed in the gap between the semiconductor die 210 and substrate 302), wherein the stairstep configuration of the first semiconductor die prevents the underfill material from reaching the second surface of the first semiconductor die when the underfill material is applied to the substrate (para [0031] describes wherein the height of the underfill material layer 402 is controlled by the step recess 404 creating a ceiling for the underfill material 402 preventing the underfill material from reaching the second surface SF when the underfill material 402 is applied to the substrate 302).
Chen fails to explicitly disclose a second semiconductor die coupled to the second surface of the first semiconductor die.
However, Kim teaches a similar integrated circuit wherein the semiconductor die is a first semiconductor die (100, Fig. 8, para [0097] describes a first semiconductor chip 100) and wherein the integrated circuit further comprises a second semiconductor die coupled to the second surface of the first semiconductor die (200, Fig. 8, para [0097] describes a second semiconductor chip 200 which is coupled to a second surface SF2 of the first semiconductor die 100).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chen with Kim to further disclose an integrated circuit device comprising a first semiconductor device and a second semiconductor device coupled to the first semiconductor device through a second surface in order to provide the advantage of increasing a gap between bonding structures in order to reduce or prevent the formation of voids in a gap-fill or underfill material between the bonding structures between chips and preventing procedural defects resulting from the formation of voids (Kim, para [0103]) and to further provide the well-known advantage of increasing a density of dies in a vertical direction thus increasing manufacturing throughput and keeping up with Moore’s Law.
Regarding Claim 19, the combination of Chen and Kim teaches the integrated circuit of claim 16, wherein at least one of the first cutting means and the second cutting means is a saw (Chen, Fig. 2, para [0027] describes a first cut or a second cut being made using a first dicing saw or a second dicing saw).
Regarding Claim 20, the combination of Chen and Kim teaches the integrated circuit of claim 16, wherein at least one of the first cutting means and the second cutting means is a laser (Chen, Fig. 2, para [0028] describes wherein the step recesses can be created by using other dicing tools such as laser dicing tools).
Regarding Claim 21, Chen teaches an integrated circuit, comprising:
a first semiconductor die (210, Fig. 3, para [0027] describes a semiconductor die 210) having:
a first surface (FF, annotated Fig. 3 depicts a first surface FF);
a second surface opposite the first surface (SF, annotated Fig. 3 depicts a second surface SF which can be seen opposite the first surface FF); and
a third surface disposed between the first surface and the second surface such that the first semiconductor die has a stairstep configuration (TF, annotated Fig. 3 depicts a third surface TF disposed between the first surface FF and second surface SF resulting in a staircase configuration of the semiconductor die 210 as described in para [0028]);
a substrate (302, Fig. 3, para [0030] describes a substrate 302);
an underfill material provided between the first surface of the first semiconductor die and the substrate (402, Fig. 4, para [0030] describes an underfill material 402 formed in the gap between the semiconductor die 210 and substrate 302), the stairstep configuration of the first semiconductor die preventing the underfill material from reaching the second surface of the first semiconductor die (para [0031] describes wherein the height of the underfill material layer 402 is controlled by the step recess 404 creating a ceiling for the underfill material 402 preventing the underfill material from reaching the second surface SF).
Chen fails to explicitly disclose a second semiconductor die coupled to the second surface of the first semiconductor die.
However, Kim teaches a similar integrated circuit wherein the semiconductor die is a first semiconductor die (100, Fig. 8, para [0097] describes a first semiconductor chip 100) and wherein the integrated circuit further comprises a second semiconductor die coupled to the second surface of the first semiconductor die (200, Fig. 8, para [0097] describes a second semiconductor chip 200 which is coupled to a second surface SF2 of the first semiconductor die 100).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chen with Kim to further disclose an integrated circuit device comprising a first semiconductor device and a second semiconductor device coupled to the first semiconductor device through a second surface in order to provide the advantage of increasing a gap between bonding structures in order to reduce or prevent the formation of voids in a gap-fill or underfill material between the bonding structures between chips and preventing procedural defects resulting from the formation of voids (Kim, para [0103]) and to further provide the well-known advantage of increasing a density of dies in a vertical direction thus increasing manufacturing throughput and keeping up with Moore’s Law.
Regarding Claim 22, the combination of Chen and Kim teaches the integrated circuit of claim 21, wherein the first surface of the first semiconductor die has a first width (Chen, FW, annotated Fig. 2 depicts a first width which is a result of reducing a width of the wafer 102 by a width b1 in a range from 20 μm to about 200 μm as described in para [0026]) and the second surface of the first semiconductor die has a second width that is greater than the first width (Chen, SW, annotated Fig. 2 depicts wherein a second width is a width of the wafer 102 that has not been reduced by a first cutting step which reduces the width of the wafer 102 by a width b1 in a range from 20 μm to about 200 μm as described in para [0026] such that the second width SW is at least 20 μm to about 200 μm greater than the first width FW).
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Regarding Claim 23, the combination of Chen and Kim discloses all the limitations of claim 21.
Chen fails to explicitly disclose the integrated circuit of claim 21, wherein the semiconductor die is a NAND memory die.
However, Kim discloses a similar integrated circuit, wherein the first semiconductor die is a NAND memory die (100, Fig. 8, para [0028] describes wherein a first semiconductor die 100 may be a volatile or non-volatile memory chip such as NAND flash).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chen with Kim to further disclose an integrated circuit wherein a semiconductor die is a NAND memory die in order to provide the well-known advantage of enabling a flip-chip semiconductor die structure configuration to be used in a plurality of different device types such as a NAND memory structure or an NMOS or PMOS semiconductor device reducing manufacturing cost and simplifying manufacturing steps for multiple different devices.
Regarding Claim 24, the combination of Chen and Kim discloses all the limitations of claim 21.
Chen discloses the integrated circuit of claim 21, wherein the stairstep configuration (404, Fig. 4, para [0031] describes a step recess 404 comprising the stairstep configuration) faces a substrate (302, Fig. 4, para [0029] describes a package substrate 310 which faces stairstep configuration 404) when the first semiconductor die is coupled to the substrate (210 and 310, Fig. 3 and Fig. 4, para [0029] describes wherein semiconductor die 210 is coupled to the substrate 310).
Chen fails to explicitly disclose the integrated circuit of claim 21, wherein the stairstep configuration faces a printed circuit board when the first semiconductor die is coupled to the printed circuit board.
However, Kim teaches a similar integrated circuit, wherein the stairstep configuration faces a printed circuit board (800, Fig. 8, para [0098] describes a base layer 800 that may be a substrate such as a printed circuit board wherein upon combining the printed circuit board of Kim with Chen, the stairstep configuration 404 of Chen would face the printed circuit board 800) when the first semiconductor die is coupled to the printed circuit board (100 and 800, Fig. 8, para [009] describes coupling the semiconductor die 100 to the printed circuit board 800).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chen with Kim to further disclose an integrated circuit wherein a substrate may be a printed circuit board wherein an integrated circuit may be coupled to the printed circuit board in order to provide the advantage of enabling a semiconductor die to be further connected to external constituent elements so that read and write operations may be performed on the semiconductor die comprising a memory chip (Kim, para [0098]).
Regarding Claim 25, the combination of Chen and Kim discloses the integrated circuit of claim 24, wherein the underfill material contacts one or more of the first surface and the third surface of the first semiconductor die (Chen, 402, Fig. 4, para [0030] describes an underfill material 402 formed in the gap between the first semiconductor die 210 and substrate 302 and contacting the first surface FF and third surface TF of annotated Fig. 3) but is prevented from contacting the second surface of the first semiconductor die as a result of the stairstep configuration (Chen, para [0031] describes wherein the height of the underfill material layer 402 is controlled by the step recess 404 creating a ceiling for the underfill material 402 preventing the underfill material from reaching the second surface SF).
Regarding Claim 26, the combination of Chen and Kim discloses all the limitations of claim 21.
Chen and Kim fail to explicitly disclose the integrated circuit of claim 21, wherein the third surface of the first semiconductor die has a third width that is less than the first width and the second width.
However, Chen discloses wherein a step recess length which comprises the length of the third surface of the first semiconductor die (TF from annotated Fig. 3) may be in a range from about a range from 20 μm to about 200 μm (Chen, para [0026]). Chen further discloses in para [0027] and Fig. 2 wherein the step recess length comprising the third surface length of the first semiconductor die is a result of a trench cut into the substrate of the first semiconductor die. An opposite side of the substrate of the first semiconductor die comprising the second surface (SF from annotated Fig. 3) is not subject to the first trench cut process.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different lengths of a third surface from a range of 20 μm to about 200 μm wherein a semiconductor substrate comprising a first and second surface must comprise a first and a second width of at least 200 μm in order to form a trench that may be up to 200 μm in length, therefore in trying a trench within the discloses range of approximately 20 μm in length resulting in a third surface of 20 μm in length would be less than a first surface comprising a first width of at least 200 μm minus 20 μm, or at least 180 μm and a second surface comprising a second width of at least 200 μm would result in a third surface comprising a third width that is less than a first width and a second width in order to provide the advantage of reducing a size of a trench feature to a minimal value needed to prevent an underfill material from reaching a second surface providing for a manufacturing process that may result in a smaller semiconductor die increasing the yield of semiconductor dies cut from a wafer and lowering manufacturing cost (see MPEP 2144.04 (IV)(A) and MPEP 2144.05 (II)(A)(B)).
Regarding Claim 29, the combination of Chen and Kim teaches the integrated circuit of claim 21, further comprising a molding compound encapsulating the first semiconductor die and the second semiconductor die (Kim, 820, Fig. 8, para [0102] describes a molding layer 820 encapsulating the first semiconductor die 100 and the second semiconductor die 200).
Claims 27, 28 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Chih-Hao Chen et al. (2014/0322866 A1; hereinafter “Chen”) in view of Seung Hwan Kim et al. (US 2022/0208648 A1; hereinafter “Kim”) and in further view of Hock Chuan Tan et al. (US 2003/0162325 A1; hereinafter “Tan”).
Regarding Claim 27, the combination of Chen and Kim discloses all the limitations of claim 21,
Chen and Kim fail to explicitly disclose the integrated circuit of claim 21, wherein the second semiconductor die is coupled to the second surface of the first semiconductor die by an adhesive.
However, Tan teaches a similar integrated circuit, wherein the second semiconductor die (46’’’, Fig. 25, para [0078] describes a second semiconductor die 46’’’’) is coupled to the second surface of the first semiconductor die by an adhesive (46’’’, 42’’’’ and 66’’’’, Fig. 25, para [0078] describes a second semiconductor die 46’’’’ coupled to an upper surface of a first semiconductor die 42’’’’ by an adhesive element 66’’’’ wherein the upper surface of the first semiconductor die 42’’’’ is a second surface and a bottom surface is a first surface).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chen and Kim with Tan to further disclose an integrated circuit wherein a second semiconductor die is coupled to a second surface of a first semiconductor die by an adhesive in order to provide the well-known advantage of providing an element securely fastening two dies together to prevent the dies from separating during subsequent manufacturing processes which may result in deterioration of device performance and cause undesirable device characteristics.
Regarding Claim 28, the combination of Chen, Kim and Tan teaches the integrated circuit of claim 27, wherein the second semiconductor die (Kim, 200, Fig. 8, para [0097] describes the second semiconductor chip 200 which is coupled to a second surface SF2 of the first semiconductor die 100) is positionable at any location on the second surface of the first semiconductor die as a result of the stairstep configuration preventing the underfill material from reaching the second surface (Chen, 210 and TF, annotated Fig. 3 depicts the third surface TF disposed between the first surface FF and second surface SF resulting in the staircase configuration preventing the underfill material from reaching the second surface SF of the first semiconductor die 210 wherein as a result the second semiconductor die 200 of Kim would be positionable at any location on the second surface SF of the first semiconductor die 210 of Chen).
Regarding Claim 30, the combination of Chen and Kim discloses all the limitations of claim 1,
Chen and Kim fail to explicitly disclose the integrated circuit of claim 1, wherein the second semiconductor die is coupled to the second surface of the first semiconductor die by an adhesive.
However, Tan teaches a similar integrated circuit, wherein the second semiconductor die (46’’’, Fig. 25, para [0078] describes a second semiconductor die 46’’’’) is coupled to the second surface of the first semiconductor die by an adhesive (46’’’, 42’’’’ and 66’’’’, Fig. 25, para [0078] describes a second semiconductor die 46’’’’ coupled to an upper surface of a first semiconductor die 42’’’’ by an adhesive element 66’’’’ wherein the upper surface of the first semiconductor die 42’’’’ is a second surface and a bottom surface is a first surface).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chen and Kim with Tan to further disclose an integrated circuit wherein a second semiconductor die is coupled to a second surface of a first semiconductor die by an adhesive in order to provide the well-known advantage of providing an element securely fastening two dies together to prevent the dies from separating during subsequent manufacturing processes which may result in deterioration of device performance and cause undesirable device characteristics.
Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Chih-Hao Chen et al. (2014/0322866 A1; hereinafter “Chen”) in view of Seung Hwan Kim et al. (US 2022/0208648 A1; hereinafter “Kim”) and in further view of Pezhman Monadgemi (US 2022/0208728 A1; hereinafter “Monadgemi”).
Regarding Claim 31, the combination of Chen and Kim discloses all the limitations of claim 1,
Chen and Kim fail to explicitly disclose integrated circuit of claim 1, further comprising one or more bond wires coupling the second semiconductor die to the substrate.
However, Monadgemi teaches a similar integrated circuit further comprising one or more bond wires coupling the second semiconductor die to the substrate (132, 130a and 130b, para [0016] describes a first semiconductor die 130a and a second semiconductor die 130b coupled to a substrate 110 by one or more wire bonds 132).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chen and Kim with Monadgemi to further disclose an integrated circuit comprising one or more bond wires coupling the second semiconductor die to the substrate in order to provide the advantage of electrically connecting a plurality of dies to a substrate enabling the plurality of semiconductor dies to be electrically connected (Monadgemi, para [0016]) which further provides the well-known advantage of increasing memory capacity in an integrated circuit by enabling multiple memory dies to be stacked vertically and electrically connected.
Response to Arguments
Applicant's arguments filed 22 June 2026 have been fully considered but they are not persuasive.
The Applicant argues on page 8, lines 27-29 and page 9, lines 1-26 of the remarks that Kim cannot be combined with Chen in the manner suggested in the Office Action because Chen’s semiconductor dies lack structural features that are necessary for the vertical stacking of chips described in Kim and furthermore that a person of ordinary skill in the art following Chen’s disclosure would not arrive at the structure where a second semiconductor die is coupled to the second surface of the first semiconductor die. The Examiner respectfully disagrees. Chen describes in para [0022] the substrate of the first semiconductor die may further comprise a variety of electrical circuits wherein the electrical circuits formed on the substrate may be any type of circuitry suitable for a particular application. Through silicon vias and/or interconnection bumps on a second surface including the substrate of the first semiconductor die may include a type of electrical circuit suitable for mounting a second semiconductor die onto the second surface of the first semiconductor die. Furthermore, Applicant’s argument that a person of ordinary skill in the art following Chen’s disclosure would not arrive at the structure where a second semiconductor die is coupled to the second surface of the first semiconductor die is a mere allegation not supported by evidence. It would be obvious to a person of ordinary skill in the art to attach a second semiconductor die to a first semiconductor die in a vertical direction as compared to a horizontal direction in order increase a density of dies that may be required when integrating a plurality of dies in a memory device to help throughput and to enable the memory structure to keep up with Moore’s Law.
The Applicant argues on page 9, lines 27-30 and page 10, lines 1-21 of the remarks that the motivation to combine Chen and Kim is inapplicable because Chen does not use gap-fill material between vertically stacked chips and a person of ordinary skill in the art would have no reason to look to Kim about reducing voids between stacked chips and furthermore wherein the instant application addresses a different problem of preventing the “epoxy on die” phenomenon. The Examiner respectfully disagrees. A person of ordinary skill in the art looking to increase die density by stacking dies in a vertical direction as required by claim 4 which has been cancelled and amended into the limitations of claim 1, would look to attach a second semiconductor die to a first semiconductor die in a manner which reduces or prevents the formation of voids in an underfill material between chips and further prevent procedural defects. Additionally, the same motivation can be applied to the underfill material used to mount a first semiconductor die to an underlying package substrate as disclosed in Chen therefore resulting in a motivation that is further applicable to Chen and Kim. Furthermore, it would be obvious to one of ordinary skill in the art to combine the teachings of Chen with Kim to further provide the well-known advantage of increasing a density of dies in a vertical direction thus increasing manufacturing throughput and keeping up with Moore’s Law.
With respect to Applicant’s arguments on page 6, lines 21-29, page 7, lines 1-29 and page 8, lines 1-17 regarding the 35 U.S.C. 102 rejection to claims 1-3, 6-9 and 16-22, these arguments are not found to be persuasive because the prior art of record, Kim, as previously applied to claim 4 which has been cancelled and amended into the limitations of independent claims 1, 16 and 21, has been applied in the 35 U.S.C. 103 rejection’s to claims 1, 16 and 21 above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights