DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR 10-2023-0032772, filed on 03/13/2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/18/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 13 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 9543912 by Lee.
Regarding claim 1, Lee teaches a buffer circuit for generating an output voltage according to an input voltage (Fig. 1; Abstract), the buffer circuit comprising:
an input stage (Fig. 1 #110) configured to provide a first differential current (Fig. 1 ILD, ILDB) to a load stage (Fig. 1 #130) or receive a second differential current (Fig. 1 ILU, ILUB) from the load stage based on a difference between the input voltage and the output voltage;
the load stage (Fig. 1, 3 #130) configured to apply gate voltages to a first output transistor (Fig. 3 MP8) and a second output transistor (Fig. 3 MN8) of an output stage (Fig. 1, 3, 4 #150) based on the first differential current (ILD, ILDB) or the second differential current (ILU, ILUB);
the output stage (Fig. 1, 3, 4 #150) configured to regulate the output voltage (Fig. 4 Vout) based on the gate voltages applied to the first output transistor (MP8) and the second output transistor (MN8); and
a slew rate compensator (Fig. 1, 5, 6, 7 #160) configured to provide a source current (Fig. 7 ICOMP_PUSH) to the load stage or receive a sink current (Fig. 7 ICOMP_PULL) from the load stage to regulate the gate voltages of the first output transistor and the second output transistor.
Regarding claim 13, Lee teaches the buffer circuit of claim 1, wherein the output stage comprises: a first compensation capacitor (Fig. 4 C1) and a second compensation capacitor (Fig. 4 C2) connected in parallel with an output terminal through which the output voltage is output (Fig. 4 Vout), and the first output transistor (Fig. 4 MP8) and the second output transistor (Fig. 4 MN8) connected in parallel with the output terminal (Vout).
Claim(s) 1, 10, and 13 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 20220383823 by Lee.
Regarding claim 1, Lee teaches a buffer circuit for generating an output voltage according to an input voltage (Fig. 2; Abstract), the buffer circuit comprising:
an input stage (Fig. 2 #11) configured to provide a first differential current (Ipll0 and Ippli) to a load stage (Fig. 2 #14) or receive a second differential current (Ipsli and Ipslo) from the load stage based on a difference between the input voltage and the output voltage;
the load stage (Fig. 3 #14) configured to apply gate voltages to a first output transistor (Fig. 3 P10) and a second output transistor (Fig. 3 N10) of an output stage (fig. 2, 3, #15) based on the first differential current or the second differential current;
the output stage (Fig. 3 #15) configured to regulate the output voltage (Fig. 3 Vout) based on the gate voltages applied to the first output transistor (P10) and the second output transistor (N10); and
a slew rate compensator (Fig. 2 #20) configured to provide a source current to the load stage (Fig. 2 Ipush) or receive a sink current from the load stage (Fig. 2 Ipull) to regulate the gate voltages of the first output transistor (P10) and the second output transistor (N10).
Regarding claim 10, Lee teaches the buffer circuit of claim 1, wherein the load stage comprises:
a first differential mirror circuit configured to have a current mirror structure and a cascode structure and mirror the second differential current and the sink current (Fig. 3 shows the first differential mirror current PS which mirros Ipsli, Ipslo; Fig. 8 also shows a configuration in which the sink current Ipull is connected to node NU1 which is the node connected to the mirror current PS);
a second differential mirror circuit configured to have a current mirror structure and a cascode structure and mirror the first differential current and the source current (Fig. 3 shows the second differential mirror current PL which mirrors Iplli and Ipllo; Fig. 8 also shows a configuration in which the source current Ipush is connected to node NL1 which is the node connected to the mirror current PL); and
a third bias circuit and a fourth bias circuit connected between the first differential mirror circuit and the second differential mirror circuit and configured to control a static state operation and an amplification operation of the first differential mirror circuit and the second differential mirror circuit (Fig. 3 P8, N8 and P9, N9).
Regarding claim 13, Lee teaches the buffer circuit of claim 1, wherein the output stage comprises:
a first compensation capacitor (Fig. 3 C1) and a second compensation capacitor (Fig. 3 C2) connected in parallel with an output terminal (Nout) through which the output voltage (Vout) is output, and
the first output transistor(P10) and the second output transistor (N10) connected in parallel with the output terminal (Nout, Vout).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-10 and 14-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 6-10, 12, 14, and 18-20 of copending Application No. 18/904,388. Although the claims at issue are not identical, they are not patentably distinct from each other because they both refer to the same field of invention: a buffer circuit for generating an output voltage according to an input voltage.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
The following chart maps the claims of this application with the copending application:
Current Application 18/468,909
Copending application 18/904,388
Claim 1
Claim 1
Claim 2
Claim 1
Claim 3
Claim 3
Claim 4
Claim 6
Claim 5
Claim 8
Claim 6
Claim 8
Claim 7
Claim 7
Claim 8
Claim 7
Claim 9
Claim 3
Claim 10
Claim 9
Claim 14
Claims 10 and 12
Claim 15
Claim 12
Claim 16
Claim 14
Claim 17
Claim 12
Claim 18
Claims 18, 19, and 20
Claim 19
Claim 19
Claim 20
Claim 20
While certain claims in the copending application have further details, the limitations of the current application can be mapped to limitations in the copending application. Some differences between the current and copending applications include the fact that the copending application has a limitation about a control circuit that the current application does not have.
Allowable Subject Matter
Claims 11 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAREH SHAMIRYAN whose telephone number is (703)756-4616. The examiner can normally be reached M-F: 7:00AM-4:00PM PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren-Baltzell can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NAREH SHAMIRYAN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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