DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 10-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group (II), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5 January 2026.
Applicant’s election without traverse of Group I in the reply filed on 5 January 2026 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 18 September 2023 and 4 February 2025 has been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over HeeJo Chi et al. (US 2013/0087898 A1; hereinafter “Chi”) in view of Tung Lok Li (US 2010/00224971 A1; hereinafter “Li”).
Regarding Claim 1, Chi teaches a method of comprising:
mounting a semiconductor die (180, Fig. 11, para [0062] describes a semiconductor die 180) on a die pad of a leadframe (124 and 130, Fig. 11, para [0062] describes mounting semiconductor die 180 on a die pad 130 of leadframe 124), the die pad having a central opening configured to expose a central portion of the semiconductor die (130, Fig. 11 depicts an opening between die pads 130 of the leadframe 124 wherein a second semiconductor die 134 is disposed in said opening);
attaching a first end of a bond wire to a bond pad of the semiconductor die (188 and 190, Fig. 11, para describes attaching a bond wire 190 to a bond pad 188 of the semiconductor die 180) and a second end of the bond wire to a lead of the leadframe (190 and 128, Fig. 11, para [0063] describes attaching a second end of the bond wire 190 to a lead 128 of the leadframe 124); and
encapsulating with an encapsulant the semiconductor die and the leadframe (192, Fig. 11, para [0064] describes depositing an encapsulant 192 over the leadframe and semiconductor die 180), a portion of the lead and a portion of the die pad exposed through the encapsulant (130 and 128, Fig. 11 depicts wherein a portion of the lead 128 and die pad 130 are exposed at a surface of the encapsulant where interconnect structure 156 is formed).
Chi fails to explicitly disclose a portion of the lead and a portion of the die pad protruded through the encapsulant.
However, Li teaches a similar method comprising a portion of the lead and a portion of the die pad protruded through the encapsulant (L and DP, annotated Fig. 10B, para [0055] describes an encapsulant 1008 encapsulating a portion of a lead L and die pads DP wherein leads L and die pads DP protrude through the encapsulant 1008 as shown in annotated Fig. 10B).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chi with Li to further disclose a method wherein a portion of leads and die pads of a leadframe protrude through an encapsulant in order to provide the advantage of providing contacts which are isolated from each other so that they may pass signals to and from an external components such as a second semiconductor chip or printed circuit board and to provide non-isolated areas of a leadframe that may be used to ground the semiconductor chip (Li, para [0053], para [0055] and para [0009]).
Claims 2-9 are rejected under 35 U.S.C. 103 as being unpatentable over HeeJo Chi et al. (US 2013/0087898 A1; hereinafter “Chi”) in view of Tung Lok Li (US 2010/0224971 A1; hereinafter “Li”) and in further view of Changjun et al. (US 2017/0250172 A1; hereinafter “Huang”).
Regarding Claim 2, the combination of Chi and Li discloses the method of claim 1, further comprising before encapsulating with the encapsulant, interconnecting a component located within the central opening (134, Fig. 6K and Fig. 11, para [0051] describes mounting a component 134 before encapsulating with an encapsulant 150 wherein Fig. 11 depicts wherein component 134 is interconnected within the central opening of the leadframe 124).
The combination of Chi and Li fails to explicitly disclose the method of claim 1 further comprising interconnecting a component located within the central opening with a through-silicon via (TSV) of the semiconductor die.
However, Huang teaches a similar method, further comprising interconnecting a component located within the central opening with a through-silicon via (TSV) of the semiconductor die (132, Fig. 9, para [0036] describes interconnecting a first semiconductor die 124b and second semiconductor die 124a through conductive TSV 132 of the first semiconductor die 124b).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chi and Li with Huang to further disclose a method wherein a TSV is used to interconnect a first semiconductor die to a component in order to provide the advantage of enabling die stacking with a common interconnect structure so as to allowing discharge of electrical current from chips through interconnects to ground in the event of an incident voltage spike (Huang, para [0040] and para [0041]).
Regarding Claim 3, the combination of Chi, Li and Huang discloses the method of claim 2, wherein the component located within the central opening is interconnected with the TSV by way of a redistribution layer formed on the semiconductor die (Huang, 134, Fig. 9, para [0026] describes a redistribution layer 134 formed on semiconductor die 124b connected with TSV 132).
Regarding Claim 4, the combination of Chi, Li and Huang discloses the method of claim 2, wherein a bottom portion of the component protrudes through the encapsulant after encapsulating with the encapsulant (Chi, 134, Fig. 11 depicts wherein component 134 is planar with a lower surface of leadframe 124 wherein upon combining the leadframe of Chi with the leadframe of Li, a bottom portion of the component 134 of Chi would be planar with a bottom portion of the leadframe of Li and protrude through a bottom surface of the encapsulant 192).
Regarding Claim 5, the combination of Chi, Li and Huang discloses the method of claim 2, further comprising forming a metal layer on a bottom side of the component (Chi, Fig. 11, para [0054] describes forming a conductive layer 158 on contact pads 136 of a bottom side of component 134).
Regarding Claim 6, the combination of Chi, Li and Huang discloses the method of claim 2, wherein the component is characterized as at least one of a second semiconductor die and a passive integrated device (PID) (134, Fig. 11, para [0050] describes wherein component 134 may be a semiconductor die comprised of integrated passive components IPDs such as inductors, capacitors and resistors).
Regarding Claim 7, the combination of Chi, Li and Huang discloses the method of claim 2, wherein a bottom surface of the component is substantially coplanar with a bottom surface of the die pad (Chi, 130 and 134, Fig. 6g and Fig. 11, para [0050] describes wherein a bottom surface of the component 134 and bottom surface of the contact pads 130 are formed on a temporary adhesive layer resulting in bottom surface of the component 134 and a bottom surface of the contact pads 130 being substantially coplanar).
Regarding Claim 8, the combination of Chi, Li and Huang discloses the method of claim 1, wherein the central opening of die pad is configured to expose the central portion of a backside of the semiconductor die (Chi, 182, Fig. 11, para [0063] describes wherein a back surface 182 of the semiconductor die 180 is oriented toward the opening in leadframe 124).
Regarding Claim 9, the combination of Chi, Li and Huang discloses the method of claim 1, wherein the leadframe is characterized as a quad flat no-lead (QFN) package type leadframe (Li, Fig. 12A-Fig. 12H, para [0057] describes wherein the IC packages comprising a leadframe may use a quad flat no lead QFN package as shown in Fig. 12A – Fig. 12C).
Claims 16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over HeeJo Chi et al. (US 2013/0087898 A1; hereinafter “Chi”) in view of Changjun et al. (US 2017/0250172 A1; hereinafter “Huang”).
Regarding Claim 16, Chi teaches a method of comprising:
mounting a semiconductor die (180, Fig. 11, para [0062] describes a semiconductor die 180) on a die pad of a leadframe (124 and 130, Fig. 11, para [0062] describes mounting semiconductor die 180 on a die pad 130 of leadframe 124), the die pad having a central opening exposing a backside portion of the semiconductor die (130, Fig. 11 depicts an opening between die pads 130 of the leadframe 124 wherein a backside portion 182 of semiconductor die 180 is exposed in said opening facing a semiconductor die 134 disposed in said opening);
attaching a first end of a bond wire to a bond pad of the semiconductor die (188 and 190, Fig. 11, para describes attaching a bond wire 190 to a bond pad 188 of the semiconductor die 180) and a second end of the bond wire to a lead of the leadframe (190 and 128, Fig. 11, para [0063] describes attaching a second end of the bond wire 190 to a lead 128 of the leadframe 124);
interconnecting a component, the component located substantially within the central opening of the die pad (134, Fig. 11, para [0063] describes a second semiconductor die 134 disposed in the opening of the leadframe 124 between die pads 130); and
encapsulating with an encapsulant the semiconductor die, the leadframe, and the component (192, Fig. 11, para [0064] describes depositing an encapsulant 192 over the leadframe, semiconductor die 180 and component 134).
Chi fails to explicitly disclose interconnecting a component with a through-silicon via (TSV) of the semiconductor die.
However, Huang teaches a similar method, further comprising interconnecting a component with a through-silicon via (TSV) of the semiconductor die (132, Fig. 9, para [0036] describes interconnecting a first semiconductor die 124b and second semiconductor die 124a through conductive TSV 132 of the first semiconductor die 124b).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chi and Li with Huang to further disclose a method wherein a TSV is used to interconnect a first semiconductor die to a component in order to provide the advantage of enabling die stacking with a common interconnect structure so as to allowing discharge of electrical current from chips through interconnects to ground in the event of an incident voltage spike (Huang, para [0040] and para [0041]).
Regarding Claim 18, the combination of Chi and Huang discloses the method of claim 16, wherein the component located within the central opening is interconnected with the TSV by way of a redistribution layer formed on the semiconductor die (Huang, 134, Fig. 9, para [0026] describes a redistribution layer 134 formed on semiconductor die 124b connected with TSV 132).
Regarding Claim 19, the combination of Chi and Huang discloses the method of claim 16, wherein a bottom surface of the component is substantially coplanar with a bottom surface of the die pad (130 and 134, Fig. 6g and Fig. 11, para [0050] describes wherein a bottom surface of the component 134 and bottom surface of the contact pads 130 are formed on a temporary adhesive layer resulting in bottom surface of the component 134 and a bottom surface of the contact pads 130 being substantially coplanar).
Regarding Claim 20, the combination of Chi and Huang discloses the method of claim 16, wherein the component is characterized as at least one of a second semiconductor die and a passive integrated device (PID) (134, Fig. 11, para [0050] describes wherein component 134 may be a semiconductor die comprised of integrated passive components IPDs such as inductors, capacitors and resistors).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over HeeJo Chi et al. (US 2013/0087898 A1; hereinafter “Chi”) in view of Changjun et al. (US 2017/0250172 A1; hereinafter “Huang”) and in further view of Tung Lok Li (US 2010/0224971 A1; hereinafter “Li”).
Regarding Claim 17, the combination of Chi and Huang discloses the method of claim 16, wherein a portion of the lead, a portion of the die pad, and a portion of the component are exposed through the encapsulant (130 and 128, Fig. 11 depicts wherein a portion of the lead 128, die pad 130, and component 134 are exposed at a surface of the encapsulant where interconnect structure 156 is formed).
Chi and Huang fails to explicitly disclose wherein a portion of the lead, a portion of the die pad, and a portion of the component are protruded through the encapsulant.
However, Li teaches a similar method comprising a portion of the lead, a portion of the die pad, and a portion of the component are protruded through the encapsulant (L and DP, annotated Fig. 10B, para [0055] describes an encapsulant 1008 encapsulating a portion of a lead L and die pads DP wherein leads L and die pads DP protrude through the encapsulant 1008 as shown in annotated Fig. 10B further wherein component 134 of Chi is planar with a lower surface of leadframe 124 wherein upon combining the leadframe of Chi with the leadframe of Li, a bottom portion of the component 134 of Chi would be planar with a bottom portion of the leadframe of Li and protrude through a bottom surface of the encapsulant 192).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chi with Li to further disclose a method wherein a portion of leads and die pads of a leadframe protrude through an encapsulant in order to provide the advantage of providing contacts which are isolated from each other so that they may pass signals to and from an external components such as a second semiconductor chip or printed circuit board and to provide non-isolated areas of a leadframe that may be used to ground the semiconductor chip (Li, para [0053], para [0055] and para [0009]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Thursday 7:00 am - 5:00 pm.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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