DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 6-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected Species (B, C and D), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 23 January 2026.
Applicant’s election without traverse of Species A, claims 1-5 in the reply filed on 23 January 2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 18 September 2023 has been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 3-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Qing Cao et al. (US 2016/0293871 A1; hereinafter “Cao”).
Regarding Claim 1, Cao teaches a semiconductor device comprising:
a stack of nanostructure material layers (510, Fig. 12A, para [0058] describes a stack of carbon nanotube structures 510) overlying a substrate (110, Fig. 12A, para [0041] describes a substrate 110 underlying nanostructure material layers 510), wherein a gate all around structure is present on a channel region portion for the stack of nanostructure material layers (1210, Fig. 12A, para [0071] describes a stack of metal gates 1210 comprising a gate all around structure present on a channel region portion of nanostructure material layers 510);
source (610, Fig. 12A, para [0064] describes a source contact 610) and drain semiconductor contacts on each side of the gate all around structure (620, Fig. 12A, para [0064] describes a drain contact 620 wherein source contact 610 and drain contact 620 are on each side of the gate all around structure 1210), the source and drain semiconductor contacts in direct contact with edges of the channel region portion for the stack of nanostructure material layers (Fig. 12A, para [0064] describes wherein source contact 610 and drain contact 620 are in direct contact with each end of the channel region portion of the stack of nanostructure material layers 510);
a gate spacer between the source and drain semiconductor contacts and the gate all around structure (810, Fig. 12A, para [0067] describes a gate dielectric 810 which portions remain between the source contact 610 and drain contact 620 and the gate all around structure 1210 after an etching process); and
an electrically insulating substrate isolation layer aligned to be between the gate all around structure, the gate spacer and the substrate (120, Fig. 12A, para [0058] describes a dielectric material layer 120 aligned between the gate all around structure 1210, the gate spacer 810 and the substrate 110), wherein a base portion of the gate spacer has an L-shaped geometry including a portion that warps over an upper surface of the electrically insulating substrate isolation layer (BP, annotated Fig. 12A depicts a base portion BP of gate spacer 810 comprising an L-shaped geometry including a portion that warps over an upper surface of the electrically insulating substrate isolation layer 120).
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Regarding Claim 3, Cao teaches the semiconductor device of claim 1, wherein the gate spacer is a composite structure including an inner spacer (910, Fig. 12A, para [0068] describes a dielectric gate spacer 910 that may be comprised of a silicon nitride material and is on an inner side of the spacer layer) and an outer spacer of different material compositions (810, Fig. 12A, para [0068] describes wherein remaining portions of sacrificial gate dielectric 810 form an outer spacer of a gate spacer dielectric material layer wherein para [0067] describes a material of the outer spacer 810 may be a silicon oxide based dielectric material, different from a silicon oxide of the inner spacer 910), wherein a first material provides the outer spacer including that at least the base portion of the gate spacer having the L-shaped geometry (BP, annotated Fig. 12A depicts wherein a first material, being silicon oxide as described in para [0067] provides the outer spacer 810 including the base portion having the L-shaped geometry BP), and a second material provides the inner spacer (910, Fig. 12A, para [0068] describes wherein a second material of silicon nitride may provide the inner spacer 910).
Regarding Claim 4, Cao teaches the semiconductor device of claim 3, wherein the second material that provides the inner spacer (910, Fig. 12A, para [0068] describes wherein a second material of silicon nitride may provide the inner spacer 910) provides a material composition for the electrically insulating substrate isolation layer (120, Fig. 12A, para [0043] describes wherein the electrically insulating substrate isolation layer 120 may be comprised of the second material, silicon nitride).
Regarding Claim 5, Cao teaches the semiconductor device of claim 1, wherein the source and drain semiconductor contacts are not confined by dielectric sidewalls (610 and 620, Fig. 12A, para [0064] describes wherein the source contact 610 and drain contact 620 are formed directly on the nanostructure material layers 510 at a sidewall of the source contact 610 and drain contact 620 resulting in source and drain semiconductor contacts not being confined by dielectric sidewalls).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Qing Cao et al. (US 2016/0293871 A1; hereinafter “Cao”) in view of Jihye Yi et al. (US 2020/0373391 A1; hereinafter “Yi”).
Regarding Claim 2, Cao discloses all the limitations of claim 1.
Cao fails to explicitly disclose the semiconductor device of claim 1, wherein electrically insulating isolation layer is a self-aligned substrate isolation (SASI) layer.
However, Yi discloses a similar semiconductor device, wherein electrically insulating isolation layer is a self-aligned substrate isolation (SASI) layer (155, Fig. 5A, para [0039] describes an isolation film 155 disposed between the active region of the substrate and the lowermost channel layers, wherein Fig. 4A, 4B, 4C and 5A depicts wherein the isolation film 155 is an isolation layer that is self-aligned with the channel and gate stack and further includes self-aligned internal insulating spacers 154 as described in para [0018]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Cao with Yi to further disclose a semiconductor device wherein a substrate isolation layer may be a self-aligned substrate isolation layer in order to provide the advantage of enhancing electrical isolation from a substrate and a gate stack (Yi, para [0018]) as well as applying a known technique such as self-aligned processing of a semiconductor layer, to a known device such as a gate all around semiconductor device, ready for improvement to yield predictable results.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Thursday 7:00 am - 5:00 pm.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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