DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to claim 1 in the Applicant’s response dated 16 July 2026. The claim amendment has been addressed below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Qing Cao et al. (US 2016/0293871 A1; hereinafter “Cao”) in view of Nicolas Loubet et al. (US 2020/0105869 A1; hereinafter “Loubet”).
Regarding Claim 1, Cao teaches a semiconductor device comprising:
a stack of nanostructure material layers (510, Fig. 12A, para [0058] describes a stack of carbon nanotube structures 510) overlying a substrate (110, Fig. 12A, para [0041] describes a substrate 110 underlying nanostructure material layers 510), wherein a gate all around structure is present on a channel region portion for the stack of nanostructure material layers (1210, Fig. 12A, para [0071] describes a stack of metal gates 1210 comprising a gate all around structure present on a channel region portion of nanostructure material layers 510);
source (610, Fig. 12A, para [0064] describes a source contact 610) and drain semiconductor contacts on each side of the gate all around structure (620, Fig. 12A, para [0064] describes a drain contact 620 wherein source contact 610 and drain contact 620 are on each side of the gate all around structure 1210), the source and drain semiconductor contacts in direct contact with edges of the channel region portion for the stack of nanostructure material layers (Fig. 12A, para [0064] describes wherein source contact 610 and drain contact 620 are in direct contact with each end of the channel region portion of the stack of nanostructure material layers 510);
a gate spacer between the source and drain semiconductor contacts and the gate all around structure (810, Fig. 12A, para [0067] describes a gate dielectric 810 which portions remain between the source contact 610 and drain contact 620 and the gate all around structure 1210 after an etching process); and
an electrically insulating substrate isolation layer aligned to be between the gate all around structure, the gate spacer and the substrate (120, Fig. 12A, para [0058] describes a dielectric material layer 120 aligned between the gate all around structure 1210, the gate spacer 810 and the substrate 110), wherein a base portion of the gate spacer has an L-shaped geometry including a first portion that wraps over and is in contact with an upper surface of the electrically insulating substrate isolation layer (BP, annotated Fig. 12A depicts a base portion BP of gate spacer 810 comprising an L-shaped geometry including a portion BP that wraps over and is in contact with an upper surface of the electrically insulating substrate isolation layer 120).
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Cao fails to explicitly teach wherein the L-shaped geometry further including a second portion extending downward from the first portion towards the substrate.
However, Loubet teaches a similar semiconductor device, comprising:
an electrically insulating substrate isolation layer aligned to be between the gate all around structure, the gate spacer and the substrate (1050, Fig. 12A, para [0083] describes an air gap 1050 aligned to be between the gate all around structure 1204, at least a portion of a gate spacer 1002 and a substrate 202 wherein the air gap 1050 constitutes an electrically insulating substrate isolation layer), wherein a base portion of the gate spacer has an L-shaped geometry (FP2, SP2 and 1002, annotated Fig. 12B, para [0083] describes a gate spacer material 1002 including a base portion FP2 and SP2 having an L-shaped geometry wherein Fig. 12B shows a cut along line Y of a same semiconductor device 100 as Fig. 12A) including a first portion that wraps over and is in contact with an upper surface of the electrically insulating substrate isolation layer (1050, FP2, annotated Fig. 12B depicts a first portion FP2 of the base portion FP2 and SP2 of the gate spacer layer 1002 that wraps over and is in contact with an upper surface of the electrically insulating substrate isolation layer 1050), the L-shaped geometry further including a second portion extending downward from the first portion towards the substrate (SP2 and 202, annotated Fig. 12B depicts a second portion SP2 of the base portion FP2 and SP2 of the gate spacer layer 1002 extending downward from the first portion FP2 towards the substrate 202).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Cao with Loubet to further disclose a semiconductor device wherein a base portion of a gate spacer has an L-shaped geometry including a first portion that wraps over and is in contact with an upper surface of an electrically insulating substrate isolation layer, the L-shaped geometry further including a second portion extending downward from the first portion towards a substrate in order to provide the advantage of preventing current leakage from one source or drain region to another source or drain region through a substrate which may cause undesirable device characteristics (Loubet, para [0109]) and to further provide the advantage of enabling an air gap to be formed which may physically and electrically separate source and drain regions from a substrate (Loubet, para [0108]).
Regarding Claim 3, the combination of Cao and Loubet teaches the semiconductor device of claim 1, wherein the gate spacer is a composite structure including an inner spacer (Cao, 910, Fig. 12A, para [0068] describes a dielectric gate spacer 910 that may be comprised of a silicon nitride material and is on an inner side of the spacer layer) and an outer spacer of different material compositions (Cao, 810, Fig. 12A, para [0068] describes wherein remaining portions of sacrificial gate dielectric 810 form an outer spacer of a gate spacer dielectric material layer wherein para [0067] describes a material of the outer spacer 810 may be a silicon oxide based dielectric material, different from a silicon oxide of the inner spacer 910), wherein a first material provides the outer spacer including that at least the base portion of the gate spacer having the L-shaped geometry (Cao, BP, annotated Fig. 12A depicts wherein a first material, being silicon oxide as described in para [0067] provides the outer spacer 810 including the base portion having the L-shaped geometry BP), and a second material provides the inner spacer (Cao, 910, Fig. 12A, para [0068] describes wherein a second material of silicon nitride may provide the inner spacer 910).
Regarding Claim 4, the combination of Cao and Loubet teaches the semiconductor device of claim 3, wherein the second material that provides the inner spacer (Cao, 910, Fig. 12A, para [0068] describes wherein a second material of silicon nitride may provide the inner spacer 910) provides a material composition for the electrically insulating substrate isolation layer (Cao, 120, Fig. 12A, para [0043] describes wherein the electrically insulating substrate isolation layer 120 may be comprised of the second material, silicon nitride).
Regarding Claim 5, the combination of Cao and Loubet teaches the semiconductor device of claim 1, wherein the source and drain semiconductor contacts are not confined by dielectric sidewalls (Cao, 610 and 620, Fig. 12A, para [0064] describes wherein the source contact 610 and drain contact 620 are formed directly on the nanostructure material layers 510 at a sidewall of the source contact 610 and drain contact 620 resulting in source and drain semiconductor contacts not being confined by dielectric sidewalls).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Qing Cao et al. (US 2016/0293871 A1; hereinafter “Cao”) in view of Nicolas Loubet et al. (US 2020/0105869 A1; hereinafter “Loubet”) and in further view of Jihye Yi et al. (US 2020/0373391 A1; hereinafter “Yi”).
Regarding Claim 2, the combination of Cao and Loubet discloses all the limitations of claim 1.
Cao and Loubet fail to explicitly disclose the semiconductor device of claim 1, wherein electrically insulating isolation layer is a self-aligned substrate isolation (SASI) layer.
However, Yi discloses a similar semiconductor device, wherein electrically insulating isolation layer is a self-aligned substrate isolation (SASI) layer (155, Fig. 5A, para [0039] describes an isolation film 155 disposed between the active region of the substrate and the lowermost channel layers, wherein Fig. 4A, 4B, 4C and 5A depicts wherein the isolation film 155 is an isolation layer that is self-aligned with the channel and gate stack and further includes self-aligned internal insulating spacers 154 as described in para [0018]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Cao and Loubet with Yi to further disclose a semiconductor device wherein a substrate isolation layer may be a self-aligned substrate isolation layer in order to provide the advantage of enhancing electrical isolation from a substrate and a gate stack (Yi, para [0018]) as well as applying a known technique such as self-aligned processing of a semiconductor layer, to a known device such as a gate all around semiconductor device, ready for improvement to yield predictable results.
Response to Arguments
Applicant’s arguments with respect to claims 1-5 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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